System on chip comprising logic circuitry
阅读说明：本技术 包括逻辑电路的片上系统 (System on chip comprising logic circuitry ) 是由 金珉修 于 2015-12-07 设计创作，主要内容包括：提供一种包括逻辑电路的片上系统。逻辑电路包括：第一组扫描触发器,均被配置为使用无源保持器和有源保持器存储数据；第二组扫描触发器,均被配置为使用有源保持器存储数据；片上时钟控制器,被配置为接收用于驱动逻辑电路的参考时钟,以基于参考时钟的高态间隔产生内部时钟,并且调节内部时钟的占空比以提供调节的内部时钟,片上系统控制器将调节的内部时钟的高态间隔设置为与参考时钟的高态间隔基本相等的水平；以及时钟分布路径,包括：至少一个第一时钟门,被配置为基于调节的内部时钟产生第一时钟并将第一时钟提供给第一组扫描触发器,以及至少一个第二时钟门,被配置为基于调节的内部时钟产生第二时钟并将第二时钟提供给第二组扫描触发器。(A system on a chip including a logic circuit is provided. The logic circuit includes: a first set of scan flip-flops each configured to store data using a passive holder and an active holder; a second set of scan flip-flops each configured to store data using an active keeper; an on-chip clock controller configured to receive a reference clock for driving the logic circuit, to generate an internal clock based on a high interval of the reference clock, and to adjust a duty ratio of the internal clock to provide an adjusted internal clock, the on-chip system controller setting the high interval of the adjusted internal clock to a level substantially equal to the high interval of the reference clock; and a clock distribution path comprising: at least one first clock gate configured to generate a first clock based on the adjusted internal clock and provide the first clock to the first set of scan flip-flops, and at least one second clock gate configured to generate a second clock based on the adjusted internal clock and provide the second clock to the second set of scan flip-flops.)
1. A system on a chip comprising a logic circuit, wherein the logic circuit comprises:
a first set of scan flip-flops each configured to store data using a passive holder and an active holder;
a second set of scan flip-flops each configured to store data using an active keeper;
an on-chip clock controller configured to receive a reference clock for driving the logic circuit, to generate an internal clock based on a high interval of the reference clock, and to adjust a duty ratio of the internal clock to provide an adjusted internal clock, wherein the on-chip system controller sets the high interval of the adjusted internal clock to a level substantially equal to the high interval of the reference clock; and
a clock distribution path comprising:
at least one first clock gate configured to generate a first clock based on the adjusted internal clock and provide the first clock to the first set of scan flip-flops, an
At least one second clock gate configured to generate a second clock based on the adjusted internal clock and to provide the second clock to a second set of scan flip-flops.
2. The system-on-chip as set forth in claim 1,
wherein a level substantially equal to the high interval of the reference clock is equal to or approximately equal to the high interval of the adjusted internal clock.
3. The system on a chip of claim 1, wherein the logic circuit further comprises at least one intellectual property module, some of the first set of scan flip-flops and the second set of scan flip-flops form a scan chain and receive scan data through the scan chain when performing scan tests to detect faults in the at least one intellectual property module.
4. The system-on-chip of claim 1, wherein some of the first set of scan flip-flops comprise:
a multiplexer configured to output one of scan data and normal data in synchronization with a first clock in response to a scan enable signal;
a first latch configured to store one of scan data and normal data using a passive holder;
a second latch configured to store data transmitted from the first latch using the active keeper.
5. The system-on-chip of claim 4, wherein the active keeper comprises a back-to-back inverter.
6. The system on a chip of claim 4, wherein the first latch comprises:
a first element configured to transfer data in synchronization with the adjusted internal clock;
a second element configured to store data transmitted from the first element using the passive holder.
7. The system on a chip of claim 4, wherein the first clock has a return-to-zero form.
8. The system-on-chip of claim 1, wherein some of the first set of scan flip-flops comprise:
a multiplexer configured to output one of scan data and normal data in synchronization with a first clock in response to a scan enable signal;
a first latch configured to store one of scan data and normal data using the active keeper;
a second latch configured to store data transmitted from the first latch using the passive keeper.
9. A system on a chip comprising a logic circuit, wherein the logic circuit comprises:
a first set of flip-flops each configured to store data using a passive keeper and an active keeper;
a second set of scan flip-flops each configured to store data using an active keeper;
an on-chip clock controller configured to receive a reference clock for driving the logic circuit and receive a second clock, to generate an internal clock using the reference clock and the second clock based on a high interval of the reference clock, and to adjust a duty ratio of the internal clock to provide an adjusted internal clock, wherein the on-chip clock controller sets the high interval of the adjusted internal clock to a level substantially equal to the high interval of the reference clock; and
a clock distribution path comprising:
at least one first clock gate configured to generate a first clock based on the adjusted internal clock and provide the first clock to the first set of flip-flops, an
At least one second clock gate configured to generate a second clock based on the adjusted internal clock and to provide the second clock to a second set of scan flip-flops.
10. The system-on-chip as set forth in claim 9,
wherein a level substantially equal to the high interval of the reference clock is equal to or approximately equal to the high interval of the adjusted internal clock.
11. The system on a chip of claim 9, wherein some of the first set of flip-flops comprise:
a first latch configured to store data using a passive keeper;
a second latch configured to store data transmitted from the first latch using the active keeper.
12. The system on a chip of claim 11, wherein the logic circuit further comprises: a scan flip-flop configured to store data using the passive keeper.
13. A system on a chip comprising a logic circuit, wherein the logic circuit comprises:
a clock gate configured to store data using a passive keeper;
an on-chip clock controller configured to receive a reference clock for driving the logic circuit and receive a second clock, to generate an internal clock using the reference clock and the second clock based on a high interval of the reference clock, and to adjust a duty ratio of the internal clock to provide the adjusted internal clock to the clock gate, wherein the on-chip clock controller controls the high interval of the adjusted internal clock to be equal to the high interval of the reference clock,
wherein, the clock gate includes:
a latch configured to store one of a clock enable signal and a scan enable signal using a passive keeper;
and an AND gate configured to perform an AND operation with respect to one of the stored clock enable signal and the scan enable signal and the adjusted internal clock.
14. The system on a chip of claim 13, wherein the latch comprises:
a first element configured to transfer data in synchronization with the adjusted internal clock;
a second element configured to store data transmitted from the first element using the passive holder.
15. The system on a chip of claim 13, wherein the logic circuit further comprises a normal flip-flop configured to store data using the passive keeper and a scan flip-flop configured to store data using the passive keeper.
Technical Field
Embodiments of the inventive concept relate to a system on chip (SoC), and more particularly, to an SoC including an on-chip clock controller for controlling a duty cycle of an internal clock to drive a scan flip-flop using a passive keeper (passive keeper) and a mobile device having the SoC.
Background
With the increasing competition in the mobile device market, the demand for mobile devices having low price, low power consumption, and high performance has increased dramatically. To meet these requirements, it is desirable to reduce or eliminate the design overhead of a system on a chip (SoC).
An example of typical design overhead is test cost. However, when the SoC is not tested, more cost may be required for reliability verification for mass production. Therefore, testing should be considered when designing the SoC.
Disclosure of Invention
Embodiments of the inventive concept provide a system on chip (SoC) with low power consumption and high performance. Other embodiments of the inventive concept provide a mobile device having a SoC.
The technical objects of the inventive concept are not limited to the above disclosure; other objects will become apparent to those of ordinary skill in the art based on the following description.
According to an aspect of the inventive concept, a SoC includes a logic circuit including a scan flip-flop and an on-chip clock controller. The scan flip-flop is configured to store data using the passive keeper. The on-chip clock controller is configured to receive a reference clock for driving the logic circuit, to generate an internal clock based on a high interval of the reference clock, and to provide the internal clock to the scan flip-flop.
The on-chip clock controller may control the high interval of the internal clock to be equal to the high interval of the reference clock.
The logic circuit may further include at least one Intellectual Property (IP) block, and the scan flip-flops may form a scan chain and receive scan data through the scan chain when performing scan tests to detect faults in the at least one IP block. The scan flip-flop may perform normal operation for one clock to detect a failure in the at least one IP block. The scan flip-flop may perform normal operation for two clocks to check a normal operation speed of the at least one IP block.
The scan trigger may include: a multiplexer configured to output one of scan data and normal data in synchronization with an internal clock in response to a scan enable signal; a first latch configured to store one of scan data and normal data using a passive holder; a second latch configured to store data transmitted from the first latch using the active keeper.
The active keeper may include back-to-back inverters. The first latch may include: a first element configured to transfer data in synchronization with an internal clock; a second element configured to store data transmitted from the first element using the passive holder. The internal clock may have a return-to-zero (return-to-zero) form.
The scan trigger may include: a multiplexer configured to output one of scan data and normal data in synchronization with an internal clock in response to a scan enable signal; a first latch configured to store one of scan data and normal data using the active keeper; a second latch configured to store data transmitted from the first latch using the passive keeper. The internal clock may have a return to zero form.
The logic circuit may also include a flip-flop configured to store data using the passive keeper.
According to another aspect of the inventive concept, a SoC includes a logic circuit including a flip-flop and an on-chip clock controller. The flip-flop is configured to store data using the passive keeper. The on-chip clock controller is configured to receive a reference clock for driving the logic circuit, to generate an internal clock based on a high interval of the reference clock, and to provide the internal clock to the flip-flop.
The on-chip clock controller may control the high interval of the internal clock to be equal to the high interval of the reference clock.
The trigger may include: a first latch configured to store data using a passive keeper; a second latch configured to store data transmitted from the first latch using the active keeper.
The first latch may include: a first element configured to transfer data in synchronization with an internal clock; a second element configured to store data transmitted from the first element using the passive holder. The internal clock may have a return to zero form. The active keeper may include back-to-back inverters.
The trigger may include: a first latch configured to store data using an active keeper; a second latch configured to store data transmitted from the first latch using the passive keeper. The internal clock may have a return-to-high (return-to-high) form.
The logic circuit may also include a scan flip-flop configured to store data using the passive keeper.
According to another aspect of the inventive concept, a SoC includes a logic circuit including a clock gate and an on-chip clock controller. The clock gate is configured to store data using a passive keeper. The on-chip clock controller is configured to receive a reference clock for driving the logic circuit, to generate an internal clock based on a high interval of the reference clock, and to provide the internal clock to the clock gate.
The on-chip clock controller may control the high interval of the internal clock to be equal to the high interval of the reference clock.
The clock gate may include: a latch configured to store one of a clock enable signal and a scan enable signal using a passive keeper; and an AND gate configured to perform an AND operation with respect to the stored signal and the internal clock. The latch may include: a first element configured to transfer data in synchronization with an internal clock; a second element configured to store data transmitted from the first element using the passive holder.
The logic circuit may also include a flip-flop configured to store data using the passive keeper and a scan flip-flop configured to store data using the passive keeper.
According to another aspect of the inventive concept, a mobile device includes an application processor having at least one logic circuit including a scan flip-flop and an on-chip clock controller. The scan flip-flop is configured to store data using the passive keeper. The on-chip clock controller is configured to receive a reference clock for driving the logic circuit, to generate an internal clock based on a high interval of the reference clock, and to provide the internal clock to the scan flip-flop.
The on-chip clock controller may control the high interval of the internal clock to be equal to the high interval of the reference clock.
The logic circuit may further include at least one Intellectual Property (IP) block, and the scan flip-flops may form a scan chain and receive scan data through the scan chain when performing scan tests to detect faults in the IP block. The scan flip-flop may perform normal operation for one clock to detect a fault in the IP block. The scan flip-flop can perform normal operation for two clocks to check the normal operation speed of the IP block.
The scan trigger may include: a multiplexer configured to output one of scan data and normal data in synchronization with an internal clock in response to a scan enable signal; a first latch configured to store one of scan data and normal data using a passive holder; a second latch configured to store data transmitted from the first latch using the active keeper.
The active keeper may include back-to-back inverters. The first latch may include: a first element configured to transfer data in synchronization with an internal clock; a second element configured to store data transmitted from the first element using the passive holder. The internal clock may have a return to zero form.
The scan trigger may include: a multiplexer configured to output one of scan data and normal data in synchronization with an internal clock in response to a scan enable signal; a first latch configured to store one of scan data and normal data using the active keeper; a second latch configured to store data transmitted from the first latch using the passive keeper. The internal clock may have a return-to-high form.
According to another aspect of the inventive concept, a synchronization system includes a combinational circuit having at least one logic circuit, a normal flip-flop, a scan flip-flop, and a clock gate. The normal flip-flop is configured to store the data input signal in response to the clock enable signal E and transmit the stored data input signal to the combining circuit. The scan flip-flop is configured to store the data input signal or the scan input signal in response to the scan enable signal SE and transmit the stored data input signal or the stored scan input signal to the combining circuit. The scan flip-flop includes: a multiplexer configured to select one of the data input signal and the scan input signal in response to a scan enable signal SE; a master latch configured to receive and store one of a scan input signal and a data input signal output from the scan multiplexer under the control of an enable clock ECK; a slave latch configured to receive and store one of the stored scan input signal SI and the data input signal D output from the master latch in response to an enable clock ECK. The clock gate is configured to generate the enable clock ECK in synchronization with the clock signal CK to supply the enable clock ECK to the normal flip-flop when the clock enable signal E is enabled and to supply the enable clock ECK to the scan flip-flop when the scan enable signal SE is enabled.
The clock gate may include a pulse latch and an and gate, wherein the pulse latch may store data using an active keeper.
The scan flip-flop may be configured to store the data input signal or the scan input signal data using the passive keeper.
When the scan enable signal SE is enabled, the master latch transmits the received data to the slave latch when the clock signal CK is in a low state, and the slave latch may output the stored data when the clock signal CK is in a high state.
Drawings
Exemplary embodiments of the inventive concept will become more apparent from the following description when taken in conjunction with the accompanying drawings, wherein like reference characters designate the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the inventive concepts. In the drawings:
fig. 1 is a block diagram illustrating a synchronization system according to an embodiment of the inventive concept;
fig. 2A is a circuit diagram illustrating in detail a scan flip-flop according to the related art;
FIG. 2B is a circuit diagram showing in detail a clock gate circuit according to the prior art;
fig. 3A is a circuit diagram illustrating a scan flip-flop according to an embodiment of the inventive concept;
fig. 3B is a circuit diagram illustrating a scan flip-flop according to another embodiment of the inventive concept;
fig. 3C is a circuit diagram illustrating a scan flip-flop according to another embodiment of the inventive concept;
fig. 3D is a circuit diagram illustrating a scan flip-flop according to another embodiment of the inventive concept;
fig. 4A is a circuit diagram illustrating a clock gate according to an embodiment of the inventive concept;
fig. 4B is a circuit diagram illustrating a clock gate according to another embodiment of the inventive concept;
fig. 4C is a circuit diagram illustrating a clock gate according to another embodiment of the inventive concept;
fig. 5 is a block diagram illustrating a logic circuit according to an embodiment of the inventive concept;
fig. 6 is a block diagram illustrating a logic circuit according to another embodiment of the inventive concept;
FIG. 7A is a timing diagram for describing the operation of a scan test to detect a failure of a logic circuit when a slow clock is present;
FIG. 7B is a timing diagram for describing the operation of a scan test to verify normal operation of the logic circuit when a slow clock is present;
FIG. 7C is a timing diagram for describing the normal operation of the logic circuit shown in FIG. 6 when a slow clock is present;
FIG. 8A is a timing diagram for describing the operation of a scan test to detect a failure of a logic circuit when no slow clock is present;
FIG. 8B is a timing diagram for describing the operation of the scan test to verify normal operation of the logic circuit when no slow clock is present;
FIG. 8C is a timing diagram for describing normal operation of the logic circuit shown in FIG. 6 when no slow clock is present;
fig. 9 is a circuit diagram illustrating a scan flip-flop according to another embodiment of the inventive concept;
fig. 10 is a block diagram illustrating a system on chip (SoC) according to an embodiment of the inventive concept;
fig. 11 is a block diagram illustrating an SoC according to another embodiment of the inventive concept;
fig. 12 is a block diagram illustrating an SoC according to another embodiment of the inventive concept;
fig. 13 is a block diagram illustrating a computer system including the logic circuit illustrated in fig. 5 according to an embodiment of the inventive concept;
fig. 14 is a block diagram illustrating a computer system including the logic circuit illustrated in fig. 5 according to another embodiment of the inventive concept;
fig. 15 is a block diagram illustrating a computer system including the logic circuit illustrated in fig. 5 according to another embodiment of the inventive concept;
fig. 16 shows a digital camera apparatus including the logic circuit shown in fig. 5;
fig. 17A to 17C illustrate a wearable device including the logic circuit illustrated in fig. 5.
Detailed Description
Specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the present inventive concepts. That is, the embodiments will be described in detail with reference to the following description and the accompanying drawings. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the concept of the inventive concept to those skilled in the art. Well-known processes, elements, and techniques have not been described for some embodiments.
While the inventive concept is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intention to limit the embodiments to the specific forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the inventive concept.
It will be understood that, although the terms "first," "second," "a," "B," etc. are used herein with respect to elements of the invention, these elements should not be construed as limited by these terms. For example, a first element could be termed a second element, and a second element could be termed a first element, without departing from the scope of the present teachings. As used herein, the term "and/or" includes any and all combinations of one or more of the referents. The term "exemplary" is intended to mean an example or illustration.
It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements (e.g., "between …" and "directly between …", "adjacent" and "directly adjacent", etc.) should be interpreted in a similar manner.
The terminology used herein to describe embodiments of the invention is not intended to limit the scope of the invention. The articles "a," "an," and "the" mean a singular number of a single referent, however, use of the singular herein does not exclude the presence of more than one referent. In other words, a reference to an element of the invention in the singular can total one or more unless the context clearly dictates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, items, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be understood as being conventional in the art to which this invention belongs. It will be further understood that terms, which are commonly used, unless explicitly defined otherwise herein, should also be interpreted as having a meaning that is customary in the relevant art and should not be interpreted ideally or overly formal.
Meanwhile, when any embodiment may be implemented in any other manner, functions or operations indicated in specific blocks may be performed differently from the flows indicated in the flowcharts. For example, two blocks shown in succession may, in fact, perform the function or operation concurrently, and the blocks may sometimes be executed with the same sequence or operation in the reverse order, depending upon the functionality involved.
Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.
Fig. 1 is a block diagram illustrating a synchronization system according to an embodiment of the inventive concept.
Referring to fig. 1, a synchronization system 10 includes a combinational circuit and a storage element. In an embodiment, the storage element may comprise a latch or a flip-flop.
In the depicted embodiment, the synchronization system 10 includes a combinational circuit 11, a plurality of normal flip-flops 12, a plurality of scan flip-flops 13, and a clock gate 14.
The combination circuit 11 may include an AND (AND) gate, a NAND (NAND) gate, an OR (OR) gate, a NOR (NOR) gate, an exclusive OR (XOR) gate, an exclusive NOR (XNOR) gate, a buffer, AND an inverter. More specifically, the combination circuit 11 may include a combination of and gates, nand gates, or gates, nor gates, xor gates, buffers, and inverters, without including latch circuits such as flip-flops or registers.
Each of the normal flip-flops 12 may include two latches connected in series. For example, each of the normal flip-flops 12 may include a master latch and a slave latch. Each of the normal flip-flops 12 may send a data input signal D to the combining circuit 11.
Each of scan flip-flops 13 may include a Multiplexer (MUX) connected to an input and two latches connected in series. For example, each of the scan flip-flops 13 may include a structure in which a MUX, a master latch, and a slave latch are connected in series. Here, the master latch is a first latch, and the slave latch is a second latch.
In response to the scan enable signal SE, the MUX may receive either the scan input signal SI or the data input signal D. Each of the scan flip-flops 13 may transmit the received data to the combining circuit 11. Hereinafter, examples of the scan flip-flop are described in detail with reference to fig. 3A to 3D.
The combination circuit 11 receives the main input data PI and data transmitted from each of the normal flip-flop 12 and the scan flip-flop 13. The combination circuit 11 outputs the main output data PO. The combining circuit 11 also sends the output of the combining circuit 11 to at least one of the normal flip-flop 12 and the scan flip-flop 13.
The clock gate 14 generates an enable clock ECK in response to the clock enable signal E and the scan enable signal SE. The clock gate 14 sends the enable clock ECK to the normal flip-flop 12 or the scan flip-flop 13. Hereinafter, an example of the clock gate 14 is described in detail with reference to fig. 4A to 4C.
The synchronous system 10 may be tested using a scan test operation. During a scan test operation, the scan flip-flop 13 may be converted into a scan chain. For example, scan flip-flop 13 may form a scan chain using respective multiplexers MUX.
During a scan test operation, the scan flip-flop may receive scan data SI through the multiplexer MUX. That is, for example, the scan data SI may be transmitted to each of the scan flip-flops 13 using a serial shift method.
During scan test operations, the synchronous system 10 may perform normal operations for one clock or two clocks. In addition, the scan chain may be used to output the execution result of the normal operation. For example, in order to detect a failure of the synchronous system 10, the synchronous system 10 may perform a normal operation for one clock in a scan test operation. Further, in order to verify the normal operation speed of the synchronous system 10, the synchronous system 10 may perform a normal operation for two clocks in a scan test operation.
In one embodiment, the synchronization system 10 may include at least one Intellectual Property (IP) module. Further, the at least one IP block may be implemented using a system on a chip (SoC). When performing scan test to detect a failure in at least one IP block, the scan flip-flop 13 forms a scan chain and receives scan data through the scan chain.
Fig. 2A is a circuit diagram illustrating in detail a scan flip-flop according to the related art.
Referring to fig. 2A, the scan flip-flop 20 includes a scan multiplexer 21, a master latch 22, and a slave latch 23. For example, the scan flip-flop 20 includes a structure in which a scan multiplexer 21, a master latch 22, and a slave latch 23 are successively connected. The master latch 22 may be referred to as a first latch and the slave latch 23 may be referred to as a second latch.
The scan multiplexer 21 may output one of the scan input signal SI and the data input signal D in response to the scan enable signal SE. For example, the scan multiplexer 21 may comprise a general-purpose multiplexer.
Each of master latch 22 and slave latch 23 may store data using an active keeper. The active holder stores data when powered. In an embodiment, the active keeper may comprise a back-to-back inverter. For example, each of master latch 22 and slave latch 23 may store data using an active keeper, thereby storing data when powered.
In contrast, passive keepers may use parasitic capacitors or passive capacitors to store data. That is, the passive holder stores data regardless of the power source. However, in passive holders, the time for storing data is very short. In various embodiments, one or both of master latch 22 and slave latch 23 may store data using a passive keeper. In this case, the master latch 22 (i.e., the first latch) or the slave latch 23 (i.e., the second latch) that stores data using a passive keeper stores data for a very short time regardless of power supply.
In synchronization with the clock signal CK, the master latch 22 receives one of the scan input signal SI and the data input signal D from the scan multiplexer 21. For example, when the clock signal CK is in a high state, the master latch 22 receives one of the scan input signal SI and the data input signal D from the scan multiplexer 21 and stores the received data. When the clock signal CK is in a low state, the master latch 22 sends the received data to the slave latch 23. The slave latch 23 stores the received data. When the clock signal CK is in a high state, the stored data is output from the latch 23. That is, the output Q of the scan flip-flop is the output of the slave latch 23.
Fig. 2B is a circuit diagram showing an example of a clock gate according to the related art in detail.
Referring to fig. 1 and 2B, the clock gate 30 supplies a clock signal to the normal flip-flop 12 and the scan flip-flop 13.
The clock gate 30 comprises a pulse latch 31 and an and gate 32. The pulse latch 31 may store data using an active keeper. For example, the pulse latch 31 may include a transmission gate, a tri-state buffer, and two inverters.
When at least one of the clock enable signal E and the scan enable signal SE is enabled, the clock gate 30 outputs the enable clock ECK in synchronization with the clock signal CK.
Typically, clock gate 30 uses an active keeper to store data. For example, the active keeper may include a back-to-back inverter. The clock gate 30 may store a signal in which at least one of the clock enable signal E and the scan enable signal SE is enabled using an active keeper.
Fig. 3A is a circuit diagram illustrating a scan flip-flop according to an embodiment of the inventive concept.
Referring to fig. 3A, the scan flip-flop 110 includes a scan multiplexer 111, a master latch 112, and a slave latch 113.
The scan multiplexer 111 may comprise the same structure as the scan multiplexer 21 discussed above with reference to fig. 2A. For example, the scan multiplexer 111 may include two tri-state buffers and inverters.
In response to the scan enable signal SE, the scan multiplexer 111 may output any one of the scan input signal SI and the data input signal D. For example, the scan multiplexer 111 may comprise a general purpose multiplexer.
The master latch 112 may store data using a passive keeper. In the depicted example, master latch 112 includes a tri-state buffer and an inverter. In one embodiment, the passive keeper can include a parasitic capacitor. In addition, there may be a parasitic capacitor at the node between the tri-state buffer and the inverter. The master latch 112 may use parasitic capacitors to store data for very short times.
Slave latch 113 may store data using an active keeper. In the depicted example, slave latch 113 includes a transmission gate, a tri-state buffer, and two inverters. The tri-state buffer and inverter in slave latch 113 may be implemented using back-to-back inverters.
In synchronization with the clock signal CK, the master latch 112 receives one of the scan input signal SI and the data input signal D from the scan multiplexer 111. For example, when the clock signal CK is in a high state, the master latch 112 receives one of the scan input signal SI and the data input signal D from the scan multiplexer 111 and stores the received data. When the clock signal CK is in a low state, the master latch 112 transmits the received data to the slave latch 113. The slave latch 113 stores the received data. When the clock signal CK is in a high state, the stored data is output from the latch 113. That is, the output Q of the scan flip-flop 110 is the output of the slave latch 113.
Because the master latch 112 uses a passive keeper, the scan flip-flop 110 can be operated using only a high frequency clock. However, the scan test operation may be operated using only the low frequency clock. Accordingly, in order to operate the scan flip-flop 110 according to an embodiment of the inventive concept, the scan flip-flop 110 receives a clock whose duty cycle is adjusted. Hereinafter, an example of timing for adjusting the duty cycle of the clock is described with reference to fig. 7A to 8C.
Fig. 3B is a circuit diagram illustrating a scan flip-flop according to another embodiment of the inventive concept.
Referring to fig. 3B, the scan flip-flop 120 includes a scan multiplexer 121, a master latch 122, and a slave latch 123.
Scan multiplexer 121 may include the same structure as scan multiplexer 21 shown in fig. 2A. In the depicted example, scan multiplexer 121 includes two tri-state buffers and inverters.
In response to the scan enable signal SE, the scan multiplexer 121 may output one of the scan input signal SI and the data input signal D. In the depicted example, scan multiplexer 121 comprises a general purpose multiplexer.
The master latch 122 may store data using a passive keeper. In the depicted example, the master latch 122 includes a transmission gate and an inverter. In one embodiment, the passive keeper can include a parasitic capacitor. In addition, there may be a parasitic capacitor at the node between the transmission gate and the inverter. The master latch 122 may store data for a very short time using parasitic capacitors.
Slave latch 123 may store data using an active keeper. In the depicted example, the slave latch 123 includes a transmission gate, a tri-state buffer, and two inverters. The tri-state buffer and inverter in the slave latch 123 may be implemented using back-to-back inverters.
In synchronization with the clock signal CK, the master latch 122 receives one of the scan input signal SI and the data input signal D from the scan multiplexer 121.
For example, when the clock signal CK is in a high state, the master latch 122 receives one of the scan input signal SI and the data input signal D from the scan multiplexer 121 and stores the received data. When the clock signal CK is in a low state, the master latch 122 transmits the received data to the slave latch 123. The slave latch 123 stores the received data. When the clock signal CK is in a high state, the stored data is output from the latch 123. That is, the output Q of the scan flip-flop 120 is the output of the slave latch 123.
Fig. 3C is a circuit diagram illustrating a scan flip-flop according to another embodiment of the inventive concept.
Referring to fig. 3C, the scan flip-flop 130 includes a scan multiplexer 131, a master latch 132, and a slave latch 133.
The scan multiplexer 131 may include the same structure as the scan multiplexer 21 shown in fig. 2A. For example, the scan multiplexer 131 may include two tri-state buffers and inverters.
The scan multiplexer 131 may output one of the scan input signal SI and the data input signal D in response to the scan enable signal SE. For example, the scan multiplexer 131 may include a general-purpose multiplexer.
Master latch 132 may store data using a passive keeper. In the depicted example, master latch 132 includes a tri-state buffer and an inverter. In one embodiment, the passive keeper can include a parasitic capacitor. In addition, there may be a parasitic capacitor at the node between the tri-state buffer and the inverter. The master latch 132 may use parasitic capacitors to store data for very short times.
Slave latch 133 may store data using an active keeper. In the depicted example, slave latch 133 includes a transmission gate, a tri-state buffer, and two inverters. The tri-state buffer and inverter in slave latch 133 may be implemented using back-to-back inverters. The position of one of the two inverters in the slave latch 133 is different from the position of the corresponding inverter shown in fig. 3A and 3B.
In synchronization with the clock signal CK, the master latch 132 receives one of the scan input signal SI and the data input signal D from the scan multiplexer 131.
For example, when the clock signal CK is in a low state, the master latch 132 receives one of the scan input signal SI and the data input signal D from the scan multiplexer 131 and stores the received data. When the clock signal CK is in a high state, the master latch 132 transmits the received data to the slave latch 133. The slave latch 133 stores the received data. When the clock signal CK is in a high state, the stored data is output from the latch 133. That is, the output Q of the scan flip-flop 130 is the output of the slave latch 133.
Fig. 3D is a circuit diagram illustrating a scan flip-flop according to another embodiment of the inventive concept.
Referring to fig. 3D, the scan flip-flop 140 includes a master latch 141 including a multiplexer and a slave latch 142.
Master latch 141 may store data using a passive keeper. In the depicted example, master latch 141 includes five PMOS transistors, ten NMOS transistors, and an nor gate.
Slave latch 142 may store data using an active keeper. In the depicted example, the slave latch 142 includes three PMOS transistors, three NMOS transistors, and an inverter.
In response to the scan enable signal, the master latch 141 receives one of the scan input signal SI and the data input signal D in synchronization with the clock signal CK.
For example, when the clock signal CK is in a high state, the main latch 141 receives one of the scan input signal SI and the data input signal D and stores the received data. When the clock signal CK is in a low state, the master latch 141 transmits the received data to the slave latch 142. The slave latch 142 stores the received data. When the clock signal CK is in a high state, the stored data is output from the latch 142. That is, the output QN of the scan flip-flop 140 is the inverted output of the slave latch 142.
It is apparent that the scan flip-flop 140 can theoretically operate with the first PMOS transistor 141a and the second PMOS transistor 141b outside the circuit. However, the first and second PMOS transistors 141a and 141b may be included in the scan flip-flop 140 (as shown in fig. 3D) so that the scan flip-flop 140 may stably operate.
Fig. 4A is a circuit diagram illustrating a clock gate according to an embodiment of the inventive concept.
Referring to fig. 1 and 4A, the clock gate 210 includes a pulse latch 211 and an and gate 212.
For example, the pulse latch 211 may include the same structure as the master latches 112, 122, and 132 shown in fig. 3A through 3C. Pulse latch 211 may store data using a passive keeper. For example, the pulse latch 211 shown in fig. 4A includes a transmission gate and two inverters.
The pulse latch 211 may store any one of the clock enable signal E and the scan enable signal SE in synchronization with the clock signal CK. The pulse latch 211 may transmit any one of the clock enable signal E and the scan enable signal SE to the and gate 212.
The and gate 212 performs an and operation with respect to the clock signal CK and the data stored in the pulse latch 211. And gate 212 outputs the result of the operation as an enable clock ECK. In one embodiment, and gate 212 may be implemented with a nand gate and an inverter.
Because pulse latch 211 uses a passive keeper, clock gate 210 may operate only at high frequency clocks. However, the scan operation may be operated only at a low frequency clock. Accordingly, in order to operate the clock gate 210 according to an embodiment of the inventive concept, the clock gate 210 may receive a clock whose duty cycle is adjusted.
Fig. 4B is a circuit diagram illustrating a clock gate according to another embodiment of the inventive concept.
Referring to fig. 1 and 4B, a clock gate 220 according to another embodiment of the inventive concept includes a pulse latch 221 and an and gate 222.
The pulse latch 221 may include the same structure as the master latches 112, 122, and 132 shown in fig. 3A through 3C. The pulse latch 221 may store data using a passive keeper. For example, the pulse latch 221 shown in fig. 4B includes a tri-state buffer.
The pulse latch 221 may store any one of the clock enable signal E and the scan enable signal SE in synchronization with the clock signal CK. The pulse latch 221 may transmit any one of the clock enable signal E and the scan enable signal SE to the and gate 222.
The and gate 222 may perform an and operation with respect to the clock signal CK and the data stored in the pulse latch 221. The and gate 222 may output the operation result as the enable clock ECK. In one embodiment, and gate 222 may be implemented with a nand gate and an inverter.
Even if the PMOS transistor 221a is not included, the clock gate 220 can theoretically operate. However, the pulse latch 211 may include a PMOS transistor 221a so that the clock gate 220 stably operates.
Fig. 4C is a circuit diagram illustrating a clock gate according to another embodiment of the inventive concept.
Referring to fig. 1 and 4C, the clock gate 230 includes a pulse latch that stores data using a passive keeper. For example, the clock gate 230 may include four PMOS transistors, seven NMOS transistors, an and gate, and an inverter.
The clock gate 230 may store any one of the clock enable signal E and the scan enable signal SE in synchronization with the clock signal CK. In synchronization with the enable signal ECK, the clock gate 230 may output any one of the clock enable signal E and the scan enable signal SE.
The clock gate 230 can theoretically operate even without including the first PMOS transistor 231 and the second PMOS transistor 232. However, the clock gate 230 may include a first PMOS transistor 231 and a second PMOS transistor 232 so that the clock gate 220 stably operates.
Fig. 5 is a block diagram illustrating a logic circuit according to an embodiment of the inventive concept.
Referring to fig. 5, the logic circuit 100 includes a first flip-flop group 101, a second flip-flop group 102, a third flip-flop group 103, and a fourth flip-flop group 104, an on-chip clock controller (OCC)105, and a clock distribution path 106.
For example, the first flip-flop group 101 may include scan flip-flops using a passive holder and an active holder. For example, the first flip-flop group 101 may include the scan flip-flops 110 to 140 illustrated in fig. 3A to 3D.
The second set of flip-flops 102 may include scan flip-flops that use only active holders. For example, the second flip-flop group 102 may include the scan flip-flop 20 shown in fig. 2A.
Similarly, the third trigger set 103 may include triggers using both passive and active holders, and the fourth trigger set 104 may include triggers using only active holders.
The OCC105 supplies a clock to each of the first flip-flop group 101, the second flip-flop group 102, the third flip-flop group 103, and the fourth flip-flop group 104 through a clock distribution path 106. Hereinafter, the OCC105 and the clock distribution path 106 will be described in detail with reference to fig. 6.
In one embodiment, the logic circuit 100 may comprise an Intellectual Property (IP) block. Further, the logic circuit 100 may be implemented in a system on a chip (SoC).
Fig. 6 is a block diagram illustrating a clock distribution path shown in fig. 5 according to an embodiment of the inventive concept.
Referring to fig. 5 and 6, the logic circuit 100 includes a plurality of flip-flops 100a, an OCC105, and a clock distribution path 106.
The clock distribution path 106 may include a plurality of clock gates, such as a first clock gate 106a and a second clock gate 106 b. For example, the first clock gate 106a may store data using a passive keeper and the second clock gate 106b may store data using an active keeper.
For example, the flip-flop 100a may include the first through fourth flip-flops 101 through 104 shown in fig. 5.
OCC105 may receive a first clock signal FCK, a second clock signal SCK, a scan clock signal SC _ CK, and a scan enable signal SE.
The first clock signal FCK is a reference clock. The first clock signal FCK may have a minimum frequency for driving the flip-flop 100 a. The second clock signal SCK is an operation clock of the logic circuit 100. The frequency of the first clock signal SCK may be an integer multiple of the frequency of the second clock signal FCK. The scan clock signal SC _ CK is an operation clock when the logic circuit 100 performs a scan operation. The scan enable signal SE is a signal for enabling a scan operation.
The OCC105 generates the internal clock signal ICK using the first clock signal FCK and the second clock signal SCK. For example, OCC105 may control the high interval of the internal clock signal ICK to be equal to the high interval of the first clock signal FCK. The OCC105 supplies the internal clock ICK to each of the first clock gate 106a and the second clock gate 106 b. In addition, OCC105 may supply the internal clock signal ICK directly to flip-flop 100 a.
When either one of the clock enable signal E and the scan enable signal SE is enabled, each of the first and second clock gates 106a and 106b supplies the internal clock signal ICK to the flip-flop 100 a. For example, the first clock gate 106a may provide the internal clock signal ICK to the first and third flip-flop groups 101 and 103, and the second clock gate 106a may provide the internal clock signal ICK to the second and fourth flip-flop groups 102 and 104.
Fig. 7A is a timing diagram for describing an operation of a scan test for detecting a failure of the logic circuit shown in fig. 6 when a slow clock exists according to an embodiment of the inventive concept.
Referring to fig. 5, 6 and 7A, the first clock signal FCK may have a minimum frequency for operating each of the first clock gate 106a, the first flip-flop group 101 and the third flip-flop group 103. The second clock signal SCK may have a minimum frequency for operating the logic circuit 100.
The first clock signal FCK may have a higher frequency than the second clock signal SCK. In one embodiment, the frequency of the first clock signal SCK may be an integer multiple of the frequency of the second clock signal FCK. The scan clock signal SC _ CK may have a frequency lower than that of the second clock signal SCK.
When the scan enable signal SE is enabled (i.e., the scan enable signal SE transitions to a low state), the logic circuit 100 performs a scan operation.
The OCC105 generates an internal clock signal ICK supplied to a scan flip-flop using a passive keeper. The OCC105 supplies the internal clock signal ICK to the first clock gate 106a and the second clock gate 106 b. Each of the first clock gate 106a and the second clock gate 106b supplies the internal clock signal ICK to the flip-flop 100 a.
The scan operation may be operated only at a low frequency clock. Accordingly, OCC105 may adjust the duty cycle for the high interval of the internal clock signal ICK. For example, the OCC105 may control the duty cycle for the high interval of the internal clock signal ICK to be equal to the duty cycle for the high interval of the first clock signal FCK.
When the scan enable signal SE is enabled, the logic circuit 100 performs a normal operation for one clock to detect a malfunction of the logic circuit 100.
Fig. 7B is a timing diagram for describing an operation of a scan test for measuring a normal operation speed of the logic circuit shown in fig. 6 when a slow clock exists according to an embodiment of the inventive concept.
Referring to fig. 6 and 7B, the OCC105 generates an internal clock signal ICK supplied to a scan flip-flop using a passive keeper. The OCC105 supplies the internal clock signal ICK to the first clock gate 106a and the second clock gate 106 b. Each of the first clock gate 106a and the second clock gate 106b supplies the internal clock signal ICK to the flip-flop 100 a.
The scan operation may be operated only at a low frequency clock. Accordingly, OCC105 may adjust the duty cycle for the high interval of the internal clock signal ICK. For example, the OCC105 may control the duty cycle for the high interval of the internal clock signal ICK to be equal to the duty cycle for the high interval of the first clock signal FCK.
When the scan enable signal SE is enabled, the logic circuit 100 performs a normal operation for two clocks to measure a normal operation speed of the logic circuit 100.
Fig. 7C is a timing diagram for describing a normal operation of the logic circuit shown in fig. 6 when a slow clock exists according to an embodiment of the inventive concept.
Referring to fig. 6 and 7C, the OCC105 generates an internal clock signal ICK supplied to a scan flip-flop using a passive keeper. The OCC105 supplies the internal clock signal ICK to the first clock gate 106a and the second clock gate 106 b. Each of the first clock gate 106a and the second clock gate 106b supplies the internal clock signal ICK to the flip-flop 100 a.
The OCC105 may control the duty cycle for the high interval of the internal clock signal ICK to be equal to the duty cycle for the high interval of the first clock signal FCK.
When the scan enable signal SE is not enabled, the logic circuit 100 may perform a normal operation. For example, the logic circuit 100 may perform a normal operation in synchronization with the first clock signal FCK or the second clock signal SCK.
Fig. 8A is a timing diagram for describing an operation of a scan test for detecting a malfunction of the logic circuit shown in fig. 6 when a slow clock is not present according to an embodiment of the inventive concept.
Referring to fig. 5, 6, and 8A, the OCC105 generates an internal clock signal ICK supplied to a scan flip-flop using a passive keeper. The OCC105 supplies the internal clock signal ICK to the first clock gate 106a and the second clock gate 106 b. Each of the first clock gate 106a and the second clock gate 106b supplies the internal clock signal ICK to the flip-flop 100 a.
The OCC105 may control the duty cycle for the high interval of the internal clock signal ICK to be equal to the duty cycle for the high interval of the first clock signal FCK.
When the scan enable signal SE is enabled, the logic circuit 100 performs a normal operation for one clock to detect a malfunction of the logic circuit 100.
Fig. 8B is a timing diagram for describing an operation of a scan test for measuring a normal operation speed of the logic circuit shown in fig. 6 when a slow clock is not present according to an embodiment of the inventive concept.
Referring to fig. 6 and 8B, the OCC105 generates an internal clock signal ICK supplied to a scan flip-flop using a passive keeper. The OCC105 supplies the internal clock signal ICK to the first clock gate 106a and the second clock gate 106 b. Each of the first clock gate 106a and the second clock gate 106b supplies the internal clock signal ICK to the flip-flop 100 a.
The OCC105 may control the duty cycle for the high interval of the internal clock signal ICK to be equal to the duty cycle for the high interval of the first clock signal FCK.
When the scan enable signal SE is enabled, the logic circuit 100 performs a normal operation for two clocks to measure a normal operation speed of the logic circuit 100.
Fig. 8C is a timing diagram for describing a normal operation of the logic circuit shown in fig. 6 when there is no slow clock according to an embodiment of the inventive concept.
Referring to fig. 6 and 8C, the OCC105 generates an internal clock signal ICK supplied to a scan flip-flop using a passive keeper. The OCC105 supplies the internal clock signal ICK to the first clock gate 106a and the second clock gate 106 b. Each of the first clock gate 106a and the second clock gate 106b supplies the internal clock signal ICK to the flip-flop 100 a.
The OCC105 may control the duty cycle for the high interval of the internal clock signal ICK to be equal to the duty cycle for the high interval of the first clock signal FCK.
When the scan enable signal SE is not enabled, the logic circuit 100 performs a normal operation. For example, the logic circuit 100 may perform a normal operation in synchronization with the first clock signal FCK.
Fig. 9 is a circuit diagram illustrating a scan flip-flop according to another embodiment of the inventive concept.
Referring to fig. 9, the scan flip-flop 300 includes a scan multiplexer 310, a master latch 320, and a slave latch 330.
Scan multiplexer 310 may comprise the same structure as scan multiplexer 21 shown in fig. 2A. For example, scan multiplexer 310 may include two tri-state buffers and inverters.
The scan multiplexer 310 outputs any one of the scan input signal SI and the data input signal D in response to the scan enable signal SE. For example, scan multiplexer 310 may comprise a general purpose multiplexer.
Master latch 320 may store data using an active keeper. For example, the master latch 320 includes two tri-state buffers and inverters. The tri-state buffers and inverters in the master latch 320 may be implemented with back-to-back inverters.
The slave latch 330 may store data using a passive keeper. For example, the slave latch 330 may include a transmission gate and an inverter. In one embodiment, the passive keeper can include a parasitic capacitor. In addition, there may be a parasitic capacitor at the node between the transmission gate and the inverter. The slave latch 330 may store data during a very short time using a parasitic capacitor.
The scan flip-flop 300 may be operated in synchronization with a clock having a return-to-high (return-to-high) form. In contrast, the scan flip-flop 110 shown in fig. 3A may be operated in synchronization with a clock having a return-to-zero (return-to-zero) form. For example, the internal clock signal ICK shown in fig. 7A to 8C has a return-to-zero form.
Fig. 10 is a block diagram illustrating an SoC according to an embodiment of the inventive concept.
Referring to fig. 10, SoC 410 includes OCC 411 and a first scan flip-flop 412 that stores data using a passive keeper and an active keeper. The OCC 411 may receive the first clock signal FCK, the second clock signal SCK, the scan clock signal SC _ CK, and the scan enable signal SE. The OCC 411 may generate the internal clock signal ICK for driving the first scan flip-flop 412 based on a high interval of the first clock signal FCK.
SoC 410 also includes a first flip-flop 413 that stores data using a passive keeper and an active keeper, a second scan flip-flop 414 that stores data using only an active keeper, and a second flip-flop 415 that stores data using only an active keeper. Each of the first scan flip-flop 412, the first flip-flop 413, the second scan flip-flop 414, and the second flip-flop 415 may operate in synchronization with the internal clock signal ICK.
Fig. 11 is a block diagram illustrating an SoC according to another embodiment of the inventive concept.
Referring to fig. 11, SoC 420 includes an OCC 421 and a first flip-flop 422 that stores data using a passive keeper and an active keeper. OCC 421 may receive a first clock signal FCK, a second clock signal SCK, a scan clock signal SC _ CK, and a scan enable signal SE. The OCC 421 may generate the internal clock signal ICK for driving the first flip-flop 422 based on a high interval of the first clock signal FCK.
SoC 420 also includes a first scan flip-flop 423 that stores data using a passive keeper and an active keeper, a second scan flip-flop 424 that stores data using only an active keeper, and a second flip-flop 425 that stores data using only an active keeper. Each of the first scan flip-flop 422, the first scan flip-flop 423, the second scan flip-flop 424, and the second flip-flop 425 may operate in synchronization with the internal clock signal ICK.
Fig. 12 is a block diagram illustrating an SoC according to another embodiment of the inventive concept.
Referring to fig. 12, the SoC 430 includes an OCC 431 and a first clock gate 432 that stores data using a passive keeper.
OCC 431 may receive a first clock signal FCK, a second clock signal SCK, a scan clock signal SC _ CK, and a scan enable signal SE. The OCC 431 may generate the internal clock signal ICK for driving the first clock gate 432 based on a high interval of the first clock signal FCK.
The SoC 430 also includes a first scan flip-flop 433 that stores data using a passive holder and an active holder, a first flip-flop 434 that stores data using a passive holder and an active holder, and a second clock gate 435 that stores data using only an active holder, a second scan flip-flop 436 that stores data using only an active holder, and a second flip-flop 437 that stores data using only an active holder.
The first clock gate 432 may generate the enable clock ECK using the internal clock signal ICK. That is, when any one of the clock enable signal E and the scan enable signal SE is enabled, the first clock gate 432 may output the internal clock signal ICK as the enable clock ECK. The first clock gate 432 supplies the internal clock signal ICK to the first scan flip-flop 433 and the first flip-flop 434. Each of the first scan flip-flop 433 and the first flip-flop 434 may operate in synchronization with the enable clock ECK supplied from the first clock gate 432.
Likewise, second clock gate 435 may generate enable clock ECK. The second clock gate 435 supplies the enable clock ECK to the second scan flip-flop 436 and the second flip-flop 437. Each of the second scan flip-flop 436 and the second flip-flop 437 may operate in synchronization with an enable clock ECK supplied by the second clock gate 435.
Fig. 13 is a block diagram illustrating a computer system 510 including the logic circuit illustrated in fig. 5 according to an embodiment of the inventive concept.
Referring to fig. 13, a computer system 510 includes a memory device 511, an Application Processor (AP)512 including a memory controller for controlling the memory device 511, a radio transceiver 513, an antenna 514, a display device 515, a touch panel 516, and a TSC 517.
Radio transceiver 513 may send and receive radio signals through antenna 514. For example, radio transceiver 513 may convert radio signals received through antenna 514 into signals that may be processed in AP 512.
Accordingly, the AP 512 may process the signal output from the radio transceiver 513 and transmit the processed signal to the display device 515. In addition, the radio transceiver 513 may convert a signal output from the AP 512 into a radio signal and transmit the converted radio signal to an external device through the antenna 514.
The touch panel 516 is configured to receive a touch signal from a user. The touch panel 516 converts the touch signal into a capacitance variation amount. The touch panel 516 transmits information about the amount of capacitance change to the TSC 517. The TSC 517 converts information about the amount of capacitance change into coordinate information. The TSC 517 transmits the coordinate information to the AP 512. In one embodiment, for example, AP 512 may include logic circuit 100 shown in fig. 5.
Fig. 14 is a block diagram illustrating a computer system 520 including the logic circuit illustrated in fig. 5 according to another embodiment of the inventive concept.
Referring to fig. 14, the computer system 520 may be, for example, a Personal Computer (PC), a web server, a tablet PC, a netbook, an e-reader, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), an MP3 player, or an MP4 player.
The computer system 520 includes a memory device 521, an AP 522 including a memory controller for controlling data processing operations of the memory device 521, a display device 523, a touch panel 524, and a TSC 525.
The touch panel 524 is configured to receive a touch signal from a user. The touch panel 524 converts the touch signal into a capacitance variation amount. The touch panel 524 transmits information regarding the amount of capacitance change to the TSC 525. The TSC525 converts information regarding the amount of capacitance change into coordinate information. The TSC525 sends the coordinate information to the AP 522.
The AP 522 displays data stored in the memory device 521 through the display device 523 based on data input through the touch panel 524. In an embodiment, for example, AP 522 may include logic circuit 100 shown in fig. 5.
Fig. 15 is a block diagram illustrating a computer system 530 including the logic circuit illustrated in fig. 5 according to another embodiment of the inventive concept.
Referring to fig. 15, the computer system 530 may be an image processing apparatus such as a digital camera, a mobile phone on which the digital camera is mounted, a smart phone, or a tablet PC, for example.
The computer system 530 includes a memory device 531, an AP532 including a memory controller for controlling data processing operations (e.g., write operations or read operations) of the memory device 531, an image sensor 533, a display device 534, a touch panel 535, and a TSC 536.
The image sensor 533 converts the optical image into a digital signal, and transmits the converted digital signal to the AP 532. The converted digital signal is displayed through the display device 534 or stored in the memory device 531 under the control of the AP 532. In addition, under the control of the AP532, data stored in the memory device 531 is displayed through the display device 534.
The touch panel 535 is configured to receive a touch signal from a user. The touch panel 535 converts the touch signal into a capacitance variation amount. The touch panel 535 sends information about the amount of capacitance change to the TSC 536. The TSC 536 converts information about the capacitance change amount into coordinate information. The TSC 536 sends the coordinate information to the AP 532. In one embodiment, for example, the AP532 may include the logic circuit 100 shown in fig. 5.
Fig. 16 illustrates a digital camera apparatus 600 including the logic circuit illustrated in fig. 5 according to another embodiment of the inventive concept.
Referring to fig. 16, Android is used for the digital camera device 600TMAnd (5) operating. In various embodiments, for example, digital Camera device 600 may comprise Galaxy CameraTMOr Galaxy Camera2TM。
The digital camera device 600 may include: a touch panel 610 configured to receive a touch input from a user; a TSC for controlling the touch panel 610; an image sensor for acquiring an image or moving an image; and the AP is used for controlling the image sensor. In an embodiment, for example, the digital camera device 600 may include the logic circuit 100 shown in fig. 5.
Fig. 17A to 17C illustrate a wearable device including the logic circuit illustrated in fig. 5 according to an embodiment of the inventive concept.
Referring to fig. 17A and 17C, firstEach of the wearable device 710, the second wearable device 720, and the third wearable device 730 has a wristwatch type. For example, each of the first wearable device 710, the second wearable device 720, and the third wearable device 730 uses AndroidTMOS (operating System) or TIZENTMThe OS operates.
In various embodiments, the first wearable device 710 may comprise Galaxy Gear2TMThe second wearable device 720 may comprise a Galaxy Gear fitTMThe third wearable device 730 may comprise Galaxy Gear STM。
Each of the first wearable device 710, the second wearable device 720, and the third wearable device 730 may include: AP, AndroidTMOperating System (OS) or TIZENTMOperating the OS; an image sensor to collect an image or a moving image; and a display device displaying the photographed image or the moving image.
In an embodiment, for example, each of the first wearable device 710, the second wearable device 720, and the third wearable device 730 may include the logic circuit 100 shown in fig. 5.
The inventive concept is applicable to an SoC including an OCC and a mobile device having the SoC.
An SoC according to an embodiment of the inventive concept may include a logic circuit using a passive keeper. Thus, the SoC can be implemented with a small chip area. In addition, the SoC may be operated with low power consumption. Embodiments of the inventive concept may be implemented in, for example, socs that include OCCs and mobile devices that include socs.
Although the present inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Accordingly, it should be understood that the above embodiments are not limiting, but illustrative.
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