阅读说明：本技术 存储器定期进行bist测试的方法、装置、计算机设备及存储介质 (Method and device for periodically performing BIST test on memory, computer equipment and storage medium ) 是由 王宏伟 张鹏 李湘锦 李华东 于 2020-03-26 设计创作，主要内容包括：本发明涉及存储器定期进行BIST测试的方法、装置、计算机设备及存储介质；其中,方法,包括：对存储器进行预设检测时间周期载入；判断是否到达存储器的检测时间周期；若到达,则启动系统内部BIST对存储器的电路进行检测；判断是否检测到存储器的电路错误；若未检测到,则反馈存储器正常,系统正常工作运行；若检测到,则对存储器进行错误标示。本发明通过在系统中预设BIST电路,周期性在系统上电后测试内部存储器是否正常工作,可以判断和保证存储器电路的性能安全,以保证该存储器在整个生命周期内工作的功能安全,且检测完成时间短、效率高。(The invention relates to a method, a device, computer equipment and a storage medium for periodically carrying out BIST test on a memory; the method comprises the following steps: loading a memory for a preset detection time period; judging whether the detection time period of the memory is reached; if the current time reaches the preset time, starting the BIST in the system to detect the circuit of the memory; judging whether a circuit error of the memory is detected; if not, the feedback memory is normal, and the system works normally; and if so, carrying out error marking on the memory. The invention can test whether the internal memory works normally or not after the system is electrified periodically by presetting the BIST circuit in the system, can judge and ensure the performance safety of the memory circuit so as to ensure the function safety of the memory working in the whole life cycle, and has short detection completion time and high efficiency.)

1. The method for periodically carrying out the BIST test on the memory is characterized by comprising the following steps:

loading a memory for a preset detection time period;

judging whether the detection time period of the memory is reached;

if the current time reaches the preset time, starting the BIST in the system to detect the circuit of the memory;

judging whether a circuit error of the memory is detected;

if not, the feedback memory is normal, and the system works normally;

and if so, carrying out error marking on the memory.

2. The method for periodically performing BIST tests on a memory according to claim 1, wherein the preset test time period in the step of loading the preset test time period into the memory is 1-90 days.

3. The method for periodically performing BIST test on a memory according to claim 1, wherein in the step of determining whether the test time period of the memory has arrived, the counter determines the test time period of the memory by embedding a counter in the memory.

4. The method for periodically performing BIST testing on a memory according to claim 1, wherein the step of "marking the memory with an error if there is an error" further comprises: and repairing or stopping the memory marked with the error.

5. An apparatus for periodically performing BIST testing on a memory, comprising: the device comprises a loading unit, a first judging unit, a detecting unit, a second judging unit, a feedback running unit and a marking unit;

the loading unit is used for loading the memory in a preset detection time period;

the first judging unit is used for judging whether the detection time period of the memory is reached;

the detection unit is used for starting the BIST in the system to detect the circuit of the memory;

the second judging unit is used for judging whether a circuit error of the memory is detected;

the feedback operation unit is used for feeding back that the memory is normal and the system works normally;

the marking unit is used for marking the memory by errors.

6. The apparatus for periodically performing BIST tests on memories according to claim 5, wherein the preset test time period in the load unit is 1-90 days.

7. The apparatus for periodically performing BIST test on a memory according to claim 5, wherein the first judging unit judges the detection time period of the memory by incorporating a counter in the memory.

8. The apparatus for periodically performing BIST test on a memory according to claim 5, wherein the flag cell further comprises: and repairing or stopping the memory marked with the error.

9. A computer device comprising a memory having a computer program stored thereon and a processor that, when executing the computer program, implements a method of periodically conducting a BIST test on a memory as claimed in any of claims 1-4.

10. A storage medium storing a computer program comprising program instructions which, when executed by a processor, implement a method of periodically performing a BIST test for a memory according to any of claims 1-4.

Technical Field

The invention relates to the technical field of memory test, in particular to a method and a device for periodically performing BIST test on a memory, computer equipment and a storage medium.

Background

In board-level application of a product, when a chip is used for a long time, a memory (RAM) unit inside the chip can be in a circuit Failure (Failure) state, so that the functional safety of the chip is damaged, data loss is caused, and even the chip cannot normally work.

In the conventional method, after a chip leaves a factory, a one-time BIST test of a storage unit is performed on a testing machine, a good chip after screening is used for a product, and detection of related circuits is not arranged after board-level work, that is, if a problem of the chip is not known in advance under the board-level application condition. In the board-level application process of the chip, the storage unit can age to cause the chip to fail along with the working time, and statistical data shows that the probability of the failure of the part of circuits is multiple times of the probability of the failure of other circuits; therefore, the existing test cannot meet the requirement.

Disclosure of Invention

It is an object of the present invention to overcome the drawbacks of the prior art and to provide a method, an apparatus, a computer device and a storage medium for performing a BIST test on a memory on a regular basis.

In order to achieve the purpose, the invention adopts the following technical scheme:

the method for periodically carrying out the BIST test on the memory comprises the following steps:

loading a memory for a preset detection time period;

judging whether the detection time period of the memory is reached;

if the current time reaches the preset time, starting the BIST in the system to detect the circuit of the memory;

judging whether a circuit error of the memory is detected;

if not, the feedback memory is normal, and the system works normally;

and if so, carrying out error marking on the memory.

The further technical scheme is as follows: the preset detection time period in the step of loading the preset detection time period into the memory is 1-90 days.

The further technical scheme is as follows: in the step of determining whether the detection time period of the memory has arrived, a counter is built in the memory, and the counter determines the detection time period of the memory.

The further technical scheme is as follows: if there is an error, the step of marking the memory with the error further includes: and repairing or stopping the memory marked with the error.

An apparatus for periodically performing BIST testing of a memory, comprising: the device comprises a loading unit, a first judging unit, a detecting unit, a second judging unit, a feedback running unit and a marking unit;

the loading unit is used for loading the memory in a preset detection time period;

the first judging unit is used for judging whether the detection time period of the memory is reached;

the detection unit is used for starting the BIST in the system to detect the circuit of the memory;

the second judging unit is used for judging whether a circuit error of the memory is detected;

the feedback operation unit is used for feeding back that the memory is normal and the system works normally;

the marking unit is used for marking the memory by errors.

The further technical scheme is as follows: the preset detection time period in the loading unit is 1-90 days.

The further technical scheme is as follows: in the first judgment unit, a counter is built in the memory, and the counter judges the detection time period of the memory.

The further technical scheme is as follows: in the unit that marks, still include: and repairing or stopping the memory marked with the error.

A computer device comprising a memory having a computer program stored thereon and a processor that when executed implements a method of periodically performing a BIST test on a memory as described above.

A storage medium storing a computer program comprising program instructions which, when executed by a processor, implement a method of BIST testing on a periodic basis for a memory as described above.

Compared with the prior art, the invention has the beneficial effects that: the built-in self-test (BIST) circuit is preset in the system, whether the internal memory works normally or not is tested after the system is electrified periodically, the performance safety of the memory circuit can be judged and ensured, the working function safety of the memory in the whole life cycle is ensured, the detection completion time is short, the efficiency is high, and the requirements can be met better.

The invention is further described below with reference to the accompanying drawings and specific embodiments.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a flow chart illustrating a method for periodically performing BIST test on a memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an application scenario of a method for periodically performing BIST test on a memory according to an embodiment of the present invention;

FIG. 3 is a schematic block diagram of an apparatus for periodically performing BIST tests on a memory according to an embodiment of the present invention;

FIG. 4 is a schematic block diagram of a computer device provided by an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Referring to the embodiments shown in fig. 1 to 4, wherein, referring to fig. 1 to 2, the invention discloses a method for periodically performing BIST test on a memory, comprising the following steps:

s1, loading the memory in a preset detection time period;

wherein, before S1, the method further comprises: and powering on the system, and operating. The preset detection time period is 1-90 days, and the detection time period can be set according to actual needs.

S2, judging whether reaching the detection time period of the memory; if not, the operation enters S7, and the system operates normally;

the detection time period of the memory is judged through the counter by arranging the counter in the memory; in the present embodiment, the counter is a watchdog (Watch-Dog) counter.

S3, if the address arrives, starting the BIST in the system to detect the circuit of the memory;

the BIST is a technique for implanting a relevant function circuit in a circuit during design to provide a self-test function, so as to reduce the dependency of device testing on Automatic Test Equipment (ATE).

S4, judging whether the circuit error of the memory is detected;

in this embodiment, if the number of the memories is 100, some or all of the 100 memories are detected according to actual needs.

S5, if not, the feedback memory is normal, and the system works normally;

s6, if it is detected, making error indication for the memory;

wherein, still include: and repairing or stopping the memory marked with the error.

And S7, the system operates normally.

As shown in fig. 2, the invention sets a watchdog (Watch-Dog) counter inside the chip to determine whether the user-defined time of the periodic test is satisfied; if the periodic Test time is met, a start signal with a signal of '1' is generated, the board-level memory (RAM) BIST self-Test is carried out to ensure the functional safety of the built-in memory RAM of the chip, and the output signal of the Test Control is used as the start signal of the ATE Test and is in a normal '0' state under the condition of board-level application.

After the system is powered on, the chip is loaded with the preset detection time in advance, whether the detection time period of the memory is reached is judged, if yes, built-in self test (BIST) is started to carry out circuit check on a plurality of or all RAM (memory) units in the chip, and therefore whether the function Failure (Failure) occurs in the memory unit (RAM) in the chip is judged, and the function safety of the chip working in the whole life Cycle (L ife-Cycle) is ensured.

The built-in self-test check of the embedded memory unit is regularly carried out under the starting state by the built-in self-test (BIST) logic of the chip under the machine test mode, so that the functional safety of the embedded memory unit in the board-level application process of the circuit is ensured. The method can be realized at a board level, and the self-built internal test of the chip can be carried out after the power is on when the conditions are met, so that the completion time is short and the efficiency is high; the configuration time of self-test can be flexibly configured according to the requirement, and the realization method is simple; the multiplexing machine station tests the existing BIST logic, and the area overhead of physical realization is not large; and the chip function safety in the board level application process is ensured.

The method is preliminarily applied to related chips of the SSD control circuit to ensure the functional safety of the built-in RAM unit in a board-level application state, so that the reliability of writing/reading of the data of the solid state disk is ensured; otherwise, the failure of the control circuit can cause the data of the hard disk to be incorrect, so that the normal work of the control chip is ensured at all times in the application process, and the method can be used as an extension of the application, can also be used for periodic testing of any memory unit embedded in the chip and can be used for ensuring the normal work of an internal memory unit.

The built-in self-test (BIST) circuit is preset in the system, whether the internal memory works normally or not is tested after the system is electrified periodically, the performance safety of the memory circuit can be judged and ensured, the working function safety of the memory in the whole life cycle is ensured, the detection completion time is short, the efficiency is high, and the requirements can be met better.

Referring to fig. 3, the present invention also discloses a device for periodically performing BIST test on a memory, including: a loading unit 10, a first judging unit 20, a detecting unit 30, a second judging unit 40, a feedback running unit 50 and a marking unit 60;

the loading unit 10 is configured to load the memory for a preset detection time period;

the first judging unit 20 is used for judging whether a detection time period of the memory is reached;

the detection unit 30 is used for starting the BIST in the system to detect the circuit of the memory;

the second judging unit 40 is configured to judge whether a circuit error of the memory is detected;

the feedback operation unit 50 is used for feeding back that the memory is normal and the system works normally;

the marking unit 60 is used for marking the memory with errors.

Wherein, the preset detection time period in the loading unit 10 is 1-90 days.

In the first determination unit 20, a counter is built in the memory, and the counter determines the detection time period of the memory.

Wherein, in the marking unit 60, further include: and repairing or stopping the memory marked with the error.

It should be noted that, as is clear to those skilled in the art, the device for periodically performing BIST test on the memory and the specific implementation process of each unit may refer to the corresponding description in the foregoing method embodiment, and for convenience and brevity of description, no further description is provided herein.

The means for periodically performing BIST tests on the memory described above may be implemented in the form of a computer program which may be run on a computer device as shown in fig. 4.

Referring to fig. 4, fig. 4 is a schematic block diagram of a computer device according to an embodiment of the present application; the computer device 500 may be a terminal or a server, where the terminal may be an electronic device with a communication function, such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster composed of a plurality of servers.

Referring to fig. 4, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.

The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer programs 5032 include program instructions that, when executed, cause the processor 502 to perform a method for periodic BIST testing of a memory.

The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.

The memory 504 provides an environment for running the computer program 5032 in the non-volatile storage medium 503, and when the computer program 5032 is executed by the processor 502, the processor 502 may be enabled to execute a method for periodically performing BIST test on the memory.

The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the configuration shown in fig. 4 is a block diagram of only a portion of the configuration associated with the present application and does not constitute a limitation of the computer device 500 to which the present application may be applied, and that a particular computer device 500 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

It should be understood that, in the embodiment of the present Application, the Processor 502 may be a Central Processing Unit (CPU), and the Processor 502 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will be understood by those skilled in the art that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program instructing associated hardware. The computer program includes program instructions, and the computer program may be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.

Accordingly, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program comprises program instructions that, when executed by a processor, implement the method for periodically performing a BIST test on a memory as described above.

The storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, which can store various computer readable storage media.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented.

The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be merged, divided and deleted according to actual needs. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a terminal, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.

The technical contents of the present invention are further illustrated by the examples only for the convenience of the reader, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation based on the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.