阅读说明：本技术 X/y应力独立电阻器的跟踪温度补偿 (Tracking temperature compensation of X/Y stress independent resistors ) 是由 M·石泽龙 J·R·托德 T·B·弗利兹 R·P·布里德劳 于 2020-01-10 设计创作，主要内容包括：本申请公开X/Y应力独立电阻器的跟踪温度补偿。集成电路(500)包括具有表面的半导体衬底(570)。横向电阻器布置在平行于衬底的表面的第一平面中。竖直参考电阻器包括层(560),该层(560)布置在平行于衬底的表面并且比第一平面深的第二平面中。掺杂该层以促进电流在第二平面中流动。竖直参考电阻器还包括耦合在该层和衬底的表面之间的第一沟槽(550A)和第二沟槽(550B)。第一沟槽和第二沟槽布置在正交于第一平面和第二平面的竖直方向上,并且被掺杂以阻碍电流在竖直方向上流动。第一沟槽和第二沟槽的横截面绕竖直方向是双重旋转对称的,并且横向电阻器以及第一沟槽和第二沟槽具有相同的温度系数。(The application discloses tracking temperature compensation of X/Y stress independent resistors. An integrated circuit (500) includes a semiconductor substrate (570) having a surface. The lateral resistor is arranged in a first plane parallel to the surface of the substrate. The vertical reference resistor comprises a layer (560), the layer (560) being arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. The layer is doped to facilitate current flow in the second plane. The vertical reference resistor further includes a first trench (550A) and a second trench (550B) coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and second planes and are doped to impede current flow in the vertical direction. The cross-sections of the first and second trenches are doubly rotationally symmetric about the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.)

1. An Integrated Circuit (IC) comprising:

a semiconductor substrate having a surface; and

a reference resistor, comprising:

a first region of a first conductivity type formed in the substrate, wherein the first region extends in a lateral direction parallel to the surface;

a second region of a second conductivity type formed in the substrate and coupled to the first region, wherein the second region extends in a vertical direction perpendicular to the surface, and wherein the second conductivity type is configured to impede current flow in the vertical direction;

a third region of the second conductivity type formed in the substrate and coupled to the first region, wherein the third region extends in the vertical direction;

a first contact structure coupled to the second region and the surface; and

a second contact structure coupled to the third region and the surface, wherein the reference resistor is dual rotationally symmetric about the vertical direction.

2. The IC of claim 1, wherein the first contact structure and an inner side of the second region are separated from the second contact structure and an outer side of the third region by an isolation structure.

3. The IC of claim 1, wherein a cross-section of the third region and the second contact structure is pinhole-shaped.

4. The IC of claim 1, wherein the second conductivity type is n-doped.

5. The IC of claim 1, wherein the IC includes a second resistor, and wherein the second conductivity type has a same temperature coefficient as a conductivity type of the second resistor.

6. The IC of claim 5, wherein a conductivity type of the second resistor is the second conductivity type.

7. The IC of claim 1, wherein the semiconductor substrate is a p-type silicon substrate.

8. An Integrated Circuit (IC) comprising:

a semiconductor substrate having a surface;

a lateral resistor arranged in a first plane parallel to the surface; and

a vertical reference resistor, comprising:

a layer arranged in a second plane parallel to the surface and deeper than the first plane, the layer having a doping configured to facilitate current flow in the second plane, an

A first trench and a second trench coupled between the layer and the surface and arranged in a vertical direction orthogonal to the first plane and the second plane, the first trench and the second trench having a doping configured to impede current flow in the vertical direction,

wherein a cross section of the first trench and the second trench is doubly rotationally symmetric about the vertical direction, and wherein the first trench and the second trench have the same temperature coefficient as the lateral resistor.

9. The IC of claim 8, wherein an inner side of the first trench is separated from an outer side of the second trench by an isolation structure.

10. The IC of claim 8, wherein a cross-section of the second trench is pinhole-shaped.

11. The IC of claim 8, wherein the first trench and the second trench are sidewall doped.

12. The IC of claim 8, wherein the first trench and the second trench are n-doped.

13. The IC of claim 8, wherein the lateral resistor is L-shaped in cross-section, the lateral resistor comprising:

a first element; and

a second element coupled in series with the first element, wherein the second element is configured such that a direction of current flow through the second element is orthogonal to a direction of current flow through the first element.

14. The IC of claim 8, wherein the semiconductor substrate is a p-type silicon substrate.

15. The IC of claim 8, further comprising:

a first current source coupled to the lateral resistor;

a second current source coupled to the vertical reference resistor; and

an amplifier coupled to the lateral resistor and the vertical reference resistor, the amplifier having an output for providing a voltage difference signal.

16. The IC of claim 15, wherein the voltage difference signal is indicative of an in-plane stress on the IC.

17. A method of determining stress on an Integrated Circuit (IC), comprising:

applying a current to a lateral resistor of a stress sensing circuit, thereby generating a first voltage across the lateral resistor;

applying the current to a vertical resistor of the stress sensing circuit, thereby generating a second voltage across the vertical resistor, wherein the vertical resistor comprises a first trench, a second trench, and a deep layer coupled between the first trench and the second trench, and wherein the first trench and the second trench are dual rotationally symmetric about a vertical direction; and is

Generating a voltage difference signal between the first voltage and the second voltage.

18. The method of claim 17, wherein the voltage difference signal is indicative of an in-plane stress on the IC.

19. The method of claim 17, wherein the first and second trenches and the lateral resistor are n-doped and have the same doping concentration.

20. The method of claim 17, wherein the first and second trenches have a first piezoresistive coefficient for current flow in the vertical direction and the deep layer has a second piezoresistive coefficient for current flow in a lateral direction orthogonal to the vertical direction.

21. The method of claim 17, further comprising providing the voltage difference signal to other circuitry on the IC, wherein the other circuitry calculates a calibration parameter based on the voltage difference signal.

Background

Mechanical stress and temperature may cause changes to the semiconductor die, for example, by changing the size or mobility of devices on the die. Such changes may result in modification of circuit parameters associated with the device, such as the frequency of the integrated oscillator and the resistivity of the resistor, which in turn changes the behavior of the Integrated Circuit (IC) that includes the device. Some circuit parameters (e.g., bandgap voltage and oscillator frequency) respond differently to stress in the x-direction than to stress in the y-direction. Determining the magnitude and direction of the stress component allows proper compensation for mechanical stress on the chip, chip temperature, and the resulting effect on the devices on the chip. Some stress sensing circuits include resistors in the x and y directions to determine the stress component in each direction. The resistance from the sense resistor is compared to the resistance from the reference resistor in the z-direction. However, in some examples, the temperature coefficient of the reference resistor is different from the temperature coefficient of the sense resistor, which may result in improper adjustment due to confusion between temperature and stress effects. Furthermore, in some examples, the resistance of the reference resistor is also affected by in-plane stress, thereby masking the correct magnitude of the stress component.

Disclosure of Invention

In some embodiments, an integrated circuit includes a semiconductor substrate having a surface and a vertical reference resistor. The vertical reference resistor comprises layers arranged in a plane parallel to the surface of the substrate. The layer is doped to facilitate current flow in the plane. The vertical reference resistor further includes a first trench and a second trench coupled between the layer and the surface of the substrate. The first trench and the second trench are arranged in a vertical direction orthogonal to the plane and the surface and are doped to impede current flow in the vertical direction. The cross-section of the first trench and the second trench is doubly rotationally symmetric (two-fold rotation symmetry) about the vertical direction.

In some examples, the integrated circuit further includes a lateral resistor disposed on a second plane parallel to the surface of the substrate. The second plane is shallower than a plane of the layer in which the vertical reference resistor is arranged. The lateral resistor and the first and second trenches have the same temperature coefficient. In some examples, the lateral resistor and the first and second trenches have the same doping.

In some examples, the first trench and the second trench are separated by an isolation structure. In some examples, the second groove is pinhole-shaped in cross-section. The integrated circuit may be used as a stress sensing circuit. In these examples, an integrated circuit includes a lateral resistor, a first current source coupled to the lateral resistor, a second current source coupled to a vertical reference resistor, and an amplifier coupled to the lateral resistor and the vertical reference resistor. The amplifier is configured to output a voltage difference signal between a voltage across the lateral resistor and a voltage across the vertical reference resistor. The voltage difference signal is indicative of a magnitude and a direction of an in-plane stress on the integrated circuit.

Drawings

Fig. 1 shows a graph showing how the oscillator responds differently to stress in two orthogonal directions.

FIG. 2 shows a graph illustrating the effect of temperature on an example reference resistor and an example sense resistor.

FIG. 3 illustrates an example stress sensing element.

FIG. 4 illustrates an example stress sensing circuit including the stress sensing element shown in FIG. 3. 3.

5A-5B illustrate example reference resistors for a stress sensing element.

Fig. 6 illustrates an example layout of trenches in the example reference resistor shown in fig. 5A-5B.

Detailed Description

Some stress sensing circuits include resistors arranged in a lateral plane parallel to a surface of a semiconductor die that includes the stress sensing circuit. The resistors in the transverse plane are arranged perpendicular to each other and are used to determine stress components in various directions within the transverse plane. The resistance from the sense resistor is compared to the resistance from the reference resistor in the vertical direction perpendicular to the transverse plane. However, some stress sensing circuits include a reference resistor with a different temperature coefficient than the sense resistor, which may result in improper tuning due to confusion between temperature and stress effects. Furthermore, in some examples, the reference resistor is also affected by in-plane stress, thereby masking the correct magnitude of the stress component.

The disclosed reference resistor for a stress sensing circuit has the same temperature dependence as the associated sense resistor, since both resistors have substantially the same doping. This ensures that the sense resistor and the reference resistor have the same temperature coefficient and respond to temperature changes in substantially the same way, thereby avoiding confusion of the actual stress on the sense resistor from different temperature responses. The disclosed reference resistor is also symmetrical in the x and y directions, ensuring that the resistance of the reference resistor is substantially independent of the direction of in-plane stress.

An example reference resistor includes a buried layer that is highly doped to facilitate current flow and exhibits low resistance. The buried layer is disposed in a lateral plane parallel to a surface of the semiconductor die including the example reference resistor. The example reference resistor further includes a deep vertical path arranged perpendicular to a lateral plane including the buried layer. The deep vertical path is sidewall doped to exhibit high resistance in the vertical direction perpendicular to the buried layer and a temperature coefficient substantially the same as the associated sense resistor. The depth and doping of the vertical path and the doping and thickness of the buried layer cause the example reference resistor to experience substantially all of the vertical current flow. The cross section of the deep vertical path is doubly rotationally symmetric, such as a pinhole or ring inside a larger ring. The symmetrical layout of the vertical current flow and the deep vertical path in the x and y directions reduces the stress direction dependence of the example reference resistor.

Fig. 1 shows a graph showing how the oscillator responds differently to stress in two orthogonal directions. The graph shown in fig. 1 is from the reference "Electrical Compensation of Mechanical stress in Precision Analog Circuit", m.motz, u.australlecher, Springer, 2016, and shows the percent output frequency drift of a resistance/capacitance (RC) relaxation oscillator when stress is applied to an Integrated Circuit (IC) on which the oscillator is implemented. The response of the oscillator to stress in one direction is different from the response to stress in the other direction, subject to different drift percentages of the output frequency depending on the direction of the stress applied thereto. In this example, stress σ xx along the x-axis causes the output frequency of the oscillator to shift more than stress σ yy along the y-axis. Further, stress along the x-axis results in an increase in output frequency, while stress along the y-axis results in a decrease in output frequency.

Temperature may also affect the components of the IC. Fig. 2 shows a graph demonstrating the effect of temperature on an example reference resistor 210 and an example sense resistor 220 with different doping. The different doping between the reference resistor 210 and the sense resistor 220 results in the two resistors having different temperature dependencies. If the reference resistor 210 and the sense resistor 220 are used in a stress sensing circuit, ambiguity (ambiguity) may be caused due to different temperature dependencies. At high or low temperatures, the reference resistor 210 and the sense resistor 220 may behave differently without applying any stress, but the stress sensing circuit will recognize the difference between the reference resistor 210 and the sense resistor 220 and treat it as stress applied to the IC. Erroneously identified stresses can contribute to unnecessary and inaccurate adjustment of other circuits on the IC.

FIG. 3 illustrates an example stress-sensing element 300. A semiconductor wafer 305, such as a silicon wafer, is sawed from a single crystal rod such that the wafer surface is associated with a crystallographic plane. The miller indices, denoted by braces { }, are used to determine the corresponding planes in the cubic crystal. FIG. 3 depicts a top view of a stress sensing element 300 on a p-type semiconductor substrate 305, the p-type semiconductor substrate 305 being cut on a 100 plane and provided with a notch along the 100 direction. Although not limiting, the examples described herein utilize p-type semiconductor wafers cut in the 100 planes. The wafer 305 shown in fig. 3 is an example; the stress sensing elements and reference resistors described herein are not limited to wafers having a [100] notch, {100} plane, or p-type doping. In other examples, an n-type semiconductor substrate is used. The n-type semiconductor wafer may be cut in any suitable plane such as 100.

The stress sensing element 300 includes a reference resistor 310 and a sense resistor 320. In this example, the reference resistor 310 and the sense resistor 320 are n-type resistors. In some examples, the reference resistor 310 and the sense resistor 320 are p-type resistors. In other examples, the reference resistor 310 and the sense resistor 320 utilize different doping types, such as mixed doping. The sense resistor 320 includes a first resistor element 320A aligned in the y-direction and a second resistor element 320B aligned in the x-direction. The alignment of resistor elements 320A and 320B results in a majority of the current flowing through resistor elements 320A and 320B being longitudinal or transverse (transverse) with respect to the [100] crystal axis. The current flows through resistor element 320A which is longitudinal with respect to the [100] crystal axis. The current flows in the [010] direction through the resistor element 320B that is transverse with respect to the [100] crystal axis direction. In other examples, resistor elements 320A and 320B are aligned such that current flowing through resistor elements 320A and 320B is longitudinal or transverse with respect to the [110] crystal axis. Other resistor orientations are possible. For example, resistor elements 320A and 320B may be rotated 45 degrees from alignment with the x and y axes. In another example, one of resistor elements 320A and 320B includes multiple rows of resistive elements such that the ratio of resistor elements 320A to resistor elements 320B is not one-to-one. The reference resistor 310 is a vertical resistor aligned in the z-direction.

FIG. 4 illustrates an example stress sensing circuit 400 that includes the stress sensing element 300 shown in FIG. 3. Stress sensing circuit 400 also includes two current sources and a differential circuit. A current source 415 is coupled to the supply voltage node 405 and the reference resistor 310. In this example, reference resistor 310 is further coupled to common mode node 410. Current source 415 applies a current to reference resistor 310, resulting in a voltage drop across reference resistor 310. Voltage Vref 420 is provided to differential circuit 440 from a point between current source 415 and reference resistor 310. A current source 425 is coupled to the supply voltage node 405 and the sense resistor 320. The sense resistor 320 is further coupled to a common mode node 410. Current source 425 applies a current to sense resistor 320 resulting in a voltage drop across sense resistor 320. The voltage Vsense 430 is provided to the difference circuit 440 from a point between the current source 425 and the sense resistor 320. In other examples, reference resistor 310 and sense resistor 320 are coupled to a supply voltage at node 410. In this example, the sense resistor 320 includes both a resistor element 320A and a resistor element 320B coupled together in series. In other examples, a separate stress sensing circuit 400 is included for each of resistor element 320A and resistor element 320B.

The differential circuit 440 outputs a voltage difference signal Vdiff 450. In some examples, the differential circuit 440 is an amplifier. Vdiff 450 represents the difference between Vsense 430 and Vref 420 and may be used to determine the value of the stress component in the transverse and longitudinal directions relative to the [100] crystal axis. In turn, the values of these stress components may be used to determine appropriate adjustments to the operation in other circuits on the IC. To determine the correct values of the stress components in the transverse and longitudinal directions, the reference resistor 310 is substantially independent of the direction of the in-plane stress. In addition, the reference resistor 310 and the sense resistor 320 have the same temperature coefficient.

For example, sense resistor 320 and reference resistor 310 have desired resistance values and corresponding desired values for Vsense and Vref, and thus a desired value for Vdiff. Because the reference resistor 310 and the sense resistor have the same temperature coefficient, any differences between the actual and expected values of Vsense and Vref due to the temperature of the semiconductor die that includes the stress sensing circuit 400 are cancelled out. Therefore, the difference between the actual and expected values of Vdiff is likely due to in-plane stress on the semiconductor die.

The reference resistor 310 is substantially independent of the direction of in-plane stress, so the difference between the actual and expected values of Vdiff is likely due to changes in Vsense caused by changes in the resistance of the sense resistor 320. The vertical arrangement of resistor element 320A and resistor element 320B allows the difference between the actual and expected Vdiff to be distributed according to the direction and magnitude of the in-plane stress component on the semiconductor die. The direction and magnitude of the in-plane stress component may be provided to other circuitry on the semiconductor die and used to determine appropriate calibration parameters for the on-die device.

Fig. 5A-5B illustrate an example reference resistor 500 for a stress sensing element (e.g., to implement reference resistor 310). The reference resistor 500 is an n-type vertical resistor. In other examples, the reference resistor 500 is a p-type resistor. Fig. 5A shows a cross-section of a reference resistor 500. The deep n-well 560 is implanted into a p-type substrate 570, which p-type substrate 570 may include an epitaxial layer (not specifically shown). In other examples, substrate 570 is an n-type substrate. The deep n-well 560 forms a buried layer and is highly doped to facilitate current flow and exhibit low resistance. The trenches 550 are sidewall-doped deep trenches that contact opposite ends of the deep n-well 560 and are highly doped for horizontal current flow and less doped for vertical current flow. This results in trench 550 having a first piezoresistive coefficient for current flow in the lateral direction and a second, higher piezoresistive coefficient for current flow in the vertical direction. Further, a larger portion of the resistive path is along the trench 550 in the vertical direction, while a smaller portion of the resistive path is in the lateral direction.

The n-well 535 is implanted into the surface of the substrate 570 to contact the trench 550 and then into the p-well 540. A dielectric layer 520 is then formed to cover the surface of the substrate 570. n-contact 530 is implanted into n-well 535 and p-contact 525 is implanted into p-well 540. Before vias 510 are formed to n-contact 530 and p-contact 525, interlayer dielectric 515 is deposited. A metallization layer 505 is then formed over the via 510.

Current 580 flows through trench 550A from n-well 535A to deep n-well 560. Current 580 flows through the length of deep n-well 560 to trench 550B, up trench 550B and through n-well 535B. The depth of the trench 550 and the lower doping concentration for current flow in the vertical direction cause the reference resistor 500 to exhibit a higher vertical resistance and a larger voltage difference across the trench 550. Conversely, the thickness and higher doping concentration of deep n-well 560 results in a lower resistance path for current flow in the lateral direction, resulting in reference resistor 500 exhibiting a lower lateral resistance and a smaller voltage difference across deep n-well 560.

Although depicted as "trenches" in fig. 5A, any suitable deep vertical path may be used. The disclosed reference resistor comprises two deep vertical paths with a lower doping concentration for current flow in the vertical direction, which results in the disclosed reference resistor exhibiting a higher vertical resistance and a larger voltage difference across the deep vertical paths. The two deep vertical paths are coupled together by a deep well having a higher doping concentration for current flow in the lateral direction, which results in the disclosed reference resistor exhibiting a lower lateral resistance and a smaller voltage difference across the deep well. The predominantly vertical current flow results in the disclosed reference resistor being substantially independent of the direction of in-plane stress.

Fig. 5B shows a top view 590 and an oblique view 595 of a cross-section of trench 550 of reference resistor 500. The cross-section of the trench 550 is symmetrical in the x and y directions, and is square in this example. In other examples, the interior trench 550B is a pinhole or other symmetrical shape. The trench 550 and the deep n-well 560 are doubly rotationally symmetric about the z-axis of the reference resistor 500, but are asymmetric when rotated in the z-direction. The x and y symmetric cross-sections of the trench 550 and the predominant vertical current flowing through the reference resistor 500 reduce the stress direction dependence such that the reference resistor 500 is substantially independent of the direction of in-plane stress on the IC. The reference resistor 500 is mainly resistive in the vertical direction. The doping in the trench 550 is the same as the doping within the associated sense resistor so that the reference resistor 500 and the associated sense resistor have the same temperature coefficient. It will be understood that the diagram of the resistor 500 is not necessarily drawn to scale.

Fig. 6 shows an alternative cross-section of the trench 550 of the reference resistor 500. The example layout 610 shows a square trench 550A and a smaller square trench 550B inside the square formed by the trench 550A. The example layout 620 shows a circular trench 550A and a smaller circular trench 550B inside the circle formed by the trench 550A. The example layout 630 shows a square trench 550A rotated 45 degrees from the x and y axes and a smaller square trench 550B rotated 45 degrees from the x and y axes inside the rotated square formed by the trench 550A. Example layout 640 shows a circular trench 550A and a circular pinhole-shaped trench 550B inside the circle formed by trench 550A. The example layout 650 shows a square trench 550A and a square pinhole shaped trench 550B inside the square formed by the trench 550A. In each of the example layouts 610, 620, 630, 640, and 650, the trenches 550 are symmetric and experience substantially the same amount of stress in the x-direction as in the y-direction. The example layout shown in fig. 6 is not a complete set of possible layouts for trenches 550. Other symmetrical arrangements may also be used.

The examples described herein utilize p-type semiconductor wafers cut in the 100 plane. However, the reference resistors described herein are not limited to wafers having [100] notches, {100} planes, or p-type doping. In other examples, an n-type semiconductor substrate is used. The n-type semiconductor wafer may be cut in any suitable plane such as 100.

In this specification, the terms "couple" or "coupling" refer to an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The reference to "based on" means "based at least in part on". Thus, if X is based on Y, X may be a function of Y and any number of other factors. Unless otherwise stated, in this specification, "the same" or "substantially" the same means that the two differ by less than ten percent, "substantially" or "substantially" unaffected means that the variation is less than ten percent, and "substantially" means ninety percent or greater.

Modifications may be made in the described embodiments within the scope of the claims, and other embodiments are possible.