阅读说明：本技术 存储器结构 (Memory structure ) 是由 车行远 李世平 于 2019-01-31 设计创作，主要内容包括：本发明公开一种存储器结构,其包括绝缘层覆硅基底、第一晶体管、第二晶体管、隔离结构以及电容器。绝缘层覆硅基底包括硅基体以及依序设置于硅基体上的介电层与硅层。第一晶体管与第二晶体管设置于硅层上。隔离结构设置于第一晶体管与第二晶体管之间的硅层中。电容器设置于第一晶体管与第二晶体管之间。电容器包括主体部分、第一延伸部分、第二延伸部分以及第三延伸部分。第一延伸部分自主体部分延伸至与第一晶体管的源极/漏极区。第二延伸部分自主体部分延伸至与第二晶体管的源极/漏极区。第三延伸部分自主体部分延伸穿过隔离结构至介电层中。(The invention discloses a memory structure, which comprises an insulating layer silicon-on-substrate, a first transistor, a second transistor, an isolation structure and a capacitor. The SOI substrate comprises a silicon substrate, and a dielectric layer and a silicon layer sequentially arranged on the silicon substrate. The first transistor and the second transistor are arranged on the silicon layer. The isolation structure is disposed in the silicon layer between the first transistor and the second transistor. The capacitor is arranged between the first transistor and the second transistor. The capacitor includes a body portion, a first extension portion, a second extension portion, and a third extension portion. The first extension portion extends from the body portion to a source/drain region of the first transistor. The second extension portion extends from the body portion to a source/drain region of the second transistor. The third extension portion extends from the body portion through the isolation structure into the dielectric layer.)

1. A memory structure, comprising:

the silicon-on-insulator substrate comprises a silicon substrate, a first dielectric layer and a silicon layer, wherein the first dielectric layer and the silicon layer are sequentially arranged on the silicon substrate;

a first transistor and a second transistor disposed on the silicon layer;

an isolation structure disposed in the silicon layer between the first transistor and the second transistor; and

a capacitor disposed between the first transistor and the second transistor, and including:

a body portion;

a first extension portion extending from the body portion to a source/drain region of the first transistor;

a second extension portion extending from the body portion to a source/drain region of the second transistor; and

a third extension portion extending from the body portion through the isolation structure into the first dielectric layer.

2. The memory structure of claim 1, wherein the first transistor is one of an nmos transistor and a pmos transistor, and the second transistor is the other of an nmos transistor and a pmos transistor.

3. The memory structure of claim 1, further comprising a second dielectric layer disposed on the silicon layer and covering the first transistor and the second transistor, wherein the body portion, the first extension portion, the second extension portion, and a portion of the third extension portion are in the second dielectric layer.

4. The memory structure of claim 1, wherein a width of the third extension portion is substantially uniform.

5. The memory structure of claim 1, wherein a thickness of the isolation structure is the same as a thickness of the silicon layer.

6. The memory structure of claim 1, wherein the capacitor is comprised of a lower electrode, an upper electrode, and an insulating layer between the lower electrode and the upper electrode, and the body portion, the first extension portion, the second extension portion, and the third extension portion each include the lower electrode, the upper electrode, and the insulating layer.

7. The memory structure of claim 6, wherein the lower electrode of the first extension is connected to a source/drain region of the first transistor.

8. The memory structure of claim 6, wherein the lower electrode of the second extension is connected to a source/drain region of the second transistor.

9. A memory structure, comprising:

the silicon-on-insulator substrate comprises a silicon substrate, a first dielectric layer and a silicon layer, wherein the first dielectric layer and the silicon layer are sequentially arranged on the silicon substrate;

a first transistor and a second transistor disposed on the silicon layer;

an isolation structure disposed in the silicon layer between the first transistor and the second transistor;

a capacitor disposed between the first transistor and the second transistor, and including:

a body portion;

a first extension portion extending from the body portion to a source/drain region of the first transistor;

a second extension portion extending from the body portion to a source/drain region of the second transistor; and

a third extension portion extending from the body portion through the isolation structure into the first dielectric layer and including a first portion and a second portion, wherein the second portion is located in the first dielectric layer and a projected area of the second portion on the silicon substrate is larger than a projected area of the first portion on the silicon substrate; and

liners disposed between the first and third extensions, between the second and third extensions, between the isolation structure and the third extension, and between the first dielectric layer and the third extension.

10. The memory structure of claim 9, wherein the first transistor is one of an nmos transistor and a pmos transistor, and the second transistor is the other of an nmos transistor and a pmos transistor.

11. The memory structure of claim 9, further comprising a second dielectric layer disposed on the silicon layer and covering the first transistor and the second transistor, wherein the body portion, the first extension portion, the second extension portion, and a portion of the third extension portion are in the second dielectric layer.

12. The memory structure of claim 9, wherein a portion of the first portion is located in the first dielectric layer.

13. The memory structure of claim 9, wherein the isolation structure has a thickness that is the same as a thickness of the silicon layer.

14. The memory structure of claim 9, wherein the capacitor is comprised of a lower electrode, an upper electrode, and an insulating layer between the lower electrode and the upper electrode, and the body portion, the first extension portion, the second extension portion, and the third extension portion each include the lower electrode, the upper electrode, and the insulating layer.

15. The memory structure of claim 14, wherein the lower electrode of the first extension is connected to a source/drain region of the first transistor.

16. The memory structure of claim 14, wherein the lower electrode of the second extension is connected to a source/drain region of the second transistor.

Technical Field

The present invention relates generally to semiconductor structures, and more particularly to memory structures.

Background

A memory structure including a transistor and a capacitor is currently developed. In such a memory structure, a capacitor is used as a storage element. Under the current trend of increasing device integration, it is a continuous effort in the industry to achieve the goal of effectively improving the electrical performance of a memory device without increasing the size of a memory cell.

Disclosure of Invention

The invention provides a memory structure, wherein a part of a capacitor is arranged in an isolation structure and a silicon layer of an insulation layer silicon-on-silicon substrate.

The memory structure of the invention comprises an insulating layer Silicon On Insulator (SOI) substrate, a first transistor, a second transistor, an isolation structure and a capacitor. The insulation layer silicon-on-insulator substrate comprises a silicon substrate, and a first dielectric layer and a silicon layer which are sequentially arranged on the silicon substrate. The first transistor and the second transistor are disposed on the silicon layer. The isolation structure is disposed in the silicon layer between the first transistor and the second transistor. The capacitor is disposed between the first transistor and the second transistor. The capacitor includes a body portion, a first extension portion, a second extension portion, and a third extension portion. The first extension portion extends from the body portion to a source/drain region of the first transistor. The second extension portion extends from the body portion to a source/drain region of the second transistor. The third extension portion extends from the body portion through the isolation structure into the first dielectric layer.

In an embodiment of the memory structure of the invention, a width of the third extending portion is substantially uniform.

The memory structure comprises an insulation layer silicon-on-insulator substrate, a first transistor, a second transistor, an isolation structure, a capacitor and a lining layer. The insulation layer silicon-on-insulator substrate comprises a silicon substrate, and a first dielectric layer and a silicon layer which are sequentially arranged on the silicon substrate. The first transistor and the second transistor are disposed on the silicon layer. The isolation structure is disposed in the silicon layer between the first transistor and the second transistor. The capacitor is disposed between the first transistor and the second transistor. The capacitor includes a body portion, a first extension portion, a second extension portion, and a third extension portion. The first extension portion extends from the body portion to a source/drain region of the first transistor. The second extension portion extends from the body portion to a source/drain region of the second transistor. The third extension portion extends from the main body portion through the isolation structure into the first dielectric layer and includes a first portion and a second portion, wherein the second portion is located in the first dielectric layer, and a projected area of the second portion on the silicon substrate is larger than a projected area of the first portion on the silicon substrate. The liner layer is disposed between the first and third extension portions, between the second and third extension portions, between the isolation structure and the third extension portion, and between the first dielectric layer and the third extension portion.

In an embodiment of the memory structure of the invention, a part of the first portion is located in the first dielectric layer, for example.

In an embodiment of the memory structure of the invention, the first transistor is, for example, one of an nmos transistor and a pmos transistor, and the second transistor is, for example, the other of an nmos transistor and a pmos transistor.

In an embodiment of the memory structure of the invention, the memory structure further includes a second dielectric layer disposed on the silicon layer and covering the first transistor and the second transistor, wherein a portion of the body portion, the first extension portion, the second extension portion, and the third extension portion is located in the second dielectric layer.

In an embodiment of the memory structure of the present invention, a thickness of the isolation structure is the same as a thickness of the silicon layer.

In an embodiment of the memory structure of the present invention, the capacitor is formed by a lower electrode, an upper electrode, and an insulating layer between the lower electrode and the upper electrode, and the body portion, the first extension portion, the second extension portion, and the third extension portion each include the lower electrode, the upper electrode, and the insulating layer.

In an embodiment of the memory structure of the present invention, the lower electrode of the first extension portion is connected to a source/drain region of the first transistor, for example.

In an embodiment of the memory structure of the invention, the lower electrode of the second extension portion is connected to a source/drain region of the second transistor, for example.

Based on the above, in the memory structure of the invention, the capacitor extends downward through the isolation structure to the dielectric layer of the soi substrate, so that the coupling ratio (coupling ratio) between the lower electrode and the upper electrode can be increased without increasing the layout area and the thickness of the memory structure, thereby improving the performance of the memory structure.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIGS. 1A to 1F are schematic cross-sectional views illustrating a manufacturing process of a memory structure according to a first embodiment of the invention;

fig. 2A to fig. 2E are schematic cross-sectional views illustrating a manufacturing process of a memory structure according to a second embodiment of the invention.

Description of the symbols

10. 20: memory structure

100: silicon-on-insulator substrate

100 a: silicon substrate

100b, 108, 122, 218: dielectric layer

100 c: silicon layer

102: isolation structure

104. 106: transistor with a metal gate electrode

104a, 106 a: gate dielectric layer

104b, 106 b: grid electrode

104c, 106 c: doped region

110a, 110b, 112, 118, 204, 208, 214: groove

114. 210: sacrificial layer

116. 202, 212: patterned mask layer

120. 124, 216, 220: conductive layer

120a, 216 a: lower electrode

122a, 218 a: insulating layer

124a, 220 a: upper electrode

126. 222: capacitor with a capacitor element

126a, 222 a: body part

126b, 126c, 126d, 222b, 222c, 222 d: extension part

200: etch stop layer

206: liner layer

208 a: lower part

208 b: upper part

Detailed Description

The following examples are set forth in detail in conjunction with the accompanying drawings, but are not provided to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, like elements in the following description will be described with like reference numerals.

Furthermore, as used herein, the terms "comprising," including, "" having, "and the like are open-ended terms, i.e.," including, but not limited to.

In addition, directional terms such as "above" and "below" are used with reference to the drawings, and are not intended to limit the present invention.

Fig. 1A to fig. 1F are schematic cross-sectional views illustrating a manufacturing process of a memory structure according to a first embodiment of the invention.

First, referring to fig. 1A, an insulation layer-on-silicon substrate 100 is provided. The soi substrate 100 comprises a silicon substrate 100a, and a dielectric layer 100b and a silicon layer 100c sequentially disposed on the silicon substrate 100 a. Generally, the silicon substrate 100a may be doped with P-type dopants, for example, and preferably has a thickness of aboutPreferably, the dielectric layer 100b has a thickness greater than about 2 μm, and the silicon layer 100c may be doped, for exampleHaving a P-type dopant and preferably having a thickness greater than about 0.5 μm. The dielectric layer 100b is, for example, a silicon oxide layer. Next, an isolation structure 102 is formed in the silicon layer 100c to define an Active Area (AA). The isolation structure is, for example, a Shallow Trench Isolation (STI) structure. In the present embodiment, the thickness of the isolation structure 102 is the same as the thickness of the silicon layer 100c, that is, the isolation structure 102 penetrates through the silicon layer 100c, so that adjacent active regions can be effectively isolated from each other. The method for forming the isolation structure 102 is well known to those skilled in the art and will not be described herein.

Next, referring to fig. 1B, a transistor 104 and a transistor 106 are formed on the silicon layer 100 c. Transistor 104 and transistor 106 are separated from each other by isolation structure 102. Transistor 104 has a different conductivity type than transistor 106. For example, the transistor 104 is an NMOS transistor, and the transistor 106 is a PMOS transistor. Conversely, if the transistor 104 is a PMOS transistor, the transistor 106 is an NMOS transistor. In the present embodiment, the transistor 104 includes a gate dielectric layer 104a and a gate 104b sequentially disposed on the silicon layer 100c, and a doped region 104c as a source/drain disposed in the silicon layer 100c, and the transistor 106 includes a gate dielectric layer 106a and a gate 106b sequentially disposed on the silicon layer 100c, and a doped region 106c as a source/drain disposed in the silicon layer 100 c. The formation methods of the transistor 104 and the transistor 106 are well known to those skilled in the art and will not be described herein. Thereafter, a dielectric layer 108 is formed on the silicon layer 100 c. A dielectric layer 108 covers the transistors 104 and 106. The dielectric layer 108 is, for example, a silicon oxide layer. The dielectric layer 108 is generally referred to as an inter-layer dielectric (ild) layer.

Then, referring to fig. 1C, a trench 110a and a trench 110b are formed in the dielectric layer 108, and a trench 112 is formed in the dielectric layer 108, the isolation structure 102 and the dielectric layer 100b, wherein the trench 110a exposes a portion of the source/drain region 104C of the transistor 104, the trench 110b exposes a portion of the source/drain region 106C of the transistor 106, the bottom of the trench 112 is disposed in the dielectric layer 100b without exposing the silicon substrate 100a, the trench 110b and the trench 112 are formed, for example, by performing a first photolithography process and an etching process to form the trench 110a and the trench 110b, and then performing a second photolithography process and an etching process to form the trench 112, or by forming the trench 112 first, then forming the trench 110a and the trench 110b, or, depending on the fabrication process conditions, simultaneously forming the trench 110a, the trench 110b and the trench 112 in a patterning process, and then forming a sacrificial layer 114 on the dielectric layer 108, the trench 110a, 110b and the trench 112 may be formed at the same etch rate as in a subsequent planarization layer 35nraf (for example, the same as in the common etching process).

Next, referring to fig. 1D, a planarization process is performed to remove a portion of the sacrificial layer 114 until the dielectric layer 108 is exposed. The planarization process is, for example, a Chemical Mechanical Polishing (CMP) process. A patterned masking layer 116 is then formed on the dielectric layer 108. The patterned mask layer 116 exposes the region between the gates 104b and 106 b. Then, an anisotropic etching process is performed to remove a portion of the dielectric layer 108 and a portion of the sacrificial layer 114 by using the patterned mask layer 116 as an etching mask, so as to form a trench 118. In another embodiment, the planarization process can be omitted and the patterned mask layer 116 can be directly formed on the sacrificial layer 114.

Then, referring to fig. 1E, the patterned mask layer 116 and the sacrificial layer 114 are removed. Next, a conductive layer 120 for forming a lower electrode of the capacitor is conformally formed on the soi substrate 100. The conductive layer 120 is, for example, a titanium nitride layer. Next, a dielectric layer 122 for forming an insulating layer of a capacitor is conformally formed on the conductive layer 120. The dielectric layer 122 is, for example, a high dielectric constant (high-K) layer. Thereafter, a conductive layer 124 for forming an upper electrode of the capacitor is formed on the dielectric layer 122. The conductive layer 124 fills the trenches 110a, 110b and 112. The conductive layer 124 is a composite layer composed of a tungsten layer and a titanium nitride layer, for example.

Then, referring to fig. 1F, a planarization process is performed to remove a portion of the conductive layer 120, a portion of the dielectric layer 122, and a portion of the conductive layer 124 until the dielectric layer 108 is exposed. The planarization process is, for example, a chemical mechanical polishing process. After the planarization process, a capacitor 126 is formed, which includes the bottom electrode 120a, the insulating layer 122a and the top electrode 124a, i.e., the capacitor 126 is a well-known metal-insulator-metal (MIM) capacitor. In this way, the memory structure 10 of the present embodiment is completed. In addition, a contact connected to the transistor 104, a contact connected to the transistor 106, a contact connected to the upper electrode 124a of the capacitor 126, and the like may be formed later, which are well known in the art and will not be described herein.

In the present embodiment, the memory structure 10 includes an soi substrate 100, an isolation structure 102, a transistor 104, a transistor 106, and a capacitor 126. The capacitor 126 is disposed between the transistors 104 and 106. The capacitor 126 is composed of a lower electrode 120a, an insulating layer 122a and an upper electrode 124a, wherein the insulating layer 122a is located between the lower electrode 120a and the upper electrode 124 a. In addition, the capacitor 126 includes a body portion 126a, an extension portion 126b, an extension portion 126c, and an extension portion 126d, and the body portion 126a, the extension portion 126b, the extension portion 126c, and the extension portion 126d each include a lower electrode 120a, an insulating layer 122a, and an upper electrode 124 a. As shown in fig. 1F, the body portion 126a is substantially horizontally located between the gate 104b and the gate 106b, the extension portion 126b extends from the body portion 126a to connect with the source/drain region (doped region 104c) of the transistor 104 and the source/drain region of the transistor 104 via the bottom electrode 120a, the extension portion 126c extends from the body portion 126a to connect with the source/drain region (doped region 106c) of the transistor 106 and the source/drain region of the transistor 106 via the bottom electrode 120a, and the extension portion 126d extends from the body portion 126a through the isolation structure 102 into the dielectric layer 100 b. Thus, the capacitor 126 is electrically connected to the transistor 104 and the transistor 106 at the same time. In addition, in the present embodiment, the extension portion 126d has a substantially uniform width.

In the memory structure 10, the extension portion 126d of the capacitor 126 extends downward through the isolation structure 102 and into the dielectric layer 100b, so that the coupling ratio between the lower electrode 120a and the upper electrode 124a can be increased without increasing the layout area and the thickness of the memory structure, thereby improving the performance of the memory structure.

Fig. 2A to fig. 2E are schematic cross-sectional views illustrating a manufacturing process of a memory structure according to a second embodiment of the invention. In the present embodiment, the same elements as those of the first embodiment will be denoted by the same reference numerals, and a description thereof will not be given.

First, referring to fig. 2A, after the structure shown in fig. 1B is formed, an upper etch stop layer 200 is formed on the dielectric layer 108. The etch stop layer 200 is, for example, a silicon nitride layer. Next, a patterned mask layer 202 is formed on the etch stop layer 200. The patterned mask layer 202 exposes a portion of the area above the isolation structure 102. Then, an anisotropic etching process is performed using the patterned mask layer 202 as an etching mask to remove a portion of the etch stop layer 200, a portion of the isolation structure 102 and a portion of the dielectric layer 100b, so as to form a trench 204. In the present embodiment, the bottom of the trench 204 is located in the dielectric layer 100b, but the invention is not limited thereto. In other embodiments, the anisotropic etching process may remove only a portion of the etch stop layer 200 and a portion of the isolation structure 102 without removing the dielectric layer 100b, such that the bottom surface of the formed trench is coplanar with the top surface of the dielectric layer.

Next, referring to fig. 2B, the patterned mask layer 202 is removed. A liner 206 is then formed on the sidewalls of the trench 204. Liner 206 is, for example, a silicon nitride layer. The liner 206 is formed, for example, by conformally forming a liner material layer on the soi substrate 100 and then performing an anisotropic etching process to remove the liner material layer on the bottom surface of the trench 204 and the top surface of the etch stop layer 200. Then, an isotropic etching process is performed to remove a portion of the dielectric layer 100b to form a trench 208.

In detail, in the isotropic etching process, since the liner layer 206 is formed on the sidewall of the trench 204 and the etch stop layer 200 is formed on the top surface of the dielectric layer 108, only the exposed dielectric layer 100b is removed. In addition, due to the characteristics of the isotropic etching process, a space having curved sidewalls and an expanded width compared to the trench 104 is formed after removing a portion of the dielectric layer 108. That is, the trench 208 is formed to have a lower portion 208a in the dielectric layer 100b having an expanded width compared to the trench 104 and a remaining upper portion 208 b. Thereafter, a sacrificial layer 210 is formed in the trench 208. The sacrificial layer 210 is, for example, a generally common organic planarization layer.

Then, referring to fig. 2C, a patterned mask layer 212 is formed on the etch stop layer 200. Patterned masking layer 212 exposes the region between gates 104b and 106 b. Then, an anisotropic etching process is performed using the patterned mask layer 212 as an etching mask to remove a portion of the etch stop layer 200, a portion of the dielectric layer 108 and a portion of the liner layer 206, so as to form a trench 214. In addition, in the above anisotropic etching process, part of the sacrificial layer 210 in the upper portion 208b of the trench 208 is also removed. Since a portion of the sacrificial layer 210 is still retained in the trench 208, the shape and size of the lower portion 208a of the trench 208 are not changed by the etching process.

Next, referring to fig. 2D, the patterned mask layer 212 is removed. Then, a conductive layer 216 for forming a lower electrode of the capacitor is conformally formed on the soi substrate 100. The conductive layer 216 is, for example, a titanium nitride layer. Next, a dielectric layer 218 for forming an insulating layer of the capacitor is conformally formed on the conductive layer 216. The dielectric layer 218 is, for example, a high-k dielectric layer. Thereafter, a conductive layer 220 for forming an upper electrode of the capacitor is formed on the dielectric layer 218. Conductive layer 220 fills trench 208 and trench 214. The conductive layer 220 is a composite layer composed of a tungsten layer and a titanium nitride layer, for example.

Thereafter, referring to fig. 2E, a planarization process is performed to remove a portion of the sacrificial layer 210, a portion of the conductive layer 216, a portion of the dielectric layer 218, and a portion of the conductive layer 220 until the dielectric layer 108 is exposed. The planarization process is, for example, a chemical mechanical polishing process. After the planarization process, a capacitor 222 is formed, which includes a bottom electrode 216a, an insulating layer 218a and a top electrode 220a, i.e., the capacitor 222 is a well-known metal-insulator-metal capacitor. In this way, the memory structure 20 of the present embodiment is completed. In addition, a contact connected to the transistor 104, a contact connected to the transistor 106, a contact connected to the upper electrode 124a of the capacitor 222, and the like may be formed later, which are well known in the art and will not be described herein.

In the present embodiment, the memory structure 20 includes an insulation layer on the silicon substrate 100, an isolation structure 102, a transistor 104, a transistor 106, a capacitor 222, and a liner layer 206. The capacitor 222 is disposed between the transistors 104 and 106. The capacitor 222 is composed of a lower electrode 216a, an insulating layer 218a and an upper electrode 220a, wherein the insulating layer 218a is located between the lower electrode 216a and the upper electrode 220 a. In addition, the capacitor 222 includes a body portion 222a, an extension portion 222b, an extension portion 222c, and an extension portion 222d, and the body portion 222a, the extension portion 222b, the extension portion 222c, and the extension portion 222d each include a lower electrode 216a, an insulating layer 218a, and an upper electrode 220 a. As shown in fig. 2E, the body portion 222a is substantially horizontally located between the gate 104b and the gate 106b, the extension portion 222b extends from the body portion 222a to connect with the source/drain region (doped region 104c) of the transistor 104 and the source/drain region of the transistor 104 via the bottom electrode 216a, the extension portion 222c extends from the body portion 222a to connect with the source/drain region (doped region 106c) of the transistor 106 and the source/drain region of the transistor 106 via the bottom electrode 216a, and the extension portion 222d extends from the body portion 222a through the isolation structure 102 into the dielectric layer 100 b. Thus, the capacitor 222 can be electrically connected to the transistor 104 and the transistor 106 at the same time. Further, in the present embodiment, among the extension portions 222d, the projected area of the portion located in the lower portion 208a of the trench 208 on the silicon substrate 100a is larger than the projected area of the portion located in the upper portion 208b of the trench 208 on the silicon substrate 100 a. The liner layer 206 is disposed between the extension portion 222b and the extension portion 222d, between the extension portion 222c and the extension portion 222d, between the isolation structure 102 and the extension portion 222d, and between the dielectric layer 100b and the extension portion 222 d.

In the memory structure 20, the extension portion 222d of the capacitor 222 extends downward through the isolation structure 102 and into the dielectric layer 100b, so that the coupling ratio between the lower electrode 216a and the upper electrode 220a can be increased without increasing the layout area and the thickness of the memory structure, thereby improving the performance of the memory structure.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.