阅读说明：本技术 一种多通道同步高速数据采集装置 (Multichannel synchronous high-speed data acquisition device ) 是由 黄武煌 袁春友 张松 邱渡裕 张沁川 杨扩军 潘卉青 叶芃 王厚军 于 2021-06-29 设计创作，主要内容包括：本发明公开了一种多通道同步高速数据采集装置,通过时钟管理模块提供同步时钟,ADC在采样时钟的驱动下对信号进行采样,得到采样数据后传输到采集FPGA,多ADC数据同步模块在ADC中为采样数据添加时间戳标记,在采集FPGA中对采样数据进行调序,将带有标记位的采样点调整为第一路,并通过增加动态时延实现多ADC数据流同步；时钟同步时间戳添加和链路建立顺序管理模块对时钟同步、时间戳功能和JESD204B链路三个独立过程的工作顺序进行管理,解决三者在多ADC数据同步中的冲突,多通道采样同步模块通过调节时间戳信号与发送端器件时钟的相位关系,避免两者时序为例而产生随机延迟,基于触发的数据存储同步模块对信号进行精确延迟调节,实现了不同板间的数据同步存储。(The invention discloses a multichannel synchronous high-speed data acquisition device, which provides a synchronous clock through a clock management module, an ADC samples signals under the drive of the sampling clock to obtain sampling data and then transmits the sampling data to an acquisition FPGA, a multi-ADC data synchronization module adds a timestamp mark to the sampling data in the ADC, the sampling data is sequenced in the acquisition FPGA, a sampling point with a mark bit is adjusted to be a first path, and multi-ADC data stream synchronization is realized by increasing dynamic time delay; the clock synchronization timestamp adding and link establishing sequence management module manages the working sequence of three independent processes of clock synchronization, a timestamp function and a JESD204B link, conflicts of the three processes in multi-ADC data synchronization are solved, the multichannel sampling synchronization module avoids random delay caused by the fact that the time sequences of a timestamp signal and a clock of a sending end device are taken as an example by adjusting the phase relation of the timestamp signal and the clock of the sending end device, the triggered data storage synchronization module carries out accurate delay adjustment on the signal, and data synchronous storage among different boards is achieved.)

1. A multichannel synchronous high-speed data acquisition device is characterized by comprising a processing board and two acquisition sub-boards, wherein the two acquisition sub-boards have the same structure, acquire data in a parallel mode and send the data to the processing board;

the collecting sub-board and the processing board comprise the following modules:

the clock management module comprises a crystal oscillator and a plurality of clock chips, wherein the clock chips adopt a clock tree cascade structure and provide synchronous clock signals of enough channels for the whole system;

a clock chip on the processing board provides a clock source for a clock chip on the acquisition board through a clock output channel, and then provides a synchronous pulse signal for the clock of the acquisition board through a pulse output channel, the clock chip of the acquisition board responds to the signal after receiving the synchronous signal to adjust the phase of the clock output channel and provides the pulse signal for the FPGA and the ADC of the acquisition board through the output channel configured in a pulse mode, thereby realizing the synchronous clock output of the multi-clock chip;

the multi-ADC data synchronization module comprises a timestamp adding module, a sampling data sequence adjusting module and a dynamic time delay adding module;

the time stamp adding module opens the time stamp function of the ADC chip according to the ADC data manual; the ADC samples an input analog signal under the drive of the SCLK, and converts the analog signal into sampling point data of M bits; then, adding W bit redundant control bits for sampling point data of M bits by a serial channel mapping unit in the ADC to form M + W bit serial channel data, wherein the value of the redundant control bits is 0 under the default condition, when a rising edge of a timestamp marking signal SYSREF sent by a clock management module arrives, marking a first sampling point behind the rising edge, specifically, setting one of the redundant control bits to be 1, and finishing the addition of a timestamp;

the sampling data sequence-adjusting module adjusts the sequence of K paths of parallel data which are transmitted to the FPGA by the ADC and are subjected to speed reduction: detecting the position of a timestamp mark appearing in parallel data, and marking the position as L, wherein L is more than or equal to 1 and less than or equal to K; delaying the 1 st path to the L-1 st path of the original parallel data by two DCLK periods, and delaying the L path to the Kth path of the original parallel data by one DCLK period to form delayed parallel data; finally, rearranging the delayed parallel data in sequence from the L-th path to the K-th path and from the 1 st path to the L-1 st path to form the parallel data after sequence adjustment;

the dynamic delay increasing module uses a plurality of FIFOs to respectively increase dynamic delay for the parallel data after each channel is subjected to sequence adjustment, and when the parallel data after a certain channel is subjected to sequence adjustment is detected to contain a timestamp flag bit '1', the write enable of the FIFO of the corresponding channel is started; and when the parallel data after all the channels are sequenced are detected to contain the timestamp flag bit 1, starting the read enable of the FIFO of all the channels, keeping the write enable on, keeping the read and write balance, and dynamically increasing the delay of the parallel data of each channel to form the final user data stream.

The system comprises a clock synchronization, timestamp addition and link establishment sequence management module, a FPGA on a system processing board sends synchronization pulses to the time management module in three times, and the specific processing flow is as follows:

after the synchronous pulse sent by the FPFA for the first time is sent to the clock manager, the clock distribution network in the clock manager carries out reset operation to complete the clock synchronization process; then, the FPGA sends an SPI command to the clock manager, on one hand, the response of the clock distribution network to the synchronous pulse is shielded, and on the other hand, the response of the pulse distribution network to the synchronous pulse is opened; meanwhile, the FPGA also sends an SPI command to the ADC, the default register data of the ADC is rewritten, the default multi-frame clock alignment function in the ADC is forbidden, and the timestamp function is turned on;

after the synchronous pulse sent by the FPFA for the second time is sent to the clock manager, the pulse distribution network in the clock manager carries out reset operation to generate a reference pulse SYSREF of the system, and the reference pulse SYSREF is respectively fed back to the FPGA and all the ADCs; after receiving the reference pulse SYSREF, the gigabit transceiver module in the FPGA raises the SYNCB signals sent to each ADC by the FPGA, and after receiving the raised SYNCB signals, the ADC starts to transmit serial channel data streams to the FPGA to complete the data transmission link establishment process;

after the synchronous pulse sent by the FPFA for the second time is sent to the clock manager, the pulse distribution network in the clock manager carries out reset operation again, generates the reference pulse SYSREF of the system for the second time and feeds back the reference pulse SYSREF to the FPGA and all the ADCs respectively; after the ADC receives the reference pulse SYSREF, marking the first sampling point data after the rising edge moment of the reference pulse SYSREF, and keeping a certain position 1 and the rest positions 0 in the redundant control position of the serial channel data corresponding to the first sampling point data to finish the timestamp marking process;

a multi-channel sampling synchronization module, which comprises ADC time sequence adjustment, inter-channel delay measurement and inter-channel delay correction;

the ADC time sequence adjustment reads back data of an internal register of the ADC through an SPI communication protocol, monitors a SYSREF establishment/maintenance time window register of the ADC, if the read-back value of the register is 1, the time sequence violation is represented, namely the effective edge of the SYSREF appears in the window of the effective edge of the SCLK, the SYSREF does not meet the time sequence condition of the SCLK, and at the moment, the corresponding SYSREF delay value sent to the ADC is gradually increased until the time sequence violation is not displayed after the reinitialization, namely the read-back value is 0;

the inter-channel delay measurement is implemented by selecting one channel as a reference channel and the other channels as channels to be measured, outputting a sine signal with a known frequency by using a signal source, inputting the sine signal into the reference channel and the channels to be measured by using a power divider and an isometric transmission line, collecting user data collected by the reference channel and the channels to be measured in the same time period by using an FPGA debugging tool ILA, calculating phase difference among the channels and further obtaining inter-channel delay;

the interchannel delay correction is realized by gradually increasing the SCLK delay and the SYSREF delay of the channel to be detected according to the steps, so that the increased delay amount is as close to an interchannel delay value as possible until the absolute value of the difference between the increased delay amount and the measured interchannel delay value is smaller than the adjustable minimum step of the clock chip delay;

the data storage synchronization module based on triggering selects waveform data in a period of time to be sent to the FPGA of the processing board for processing and displaying on the upper computer after the data of the acquisition boards are synchronized, the process is called triggering, the selected data are temporarily stored into the Block FIFO which is triggered in the acquisition board at another stage from the Align FIFO which realizes synchronization, the read-write enabling signals of the Block FIFO are sent to the two acquisition boards by the FPGA of the processing board, and the control signals transmitted across the boards are accurately delayed and adjusted by the FPGA Idelay2 unit, so that the control signals of a receiving end are far away from a metastable state interval, and the storage synchronization of the waveform data of multiple modules is ensured.

Technical Field

The invention belongs to the technical field of oscilloscopes, and particularly relates to a multi-channel synchronous high-speed data acquisition device.

Background

With the continuous improvement of scientific research level, the demand of people on the multi-channel oscilloscope is continuously increased. In an increasing number of application scenarios, users are eager to acquire enough multi-channel data at the same time. In the safety detection of the helicopter hub, multi-channel acoustic emission signals need to be collected to position the cracks of the central part of the helicopter hub; in the seismic data acquisition system, observation signals not only comprise weak signals of thousands of kilometers away, such as weak earthquakes, nuclear earthquake signals, earth pulsation, earth background noise and the like, but also comprise more than 8-grade major earthquakes monitored by a near field, and the multi-channel hierarchical acquisition technology can effectively expand the dynamic range of the seismic data acquisition unit; in a wind tunnel test, the data acquisition system is provided with 32 input channels, each channel works independently, and one channel cannot be influenced by faults of other channels, so that the whole test system has high reliability and maintainability; in the gap test of the fighting parts, the data acquisition of a plurality of fighting parts can also improve the information quantity acquired in unit cost.

For a multi-channel high-speed data acquisition system using a GSPS ADC (analog-to-digital converter) with a JESD204B interface in pursuit of a higher sampling rate, data synchronization of multiple ADCs is a critical difficulty to be solved. ADCs on a single board can use deterministic delays to achieve data alignment, but for large systems such as those mentioned above, which often contain two or even more boards, there has been no clear solution on how to synchronize multiple ADC data on multiple boards.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a multichannel synchronous high-speed data acquisition device which comprises a processing board and a plurality of acquisition sub-boards, wherein each acquisition sub-board samples multichannel data, then a plurality of ADC data on a plurality of circuit boards are synchronized, and the delay among channels of the whole device is not more than 25 ps.

In order to achieve the purpose, the multichannel synchronous high-speed data acquisition device is characterized by comprising a processing board and a plurality of acquisition sub-boards, wherein each acquisition sub-board has the same structure, acquires data in a parallel mode and sends the data to the processing board;

the collecting sub-board and the processing board comprise the following modules:

the clock management module comprises a crystal oscillator and a plurality of clock chips, wherein the clock chips adopt a clock tree cascade structure and provide synchronous clock signals of enough channels for the whole system;

a clock chip on the processing board provides a clock source for a clock chip on the acquisition board through a clock output channel, and then provides a synchronous pulse signal for the clock of the acquisition board through a pulse output channel, the clock chip of the acquisition board responds to the signal after receiving the synchronous signal to adjust the phase of the clock output channel and provides the pulse signal for the FPGA and the ADC of the acquisition board through the output channel configured in a pulse mode, thereby realizing the synchronous clock output of the multi-clock chip;

the multi-ADC data synchronization module comprises a timestamp adding module, a sampling data sequence adjusting module and a dynamic time delay adding module;

the time stamp adding module opens the time stamp function of the ADC chip according to the ADC data manual; the ADC samples an input analog signal under the drive of the SCLK, and converts the analog signal into sampling point data of M bits; then, adding W bit redundant control bits for sampling point data of M bits by a serial channel mapping unit in the ADC to form M + W bit serial channel data, wherein the value of the redundant control bits is 0 under the default condition, when a rising edge of a timestamp marking signal SYSREF sent by a clock management module arrives, marking a first sampling point behind the rising edge, specifically, setting one of the redundant control bits to be 1, and finishing the addition of a timestamp;

the sampling data sequence-adjusting module adjusts the sequence of K paths of parallel data which are transmitted to the FPGA by the ADC and are subjected to speed reduction: detecting the position of a timestamp mark appearing in parallel data, and marking the position as L, wherein L is more than or equal to 1 and less than or equal to K; delaying the 1 st to L-1 st paths of the original parallel data by two DCLK periods, and delaying the first to the second paths of the original parallel data by one DCLK period to form delayed parallel data; finally, rearranging the delayed parallel data in sequence from the L-th path to the K-th path and from the 1 st path to the L-1 st path to form the parallel data after sequence adjustment;

the dynamic delay increasing module uses a plurality of FIFOs to respectively increase dynamic delay for the parallel data after each channel is subjected to sequence adjustment, and when the parallel data after a certain channel is subjected to sequence adjustment is detected to contain a timestamp flag bit '1', the write enable of the FIFO of the corresponding channel is started; when the parallel data after all the channels are sequenced are detected to contain a timestamp flag bit '1', starting the read enable of the FIFO of all the channels, keeping the write enable on, keeping the read and write balanced, and dynamically increasing the delay of the parallel data of each channel to form a final user data stream;

the system comprises a clock synchronization, timestamp addition and link establishment sequence management module, a FPGA on a system processing board sends synchronization pulses to the time management module in three times, and the specific processing flow is as follows:

after the synchronous pulse sent by the FPFA for the first time is sent to the clock manager, the clock distribution network in the clock manager carries out reset operation to complete the clock synchronization process; then, the FPGA sends an SPI command to the clock manager, on one hand, the response of the clock distribution network to the synchronous pulse is shielded, and on the other hand, the response of the pulse distribution network to the synchronous pulse is opened; meanwhile, the FPGA also sends an SPI command to the ADC, the default register data of the ADC is rewritten, the default multi-frame clock alignment function in the ADC is forbidden, and the timestamp function is turned on;

after the synchronous pulse sent by the FPFA for the second time is sent to the clock manager, the pulse distribution network in the clock manager carries out reset operation to generate a reference pulse SYSREF of the system, and the reference pulse SYSREF is respectively fed back to the FPGA and all the ADCs; after receiving the reference pulse SYSREF, the gigabit transceiver module in the FPGA raises the SYNCB signals sent to each ADC by the FPGA, and after receiving the raised SYNCB signals, the ADC starts to transmit serial channel data streams to the FPGA to complete the data transmission link establishment process;

after the synchronous pulse sent by the FPFA for the third time is sent to the clock manager, the pulse distribution network in the clock manager carries out reset operation again, generates the reference pulse SYSREF of the system for the second time and feeds back the reference pulse SYSREF to the FPGA and all the ADCs respectively; after the ADC receives the reference pulse SYSREF, marking the first sampling point data after the rising edge moment of the reference pulse SYSREF, and keeping a certain position 1 and the rest positions 0 in the redundant control position of the serial channel data corresponding to the first sampling point data to finish the timestamp marking process;

a multi-channel sampling synchronization module, which comprises ADC time sequence adjustment, inter-channel delay measurement and inter-channel delay correction;

the ADC time sequence adjustment reads back data of an internal register of the ADC through an SPI communication protocol, monitors a SYSREF establishment/maintenance time window register of the ADC, if the read-back value of the register is 1, the time sequence violation is represented, namely the effective edge of the SYSREF appears in the window of the effective edge of the SCLK, the SYSREF does not meet the time sequence condition of the SCLK, and at the moment, the corresponding SYSREF delay value sent to the ADC is gradually increased until the time sequence violation is not displayed after the reinitialization, namely the read-back value is 0;

the inter-channel delay measurement is implemented by selecting one channel as a reference channel and the other channels as channels to be measured, outputting a sine signal with a known frequency by using a signal source, inputting the sine signal into the reference channel and the channels to be measured by using a power divider and an isometric transmission line, collecting user data collected by the reference channel and the channels to be measured in the same time period by using an FPGA debugging tool ILA, calculating phase difference among the channels and further obtaining inter-channel delay;

the interchannel delay correction is realized by gradually increasing the SCLK delay and the SYSREF delay of the channel to be detected according to the steps, so that the increased delay amount is as close to an interchannel delay value as possible until the absolute value of the difference between the increased delay amount and the measured interchannel delay value is smaller than the adjustable minimum step of the clock chip delay;

the data storage synchronization module based on triggering selects waveform data within a period of time and sends the waveform data to a processing board FPGA for processing and displaying on an upper computer after data synchronization of the acquisition boards, the process is called triggering, the selected data is temporarily stored into a Block FIFO for triggering at another stage in the acquisition boards from an Align FIFO for realizing synchronization, read-write enabling signals of the Block FIFO are sent to the two acquisition boards FPGA by the processing board FPGA, and an FPGA Idelay2 unit is used for implementing accurate delay adjustment on control signals transmitted across the boards, so that the control signals of a receiving end are far away from a metastable state interval, and the storage synchronization of multi-module waveform data is ensured.

The invention aims to realize the following steps:

the invention relates to a multichannel synchronous high-speed data acquisition device, which comprises a processing board and two acquisition sub-boards, wherein the acquisition sub-boards have the same structure, acquire data in a parallel mode and send the data to the processing board; the acquisition daughter board and the processing board are internally provided with a clock management module, a multi-ADC data synchronization module, a multi-channel sampling synchronization module, a clock synchronization timestamp adding and link establishing sequence management module and a data storage synchronization module based on triggering; the clock management module provides a synchronous clock for the whole system, the ADC samples an analog signal under the drive of the sampling clock to obtain sampling point data and then transmits the sampling point data to the acquisition FPGA, the multi-ADC data synchronization module adds a timestamp mark to the sampling point data in the ADC, carries out sequence adjustment on the sampling data in the acquisition FPGA, adjusts the sampling point with a mark bit into first path data, realizes the synchronization of multi-ADC data flow by increasing dynamic time delay, and manages the working sequence of three independent processes of clock synchronization, a timestamp function and a JESD204B link by the clock synchronization timestamp adding and link establishing sequence management module to solve the conflict of the three in the multi-ADC data synchronization process, the multi-channel sampling synchronization module avoids the random delay caused by the time sequence of the clock and a device clock of a sending end by adjusting the phase relation of the timestamp signal and the clock of the device of the sending end, and corrects the inherent delay between channels, the trigger-based data storage synchronization module realizes the synchronous storage of data among different acquisition boards by accurately delaying and adjusting the control signals transmitted across the boards; therefore, the whole device realizes the synchronization of multi-channel high-speed data acquisition, the delay among the channels is not more than 25ps, and the device has the characteristics of high synchronization rate, high precision and the like.

Drawings

FIG. 1 is a block diagram of an embodiment of a multi-channel synchronous high-speed data acquisition device according to the present invention;

FIG. 2 is a diagram of one embodiment of a clock tree cascade structure;

FIG. 3 is a block diagram of one embodiment of the clock distribution of the present system;

FIG. 4 is a schematic diagram of a sample point timestamping;

FIG. 5 is a schematic diagram of sample point sequence adjustment;

FIG. 6 is a schematic diagram of adding FIFO to increase dynamic delay;

FIG. 7 is a system initialization flow diagram;

FIG. 8 is a schematic diagram of monitoring SYSREF valid edge timing violations via registers;

FIG. 9 is a data stream alignment and correction flow;

FIG. 10 is a schematic diagram of a data transmission and storage process in an FPGA.

Fig. 11 is a control signal timing analysis model.

Detailed Description

The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.

Examples

Fig. 1 is a structural diagram of an embodiment of a multichannel synchronous high-speed data acquisition device according to the present invention.

In this embodiment, as shown in fig. 1, the multichannel synchronous high-speed data acquisition device of the present invention includes a processing board and two acquisition sub-boards, where the two acquisition sub-boards have the same structure, and acquire data in a parallel manner and then send the data to the processing board;

the collecting sub-board and the processing board comprise the following modules:

the clock management module comprises a crystal oscillator and three clock chips, wherein the clock chips adopt a clock tree cascade structure and provide synchronous clock signals of enough channels for the whole system;

in this embodiment, the processing board receives and processes the sampling data of the 2 acquisition daughter boards, and also takes the roles of controlling and reading back the state of the FPGA of the acquisition board and providing a clock source for each acquisition module clock chip. The clock chip of the processing board takes a 10MHz clock output by the crystal oscillator as a source and provides a clock source and a synchronous signal for the clock chip of the acquisition board. In order to improve the reliability of the system, the signal paths of the board level all adopt a differential signal transmission mode.

Clock synchronization is the basis for system synchronization. If the clocks of the acquisition sub-boards are in an asynchronous relation, the clock phase relation of the acquisition sub-boards changes randomly after each electrification, and the sampled data are naturally difficult to align; the other hidden danger of clock asynchronization is uncertainty of control signals, a system needs two acquisition boards to receive the control signals sent by a processing board in the same clock period, the control signals span multiple FPGAs, are generated by sequential logic and are also received by the sequential logic, if the clocks of a sending side and a receiving side are in an asynchronous relation and are processed as asynchronous signals, the metastable state of asynchronous signal transmission is difficult to avoid, the control signals have errors of 1 clock period, and one clock period corresponds to 8 sampling points, so the errors of 8 sampling points can be amplified in data. From this point of view, the system also ensures that the operating clocks of the different FPGAs are synchronized.

For a single clock chip, the outputs of the channels are in synchronous alignment. However, due to the fact that the number of channels of the system is large, the JESD204B protocol needs additional clock signals, and the like, the number of channels of a single clock chip is not enough to drive all branches, and therefore the system adopts multiple clock chips to provide clocks. Similar to the synchronization of multiple ADCs, the outputs of the clock chips also need to be synchronized.

The basis of multi-clock chip synchronization is a cascaded structure called a clock tree, also called a clock array structure, as shown in fig. 2. The method is characterized in that a first-stage clock chip provides a clock source for a second-stage clock chip through a clock output channel, then a pulse output channel provides a synchronous pulse signal for the second-stage clock chip, the second-stage clock chip receives the synchronous signal and responds to the signal to adjust the phase of the clock output channel, and the synchronous pulse is continuously transmitted to a third-stage clock chip through the output channel configured in a pulse mode. After responding to the synchronous pulse event, the clocks output by the clock chips in the same stage have a fixed phase relationship. In practical application, the stage number of the clock cascade structure is determined according to the requirement of the system on the number of clock channels, and the clock signal and the pulse signal output by the last stage are sent to the FPGA and the ADC of the system. The clock tree cascade structure not only solves the problem that fan-out channels of single clock chips are insufficient, but also provides a solution for synchronizing a plurality of clock chips.

A clock chip on the processing board provides a clock source for a clock chip on the acquisition board through a clock output channel, and then provides a synchronous pulse signal for the clock of the acquisition board through a pulse output channel, the clock chip of the acquisition board responds to the signal after receiving the synchronous signal to adjust the phase of the clock output channel and provides the pulse signal for the FPGA and the ADC of the acquisition board through the output channel configured in a pulse mode, thereby realizing the synchronous clock output of the multi-clock chip;

the specific implementation of the clock tree in the present system is shown in fig. 3, and a two-stage clock tree structure is adopted in the present system. On the processing bottom plate, a crystal oscillator chip provides a clock source of 10MHz for a first-stage clock chip A, and the first-stage clock chip A aligns an output clock phase and transmits a synchronous pulse signal to an acquisition board clock chip by responding to a SYNC command from an FPGA. On the acquisition daughter board, the second-stage clock chip B1 and the clock chip B2 receive the phase-adjusted 10MHz clock of the first-stage clock chip a as a main clock source, and respond to the RFSYNC synchronization pulse from the first-stage clock chip a. For the second-stage clock chip, responding to the RFSYNC synchronization signal sent from the first-stage clock chip A comprises two functions: firstly, performing output clock phase alignment, including performing phase alignment on a 2.5GHz sampling clock (DCLK) transmitted to an ADC and an 156.25MHz reference clock (REFCLK) of an FPGA; the second is to issue a SYSREF pulse to the FPGA and ADC that is used for JESD204B link setup and time stamping.

The multi-ADC data synchronization module comprises a timestamp adding module, a sampling data sequence adjusting module and a dynamic time delay adding module;

in this embodiment, each acquisition daughter board includes 4 ADCs with 2.5GSPS sampling rate and 12bits resolution, the ADCs samples 4 analog signals and then transmits the sampled data to the FPGA, and the clock chip provides the 2.5GHz sampling clock SCLK required by the ADCs and the reference clock REFCLK required by the GT port of the FPGA. According to the JESD204B protocol, the clock chip also sends SYSREF pulses to all the ADCs and the FPGAs to be used as the reference for multi-frame clock phase alignment; the SYNC signal is transmitted to the ADC by the FPGA, the next LMFC after the SYSREF signal is received by the FPGA is pulled up, the ADC is indicated to enter an ILAS stage, and the stage is used for realizing multi-channel data synchronization between single links. After ILAS, the user data transfer phase is entered, i.e. the ADC starts sending sampled data to the FPGA. After being received by the FPGA, the sampling data is decoded, slowed down and the like through the JESD204IP core and converted into sampling data which can be processed by a user. After some preprocessing is carried out on the sampling data, the data of the two acquisition modules are collected to the processing module FPGA again, and a higher-level data processing task is carried out.

The time stamp adding module opens the time stamp function of the ADC chip according to the ADC data manual; the ADC samples an input analog signal under the drive of the SCLK, and converts the analog signal into 12-bit sampling point data; then, adding 4-bit redundant control bits for 12-bit sampling point data through a serial channel mapping unit in the ADC to form 16-bit serial channel data, wherein the value of the redundant control bits is 0 under the default condition, when a rising edge of a timestamp marking signal SYSREF sent by a clock management module arrives, marking a first sampling point behind the rising edge, specifically, setting one of the redundant control bits to be 1, and finishing the addition of a timestamp;

the ADC (AD96XX) adopted in this embodiment has no dedicated timestamp port, but uses SYSREF as a timestamp signal, and after reading the technical manual, according to the register configuration specification, the function of using SYSREF for local multi-frame clock phase alignment is disabled, instead of the timestamp function, and the AD96XX series uses 16bits to transmit 12bits of sample points, so that one bit of the remaining 4 bits is selected to carry a timestamp. The process of adding the time stamp marking bit to the sample point by the ADC is shown in fig. 4, a device clock SCLK samples SYSREF, when a jump of a SYSREF signal from a low level to a high level is detected, data of a first sampling point is marked, and the specific method of performing the time stamp marking is to select one of 4 redundant control bits corresponding to a sampling point to be marked to perform a position 1 operation, where the control bits are all 0 at any time.

The sampling data sequence-adjusting module adjusts the sequence of K paths of parallel data which are transmitted to the FPGA by the ADC and are subjected to speed reduction: detecting the position of a timestamp mark appearing in parallel data, and marking the position as L, wherein L is more than or equal to 1 and less than or equal to K; delaying the 1 st to L-1 st paths of the original parallel data by two DCLK periods, and delaying the first to the second paths of the original parallel data by one DCLK period to form delayed parallel data; finally, rearranging the delayed parallel data in sequence from the L-th path to the K-th path and from the 1 st path to the L-1 st path to form the parallel data after sequence adjustment;

because of the limitation of the clock rate of the FPGA, the sampling data of the ADC must be received and transmitted by reducing the clock rate and increasing the bit width, the data bit width of the single-chip ADC of the system is 12bits, the clock rate is up to 2.5GHz, the clock rate can be reduced to 312.5MHz after passing through the FPGA deserializer, the bit width can be correspondingly increased to 96bits, which means that in the FPGA, one data clock period is aligned to 8 sampling points, and the sampling point carrying the timestamp marker can be any one path in 8 paths of data, so the sequence of each path of data stream is firstly adjusted, and the sampling point carrying the timestamp marker is fixed on the first path in 8 paths of data.

The sampling point sequence adjustment sequence is as shown in fig. 5, the sampling point sequence adjustment is started after the Timestamp (Timestamp mark signal) is detected to be high, the sampling point (D4) carrying the Timestamp mark is moved to the position of the original first sampling point, the positions of the remaining 7 sampling points are complemented by 3 sampling points (D5, D6 and D7) after D4 and 4 sampling points (D8, D9, D10 and D10) before the next clock cycle in the same clock cycle, and the data is effectively enabled to be pulled at the moment

The dynamic delay increasing module uses a plurality of FIFOs to respectively increase dynamic delay for the parallel data after each channel is subjected to sequence adjustment, and when the parallel data after a certain channel is subjected to sequence adjustment is detected to contain a timestamp flag bit '1', the write enable of the FIFO of the corresponding channel is started; when the parallel data after all the channels are sequenced are detected to contain a timestamp flag bit '1', starting the read enable of the FIFO of all the channels, keeping the write enable on, keeping the read and write balanced, and dynamically increasing the delay of the parallel data of each channel to form a final user data stream;

after the sequence of the data stream is adjusted, the phase difference of each channel data in integral multiple clock cycles exists, namely: Δ t ± N × 3.2ns, N ═ 1,2,3, …; to do this, we can send the sequentially adjusted data stream to a FIFO array, one FIFO for each piece of ADC data. The write bit width and the read bit width of the FIFO are kept consistent and are both 96 bits. The write enable of the FIFO is data valid enable; when it is detected that all the FIFOs have data written therein, the read enable is turned on together with all the FIFOs, the write enable is also turned off, and the FIFOs keep a read-write balanced state of reading while writing, so that corresponding delay is added to the fast-path data and the slow-path data are kept aligned, and a process of adding dynamic delay to the fast-path data through the FIFOs is shown in fig. 6.

The system comprises a clock synchronization, timestamp addition and link establishment sequence management module, a FPGA on a system processing board sends synchronization pulses to the time management module in three times, and the specific processing flow is as follows:

after the synchronous pulse sent by the FPFA for the first time is sent to the clock manager, the clock distribution network in the clock manager carries out reset operation to complete the clock synchronization process; then, the FPGA sends an SPI command to the clock manager, on one hand, the response of the clock distribution network to the synchronous pulse is shielded, and on the other hand, the response of the pulse distribution network to the synchronous pulse is opened; meanwhile, the FPGA also sends an SPI command to the ADC, the default register data of the ADC is rewritten, the default multi-frame clock alignment function in the ADC is forbidden, and the timestamp function is turned on;

after the synchronous pulse sent by the FPFA for the second time is sent to the clock manager, the pulse distribution network in the clock manager carries out reset operation to generate a reference pulse SYSREF of the system, and the reference pulse SYSREF is respectively fed back to the FPGA and all the ADCs; after receiving the reference pulse SYSREF, the gigabit transceiver module in the FPGA raises the SYNCB signals sent to each ADC by the FPGA, and after receiving the raised SYNCB signals, the ADC starts to transmit serial channel data streams to the FPGA to complete the data transmission link establishment process;

after the synchronous pulse sent by the FPFA for the third time is sent to the clock manager, the pulse distribution network in the clock manager carries out reset operation again, generates the reference pulse SYSREF of the system for the second time and feeds back the reference pulse SYSREF to the FPGA and all the ADCs respectively; after the ADC receives the reference pulse SYSREF, marking the first sampling point data after the rising edge moment of the reference pulse SYSREF, and keeping a certain position 1 and the rest positions 0 in the redundant control position of the serial channel data corresponding to the first sampling point data to finish the timestamp marking process;

during actual debugging, the clock synchronization, the timestamp function and the JESD204B link establishment are found to have conflicts, when the clock chip responds to the SYNC/RFSYNC event, the clock phase adjustment and the pulse transmission are carried out simultaneously, and the latter-stage clock chip carries out the same action when receiving the pulse signal. However, the phase of the input clock source of the subsequent clock chip is unstable, and the phase alignment of the output clock performed in this case naturally fails.

Similar problems also occur when the rear-stage clock chip is replaced by the ADC and the FPGA, if the ADC receives SYSREF pulses when a sampling clock or the FPGA is unstable in phase of a reference clock, the situation that the pulses cannot be identified occurs with a great probability, and two consequences are caused: 1. the link cannot be established and 2, the timestamp cannot be marked.

Finally, JESD204B link establishment and timestamp marking are two separate processes, and timestamp marking cannot be added when the ADC sends the K code or ILAS. Therefore, three process sequences need to be managed.

The complete configuration flow is shown in fig. 7, where the SYNC arrow indicates that the FPGA of the processing board sends SYNC synchronization pulses to the clock chip of the processing board, and the core idea of the flow is to divide the clock phase alignment of the clock chip and the pulse transmission to the backward stage into two steps. The method comprises the steps that after the clock chip carries out phase adjustment alignment on an output clock channel, after the locking of a phase-locked loop of the clock chip is detected, the SYNC enable of the clock channel is closed to shield a subsequent received SYNC event, the configuration of a pulse channel is unchanged, and the state of propagating synchronous pulses to a later stage is continuously kept. Then, the link establishment process and the timestamp marking process are divided into two steps, specifically, the acquisition board clock chip sends two SYSREF pulses to the ADC and the FPGA. The purpose of the first pulse event is to send a link setup command to the FPGA side, and whether the ADC receives the pulse does not have any effect, since the timestamp function is not valid at this time, as described above; the second pulse event is to add a timestamp mark to the sampling data of the ADC, and whether the pulse is generated by the FPGA will not be affected, because the IP core of the FPGA JESD204B is set to respond to the pulse only once, and therefore, no response is made to the subsequent SYSREF after the link is established.

So far, after the data transmission link is established, the sampled data carrying the timestamp marker will enter the FPGA and perform data alignment according to the timestamp synchronization content described above.

The multichannel sampling synchronization module comprises ADC time sequence adjustment, interchannel delay measurement and interchannel delay correction;

the ADC time sequence adjustment reads back data of an internal register of the ADC through an SPI communication protocol, monitors a SYSREF establishment/maintenance time window register of the ADC, if the read-back value of the register is 1, the time sequence violation is represented, namely the effective edge of the SYSREF appears in the window of the effective edge of the SCLK, the SYSREF does not meet the time sequence condition of the SCLK, and at the moment, the corresponding SYSREF delay value sent to the ADC is gradually increased until the time sequence violation is not displayed after the reinitialization, namely the read-back value is 0;

the inter-channel delay measurement is implemented by selecting one channel as a reference channel and the other channels as channels to be measured, outputting a sine signal with a known frequency by using a signal source, inputting the sine signal into the reference channel and the channels to be measured by using a power divider and an isometric transmission line, collecting user data collected by the reference channel and the channels to be measured in the same time period by using an FPGA debugging tool ILA, calculating phase difference among the channels and further obtaining inter-channel delay;

the interchannel delay correction is realized by gradually increasing the SCLK delay and the SYSREF delay of the channel to be detected according to the steps, so that the increased delay amount is as close to an interchannel delay value as possible until the absolute value of the difference between the increased delay amount and the measured interchannel delay value is smaller than the adjustable minimum step of the clock chip delay;

delay value differences of a random part and a fixed part also exist in multi-channel data subjected to FPGA soft logic alignment. The random delay is derived from a metastable state phenomenon caused by timing violation of a SYSREF signal and a device clock, and the metastable state elimination of the random delay can be avoided by adjusting the phase relationship of the SYSREF signal and the device clock; the fixed delay, which results from the data transmission path disparity, can be reduced to less than a programmable delay value by a previously deployed time stamping mechanism in conjunction with delay adjustment as will be described below.

As shown in fig. 8, the ADC used in the embodiment of the present invention includes a SYSREF setup time and hold time monitor register, and if the valid edge of SYSREF appears in the window of the CLK valid edge, the register read value will be 1, so as to warn the user that the SYSREF does not satisfy the timing condition of CLK, and the window width may be increased to leave more margin. After the clock chip provides a stable clock for the ADC, sending a SYSREF pulse signal, and reading back the register value, wherein if the value is 0, no adjustment is needed; if it is 1, the delay value of the corresponding SYSREF pulse is increased, and the above process is repeated until the read-back value becomes 0. For the present embodiment, a sampling clock period is 400ps, and the programmable delay value of the output channel of the clock chip is 25ps, which can be adjusted to step from 0 to 23, so that a proper value can be always found out so that the valid edge of SYSREF does not fall within the timing violation window of CLK. Finally, it is noted that all ADCs must do this.

And then determining a reference channel, wherein the other channels are to-be-detected channels, and inputting the same signal to measure the phase difference between the reference channel and the to-be-detected channel. The signal is obtained by dividing a signal source into two parts through a power divider and is connected to a system through equal-length transmission lines; the method of phase difference measurement may employ cross-correlation phase difference measurement, three-parameter sine fitting, or other signal phase difference measurement algorithms, which are not discussed in detail herein. The result of the calculation may be represented by the following sub-formula: and delta T is K T + C D + m, wherein delta T is the calculated inter-channel delay, T is the sampling clock period, D is the programmable delay value of the clock chip, K and C are integers which are more than or equal to 0, and m is the delay part which is less than D. The meaning of this equation is to divide the interchannel delay value into K clock cycles, C adjustable minimum steps and the remaining unadjustable delay m parts. Taking this embodiment as an example, if T is 400ps and D is 25ps, and Δ T is measured to be 736ps, Δ T can be divided into: Δ t-736 ps-1-400 ps + 13-25 ps +11 ps;

delaying the SYSREF signal of the late channel by K delay values (using a digital delay channel different from D) may advance the late signal data by K clock cycles, since the sysrf signal moves by an integer multiple of the clock cycle, no new timing violations are generated; the SYSREF signal and the CLK signal for the lagging channel are delayed by C delay values (not for the model delay channel of T) at the same time, and the lagging data can be advanced by C by D time values. Through the above decomposition, m is always smaller than D, i.e. 25ps for the present embodiment. The complete data stream alignment and correction flow described above is shown in fig. 9.

Based on the data storage synchronization module that triggers, after the acquisition board data synchronization, select waveform data that gets in a period of time and send to processing board FPGA and handle and show at the host computer, this process is called to trigger, keep in the Block FIFO that another level realized triggering in the acquisition board from realizing synchronous Align FIFO, Block FIFO's reading and writing enable signal is sent to two acquisition board FPGA by processing board FPGA, and use FPGA Idelay2 unit to implement accurate delay adjustment to the control signal of striding the board transmission, make the receiving terminal control signal keep away from the metastability interval, guarantee the storage synchronization of many module waveform data.

After the data in the acquisition board FPGA are synchronized, due to the limitation of the number and the speed of IO ports, only the waveform data in a period of time can be selected and sent to the processing board FPGA for processing and displaying on an upper computer, and the selection process is called triggering. The selected data is temporarily stored in another stage of FIFO in the acquisition board, the stage of FIFO used as data stream synchronization is called Align FIFO, and the stage of FIFO used as data temporary storage to realize trigger function is called Block FIFO. The way triggers are generated is varied, but is ultimately reflected in the read and write enable of the Block FIFO.

Table 1 triggering Block FIFO read-write control of different stages of the system

Phases	Writing	Reading
			Pre-trigger	√	×
Waiting for a trigger	√	V (but data not valid)
			After triggering	√	×
After full writing	×	Hook (effective data)

As shown in table 1, the pre-trigger is to ensure that waveform data in a period of time before the trigger can also be observed, at this time, the Block FIFO is written and not read, and after the number of points required by the pre-trigger is written, the Block FIFO enters a waiting trigger phase. And waiting for a trigger phase, writing and reading the Block FIFO while keeping the data updating, and at the moment, outputting invalid data by the Block FIFO. When the trigger signal comes, the Block FIFO closes the read enable until the write is full. And the data in the Block FIFO after being fully written is the data which is to be transmitted to the processing board and displayed on the upper computer, at the moment, the effective enabling of the data is set to be effective, and all the data is transmitted to the rear end to be processed and displayed.

The bit width of the FIFO is 96bits, and the width of the data bus of the FPGA of the final acquisition board and the FPGA of the processing board is only 12bits, so that in the reading stage after the FIFO is fully written, a read enable is generated every eight clock cycles, the read enable lasts for one clock cycle, and the data stream of converting 96bits data into 12bits is required to be sent to the FPGA of the processing board in the interval period from the effective read enable of the last read enable to the effective read enable of the next read enable. The whole transmission flow is as shown in fig. 10, and the JESD204B IP core performs operations such as descrambling, demapping, bit width reduction and the like on the ADC sampling data. The Align Fifo module implements the timestamp synchronization logic described above. The Block Fifo receives the synchronous data transmitted by the previous stage, and the read-write enabling signals of the Block Fifo are transmitted to the two acquisition boards by the processing board FPGA so as to achieve the purpose of synchronous storage. The Data Tx SDR module realizes the parallel-serial conversion, and transmits the sampling Data to the processing board FPGA by calling the FPGA Select IO IP core. The Rmaster Interface module is connected with the processing board through an additional data bus, can receive control commands issued by the upper computer and can also upload status signals to the upper computer.

The two acquisition sub-boards of the system need to receive three control signals sent by the processing board at the same time: start, FIFO _ wen, FIFO _ ren. The signals are transmitted to the input end of the D trigger in the FPGA of the acquisition board from the output end of the D trigger in the FPGA of the processing board, the transmission delay of the signals consists of three parts, namely internal routing delay of the FPGA of the processing board, PCB routing delay and internal routing delay of the FPGA of the acquisition board. When the transmission delay is compared with the clock cycle, the control signal is difficult to satisfy the time sequence condition of the receiving end D trigger, the metastable state is generated, and the waveform storage and transmission of the two acquisition sub-boards generate an error of 8 sampling points in one clock cycle.

The method adopted by the embodiment is as follows: and adjusting the internal routing delay of the FPGA of the acquisition board to prevent the jumping edge of the data signal from appearing in a metastable state window of a target clock. The specific implementation is that an Idelay2 module integrated in the Xilinx 7 series FPGA is used for gradually increasing the delay of an input signal by taking 78ps as a step, so that a control signal is far away from a metastable state interval of a target clock.

The corresponding time sequence analysis model is shown in fig. 11. T is_COIs the delay from the clock to the output of the FPGA flip-flop, T_NETIs a control signal transmission delay, T_SYS-CLK2-T_SYS-CLK1＝T_SKEW. In addition, T_PERIODIs the system clock period, T_SETUPAnd T_HOLDRespectively establishing and holding time, T, for FPGA D flip-flops_SLACK.SETUAnd T_SLACK.HOLDThe delay added by the Idelay2 module is Δ T, establishing and holding time margins, respectively, for the FPGA D flip-flops_NET。

According to the theory of static timing analysis, there are two formulas:

T_SLACK.SETUP＝T_PERIOD+T_SKEW-T_CO-T_NET-T_SETUP-ΔT_NET

T_SLACK.HOLD＝T_CO+T_NET-T_SKEW-T_HOLD+ΔT_NET

further, it is possible to obtain: t is_SKEW-T_CO-T_NET+T_HOLD＜T_SKEW-T_CO-T_NET+T_PERIOD-T_SETUPThe delay added by Idelay2 needs to be at (T)_SKEW-T_CO-T_NET+T_HOLD,T_SKEW-T_CO-T_NET+T_PERIOD-T_SETUP) Within the interval (c). In the case where the above parameters are not accurately known, the delay value can be adjusted step by repeatedly sending a control signal to see if the data for effective edge alignment are consistent, preferably Δ T_NETAt (T)_SKEW-T_CO-T_NET+T_HOLD,T_SKEW-T_CO-T_NET+T_PERIOD-T_SETUP) In the middle of the interval. After the delay value is determined, the constraint of fixed wiring is carried out on related circuits inside the FPGA of the acquisition board and the FPGA of the processing board, and the change of wiring delay after the FPGA carries out layout wiring again is avoided.

Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.