阅读说明：本技术 半导体结构 (Semiconductor structure ) 是由 林庭佑 涂祈吏 许书维 于 2019-01-17 设计创作，主要内容包括：本发明提供一种半导体结构,包含：半导体基底、埋置层、一对第一阱、第二阱、体掺杂区、以及第一重掺杂区。此半导体基底具有第一导电类型。此埋置层位于此半导体基底上且具第二导电类型。此对第一阱位于此埋置层上且具有第二导电类型。此第二阱位于此埋置层上并位于此对第一阱之间,其具有第一导电类型。此体掺杂区位于此第二阱中,其具有此第一导电类型。此第一重掺杂区位于此体掺杂区中,其具有第一导电类型。在上视图中,此第一重掺杂区以及此对第一阱沿着第一方向延伸,并且此第一重掺杂区延伸超出此对第一阱的二个相反边缘。本发明可改善晶体管的导通均匀性、改善阱之间的漏电流、以及降低电阻与主动区面积。(The present invention provides a semiconductor structure, comprising: the semiconductor device comprises a semiconductor substrate, a buried layer, a pair of first wells, a second well, a body doping region and a first heavily doped region. The semiconductor substrate has a first conductivity type. The buried layer is located on the semiconductor substrate and has a second conductive type. The pair of first wells is located on the buried layer and has a second conductivity type. The second well is located on the buried layer and between the pair of first wells, and has the first conductivity type. The body doped region is in the second well and has the first conductive type. The first heavily doped region is in the body doped region and has a first conductivity type. In the top view, the first heavily doped region and the pair of first wells extend along the first direction, and the first heavily doped region extends beyond two opposite edges of the pair of first wells. The invention can improve the conduction uniformity of the transistor, improve the leakage current between wells, and reduce the resistance and the area of the active region.)

1. A semiconductor structure, comprising:

a semiconductor substrate having a first conductivity type;

a buried layer on the semiconductor substrate and having a second conductivity type different from the first conductivity type;

a pair of first wells on the buried layer and having the second conductivity type;

a second well on the buried layer and between the pair of first wells, and having the first conductivity type and a first doping concentration;

a bulk doped region in the second well having the first conductivity type and a second doping concentration;

a first heavily doped region in the body doped region, having the first conductivity type and a third doping concentration, wherein the third doping concentration is greater than the second doping concentration, and the second doping concentration is greater than the first doping concentration; and

in the top view, the first heavily doped region and the pair of first wells extend along a first direction, and the first heavily doped region extends beyond two opposite edges of the pair of first wells along the first direction.

2. The semiconductor structure of claim 1, wherein in a top view, the second well has a first length extending along the first direction, and the pair of first wells has a second length extending along the first direction, wherein the first length is less than the second length.

3. The semiconductor structure of claim 1, wherein in a top view, the first heavily doped region exceeds a first edge of the second well by a first distance along the first direction, and the pair of first wells exceeds the first edge of the second well by a second distance along the first direction, wherein the first distance is greater than the second distance.

4. The semiconductor structure of claim 1, wherein the depth of the first heavily doped region is less than about 0.5 microns and the depth of the body doped region is in the range of about 0.5 microns to about 1 micron.

5. The semiconductor structure of claim 1, wherein the second well has a width along a second direction of no more than 2 microns.

6. The semiconductor structure of claim 1, further comprising a source/drain region of the second conductivity type, wherein the source/drain region is respectively located in the pair of first wells.

7. The semiconductor structure of claim 6, wherein the source region is a first drift distance from an interface between the pair of first wells and the second well, and the drain region is a second drift distance from the interface between the pair of first wells and the second well, wherein neither the first drift distance nor the second drift distance exceeds 2 microns.

8. The semiconductor structure of claim 7, wherein the first drift distance is different from the second drift distance, and the pair of first wells is asymmetric to the first heavily doped region.

9. The semiconductor structure of claim 1, wherein the pair of first wells are symmetric to the first heavily doped region.

10. The semiconductor structure of claim 1, wherein the second well further comprises a pair of second heavily doped regions having the second conductivity type, wherein the first heavily doped region is located between the pair of second heavily doped regions.

11. The semiconductor structure of claim 10, further comprising a pair of gate regions located above the pair of first wells and the second well, wherein the pair of gate regions partially cover the pair of second heavily doped regions.

12. The semiconductor structure of claim 1, further comprising a pair of third wells on the buried layer and having the first conductivity type, wherein the pair of first wells is between the pair of third wells.

13. The semiconductor structure of claim 1, wherein the end of the first heavily doped region is shaped as an I-type or a T-type in top view.

14. The semiconductor structure of claim 1, wherein in a top view, at least one additional pair of first heavily doped regions is located around the pair of first wells.

15. A semiconductor structure, comprising:

a semiconductor substrate having a first conductivity type;

a buried layer on the semiconductor substrate and having a second conductivity type different from the first conductivity type;

a pair of first wells on the buried layer and having the second conductivity type;

a pair of second wells on the buried layer and between the pair of first wells, respectively, and having the first conductivity type and a first doping concentration;

a pair of body doped regions respectively located in the pair of second wells and having the first conductivity type and a second doping concentration;

a pair of first heavily doped regions respectively located in the pair of body doped regions and having the first conductivity type and a third doping concentration, wherein the third doping concentration is greater than the second doping concentration, and the second doping concentration is greater than the first doping concentration;

a third well on the buried layer and between the pair of second wells, and having the second conductivity type; and

in the top view, the pair of first heavily doped regions and the pair of first wells extend along a first direction, and the pair of first heavily doped regions extend beyond two opposite edges of the pair of first wells along the first direction.

16. The semiconductor structure of claim 15, wherein in a top view, the pair of second wells has a first length extending along the first direction, and the pair of first wells has a second length extending along the first direction, wherein the first length is less than the second length.

17. The semiconductor structure of claim 15, wherein in a top view, the pair of first heavily doped regions exceeds a first edge of the pair of second wells by a first distance along the first direction, and the pair of first wells exceeds the first edge of the pair of second wells by a second distance along the first direction, wherein the first distance is greater than the second distance.

18. The semiconductor structure of claim 15, wherein the depth of the pair of first heavily doped regions is less than about 0.5 microns, the depth of the pair of body doped regions is in a range from about 0.5 microns to about 1 micron, and the width of the pair of second wells along a second direction is no more than 2 microns.

19. The semiconductor structure of claim 15, further comprising a second heavily doped region in the third well and having the second conductivity type.

20. The semiconductor structure of claim 19, further comprising a source/drain region of the second conductivity type, wherein the source/drain region is respectively located in the pair of first wells.

21. The semiconductor structure of claim 20, wherein the source/drain regions are spaced apart from an interface between the pair of first wells and the second well by a first drift distance, and the second heavily doped region is spaced apart from an interface between the second well and the third well by a second drift distance, wherein the first drift distance and the second drift distance are each no more than 2 μm.

22. The semiconductor structure of claim 15, wherein the pair of second wells further comprises a pair of third heavily doped regions having the second conductivity type, respectively, wherein one of the pair of first heavily doped regions is located between the pair of third heavily doped regions.

23. The semiconductor structure of claim 22, further comprising a plurality of pairs of gate regions located over the pair of first wells and the pair of second wells and the third well, wherein the plurality of pairs of gate regions partially cover the pair of third heavily doped regions.

24. The semiconductor structure of claim 15, wherein in the top view, at least one additional pair of first heavily doped regions is located around the pair of first wells and connected to the pair of first heavily doped regions.

Technical Field

The present invention relates to semiconductor structures, and more particularly to a bidirectional conducting semiconductor structure.

Background

A battery disconnect switch (also referred to as a bidirectional power switch) is a bidirectional switch that can be used to control whether current is allowed to flow between a battery and a load or between a battery and a charger. A conventional power metal-Oxide-Semiconductor Field-Effect Transistor (power MOSFET) can be used to form a battery-isolated switch, but a single P-N junction between a source and a drain included in a single power MOSFET cannot block a bidirectional current.

Nowadays, the ability to control bi-directional current between two or more power sources is almost a necessary function for all battery-split switches, and the use of split power metal oxide semiconductor field effect transistors (discrete power MOSFETs) requires two devices connected back-to-back, where the two devices have a common source or drain region. The total resistance of the battery disconnect switch is twice that of the power mosfet alone, and problems such as excessive current density, leakage current, and non-uniform conduction are easily caused.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor structure, comprising: the semiconductor device comprises a semiconductor substrate, a buried layer, a pair of first wells, a second well, a body doping region and a first heavily doped region. The semiconductor substrate has a first conductivity type. The buried layer is on the semiconductor substrate and has a second conductivity type different from the first conductivity type. The pair of first wells is located on the buried layer and has a second conductivity type. The second well is located on the buried layer and between the pair of first wells, and has a first conductivity type and a first doping concentration. The body doped region is in the second well and has the first conductivity type and a second doping concentration. The first heavily doped region is arranged in the body doped region and has a first conductivity type and a third doping concentration, wherein the third doping concentration is greater than the second doping concentration, and the second doping concentration is greater than the first doping concentration. In the top view, the first heavily doped region and the pair of first wells extend along a first direction, and the first heavily doped region extends beyond two opposite edges of the pair of first wells along the first direction.

Some embodiments of the present invention provide a semiconductor structure, comprising: the semiconductor device comprises a semiconductor substrate, a buried layer, a pair of first wells, a pair of second wells, a pair of body doped regions, a pair of first heavily doped regions and a third well. The semiconductor substrate has a first conductivity type. The buried layer is on the semiconductor substrate and has a second conductivity type different from the first conductivity type. The pair of first wells is located on the buried layer and has a second conductivity type. The pair of second wells are located on the buried layer and between the pair of first wells respectively, and have a first conductivity type and a first doping concentration. The pair of body doping regions are respectively located in the pair of second wells and have a first conductivity type and a second doping concentration. The pair of first heavily doped regions are respectively located in the pair of body doped regions and have a first conductivity type and a third doping concentration, wherein the third doping concentration is greater than the second doping concentration, and the second doping concentration is greater than the first doping concentration. The third well is located on the buried layer and between the pair of second wells, and has a second conductivity type. In the top view, the pair of first heavily doped regions and the pair of first wells extend along a first direction, and the pair of first heavily doped regions extend beyond two opposite edges of the pair of first wells along the first direction.

The invention can improve the conduction uniformity of the transistor, improve the leakage current between wells, and reduce the resistance and the area of the active region.

Drawings

The embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the embodiments of the present invention.

FIG. 1 is a partial top view illustrating an exemplary semiconductor structure, in accordance with some embodiments of the present invention;

FIG. 2 is a cross-sectional view of a segment A1-A1 corresponding to the semiconductor structure shown in FIG. 1, in accordance with some embodiments of the present invention;

FIG. 3 is a schematic cross-sectional view illustrating a line A2-A2 corresponding to the semiconductor structure shown in FIG. 1, in accordance with some embodiments of the present invention;

FIG. 4 is a cross-sectional view of a segment A3-A3 corresponding to the semiconductor structure shown in FIG. 1, in accordance with another embodiment of the present invention;

FIG. 5 illustrates a partial top view of an exemplary semiconductor structure, in accordance with further embodiments of the present invention;

FIG. 6 is a partial top view illustrating an exemplary semiconductor structure, in accordance with yet other embodiments of the present invention;

FIG. 7 illustrates a partial top view of an exemplary semiconductor structure, in accordance with some embodiments of the present invention;

FIG. 8 is a schematic cross-sectional view illustrating a line B1-B1 corresponding to the semiconductor structure shown in FIG. 7, in accordance with some embodiments of the present invention;

FIG. 9 is a schematic cross-sectional view illustrating a line B2-B2 of the semiconductor structure of FIG. 7, in accordance with another embodiment of the present invention;

FIG. 10 illustrates a partial top view of an exemplary semiconductor structure, in accordance with some embodiments of the present invention;

FIG. 11 is a cross-sectional view of a line C-C corresponding to the semiconductor structure shown in FIG. 10, in accordance with some embodiments of the present invention;

FIG. 12 illustrates a partial top view of an exemplary semiconductor structure, in accordance with other embodiments of the present invention;

FIG. 13 is a partial top view illustrating an exemplary semiconductor structure, in accordance with further embodiments of the present invention;

FIG. 14 illustrates a partial top view of an exemplary semiconductor structure, in accordance with yet other embodiments of the present invention.

Reference numerals:

100. 500, 600, 700, 1000, 1200, 1300, 1400-semiconductor structure

101. 701-first well

102. 702 to second well

103. 703-body doped region

104. 704-first heavily doped region

105. 705 to third trap

106. 707 to fourth well

107. 708 to fifth trap

108. 710 active region

200. 800-semiconductor substrate

201. 801 buried layer

202. 802-first conductivity type region

203. 803 to source/drain regions

204. 706-second heavily doped region

205. 805 Gate dielectric layer

206. 806 Gate electrode layer

207. 807 insulating layer

208. 802-metal layer

209-isolation structure

220. 820-grid structure

221. 821-Gate spacer

210. 211, 212, 810, 811, 812 to the heavily doped region

413. 913 epitaxial layer

604. 1104, 1204-additional first heavily doped region

709 to sixth trap

804 to the third heavily doped region

G1, G2-grid electrode

S/D-source/drain electrode

E1, E2-electrode

L1 to first length

L2 to second length

D1 first distance

D2 second distance

W1-Width

W2 first drift distance

W3-second drift distance

H1, H2-depth

A1-A1, A2-A2, A3-A3, B1-B1, B2-B2 and C-section

Detailed Description

The following disclosure provides many embodiments, or examples, for implementing various components of the provided semiconductor structures. Specific examples of components and arrangements thereof are described below to simplify the description of the embodiments of the invention. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments discussed.

Furthermore, spatially relative terms, such as "under …," "under," "lower," "over," "upper," and the like, may be used herein for convenience in describing the relationship of one element(s) or feature(s) to another element(s) or feature(s) in the drawings and will include different orientations of the device in use or operation and the orientation depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.

As used herein, the terms "about", "approximately", "substantial" and "approximately" generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, i.e., the meanings of "about", "about" and "about" can be implied without specifying "about", "about" and "about".

Although the components in some of the described embodiments are described in a particular order, these descriptions may be presented in other logical orders. Other features may be added to the semiconductor structure in embodiments of the present invention. In different embodiments, some components may be replaced or omitted.

Embodiments of the present invention provide a semiconductor structure comprising a novel Floating Body Double Gate (FBDG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). according to some embodiments of the present invention, the semiconductor structure comprising a Floating Body Double Gate Metal Oxide Semiconductor Field Effect Transistor (FBDGMOSFET) may be applied to a lithium Ion Battery split Switch (L, Ion Battery split Switch) or other similar Battery split switches, it should be noted that the application of the embodiments of the present invention is not limited thereto.

First, please refer to fig. 1 with reference to fig. 2-4. Fig. 1 is a top view of a portion of an exemplary semiconductor structure 100 according to some embodiments of the present invention, fig. 2 is a cross-sectional view taken along line a1-a1 shown in fig. 1, fig. 3 is a cross-sectional view taken along line a2-a2 shown in fig. 1, and fig. 4 is a cross-sectional view taken along line A3-A3 shown in fig. 1. It should be understood that not all elements of the semiconductor structure 100 are shown in fig. 1-4 for simplicity in describing embodiments of the present invention.

Referring to fig. 1, a partial top view of an exemplary semiconductor structure 100 is shown, in accordance with some embodiments of the present invention. According to some embodiments of the present invention, the semiconductor structure 100 includes a pair of first wells 101, a second well 102 between the pair of first wells 101, and a body doped region (body doped region)103 and a first heavily doped region 104 located in the second well 102, wherein an end of the first heavily doped region 104 in a top view is shaped as an I-type.

In the top view, according to some embodiments of the present invention, the first heavily doped region 104 and the pair of first wells 101 extend along a first direction, wherein the first heavily doped region 104 extends along the first direction beyond two opposite edges of the pair of first wells 101. in some embodiments, the second well 102 has a first length L1 extending along the first direction, the pair of first wells 101 has a second length L2 extending along the first direction, wherein the first length L1 is less than or equal to the second length L2. in some embodiments, for example, the potential difference of the pair of first wells 101 is greater than 0 volt, and when the first length L1 is less than the second length L2 and the width W1 is less than 2 micrometers (mum), a surface current leakage path (surface leakage path) may be generated to affect the circuit operation.

In the top view, according to some embodiments of the present invention, the distance that the first heavily doped region 104 exceeds the first edge of the second well 102 along the first direction is a first distance D1, and the distance that the pair of first wells 101 exceeds the first edge of the second well 102 along the first direction is a second distance D2, wherein the first distance D1 is greater than or equal to the second distance D2. For example, the first distance D1 may be in a range of about 1 micrometer (um) to about 10 micrometers (um), such as may be 3 micrometers (um), and the second distance D2 may be in a range of about 1 micrometer (um) to about 10 micrometers (um), such as may be 2 micrometers (um), wherein the difference between the first distance D1 and the second distance D2 (i.e., D1-D2) may be in a range of about 0 micrometers (um) to about 10 micrometers (um), such as may be 1 micrometer (um). In some embodiments, when the difference between the first distance D1 and the second distance D2 is greater than 0 micrometer (um), the effect of suppressing the surface current can be achieved. In other embodiments, when the difference between the first distance D1 and the second distance D2 is less than 0 micrometer (um), a leakage path that may generate surface current affects the circuit operation.

According to some embodiments of the present invention, the semiconductor structure 100 includes the body doped region 103 and the first heavily doped region 104 located between the pair of first wells 101 and extending along the first direction, and the leakage current between the pair of first wells 101 can be reduced or avoided by the protection structure formed by the configuration of the body doped region 103 and the first heavily doped region 104. In some embodiments, when the distance between the pair of first wells 101 (e.g., the width W1 in fig. 1) is less than 2 micrometers (um), the configuration of the body doping region 103 and the first heavily doped region 104 can be utilized to avoid generating leakage current. It should be understood that, in order to briefly describe the embodiments of the present invention and to highlight the technical features thereof, not all elements of the semiconductor structure 100 are shown in fig. 1, nor are all elements of the cross-sectional views shown in fig. 2 and 4 shown in fig. 1.

As shown in fig. 1, in the semiconductor structure 100, the pair of first wells 101 is surrounded by the third well 105, the third well 105 is surrounded by the fourth well 106, and the fourth well 106 is surrounded by the fifth well 107, according to some embodiments of the present invention. In some embodiments, the pair of first well 101 and fourth well 106 have a second conductivity type, and the second well 102, third well 105, and fifth well 107 have a first conductivity type opposite to the second conductivity type. In some embodiments, the first conductivity type is p-type, for example, and the second conductivity type is n-type, for example, but the invention is not limited thereto.

As shown in fig. 2, and in conjunction with the top view shown in fig. 1, according to some embodiments of the present invention, the semiconductor structure 100 mainly includes a semiconductor substrate 200 having a first conductivity type, a buried layer 201 having a second conductivity type on the semiconductor substrate 200, a pair of first wells 101 on the buried layer 201, a second well 102 on the buried layer 201 and between the pair of first wells 101, a body-doped region 103 in the second well 102, and a first heavily-doped region 104 in the body-doped region 103. In some embodiments, the pair of first wells 101 has the same second conductivity type as the buried layer 201, and the second well 102, the body doped region 103, and the first heavily doped region 104 have the same first conductivity type as the semiconductor substrate 200. In some embodiments, the first conductivity type is, for example, p-type, and the second conductivity type opposite the first conductivity type is n-type. In some embodiments, the second well 102 has a first doping concentration, the body doped region 103 has a second doping concentration, and the first heavily doped region 104 has a third doping concentration, wherein the third doping concentration is greater than the second doping concentration, and the second doping concentration is greater than the first doping concentration.

As shown in fig. 2, in some embodiments, the semiconductor substrate 200 may be a silicon substrate, but the embodiments of the invention are not limited thereto. For example, the semiconductor substrate 200 may also be an elemental semiconductor (elementary semiconductor) including: germanium (germanium); a compound semiconductor (compound semiconductor) comprising: gallium nitride (GaN), silicon carbide (silicon carbide), gallium arsenide (gallium arsenide), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide), and/or indium antimonide (indium antimonide); an alloy semiconductor (alloy semiconductor) comprising: silicon germanium alloy (SiGe), gallium arsenic phosphide alloy (GaAsP), aluminum indium arsenide alloy (AlInAs), aluminum gallium arsenide alloy (AlGaAs), indium gallium arsenide alloy (GaInAs), indium gallium phosphide alloy (GaInP), and/or indium gallium arsenide phosphide alloy (GaInAsP), or combinations thereof. In some embodiments, the semiconductor substrate may comprise a single crystal substrate, a multi-layer substrate, a gradient substrate, other suitable substrates, or combinations thereof. In some embodiments, the semiconductor substrate 200 has a first conductivity type, which may be, for example, p-type, with dopants such as boron, aluminum, gallium, indium, boron trifluoride ion (BF)₃ ⁺) Or combinations thereof, with a doping concentration of about 10¹⁵/cm³To about 10¹⁶/cm³The range of (1).

As shown in fig. 2, the semiconductor structure 100 includes a buried layer 201 on a semiconductor substrate 200, according to some embodiments of the present invention. In some embodiments, buried layer 201 has a second conductivity type, which may be n-type, and has a dopant concentration of about 10, such as nitrogen, arsenic, phosphorus, antimony ions, or combinations thereof¹⁷/cm³To about 10¹⁸/cm³The range of (1). In some embodiments, the thickness of buried layer 201 may be about 6 micrometers (um). In some embodiments, the buried layer 201 may be formed by an ion implantation (ionization) process.

As shown in fig. 2, the semiconductor structure 100 includes a pair of first wells 101 on a buried layer 201, according to some embodiments of the invention. In some embodiments, the pair of first wells 101 has a second conductivity type, such as n-type, and the dopant is nitrogen, phosphorus, arsenic, antimony ions, or a combination thereof, with a doping concentration of about 10¹⁵/cm³To about 10¹⁶/cm³The range of (1). In some embodiments, the pair of first wells 101 may be formed by an ion implantation process or a diffusion process. In some embodiments, the first conductive type region 202 is included between the first well 101 and the buried layer 201, and the first conductive type region 202 may have the same doping and concentration as the semiconductor substrate 200, and thus, the description thereof is omitted. In other embodiments, the first well 101 may directly contact the buried layer 201.

As shown in fig. 2, the semiconductor structure 100 includes a second well 102 located on a buried layer 201 and between the pair of first wells 101, according to some embodiments of the present invention. In some embodiments, the second well 102 has a first conductivity type, e.g., may be p-type, with dopants such as boron, aluminum, gallium, indium, boron trifluoride ions (BF)₃ ⁺) Or combinations thereof, with a doping concentration of about 10¹⁵/cm³To about 10¹⁶/cm³The range of (1). In some embodiments, the second well 102 may be formed by an ion implantation process or a diffusion process. In a top view, such as depicted in fig. 1, in some embodiments, the width W1 of the second well 102 along the second direction does not exceed 2 micrometers (um), such as may be 2 micrometers (um) or 1 micrometer (um).

As shown in fig. 2, the semiconductor structure 100 includes a pair of third wells 105 on a buried layer 201, disposed outside and surrounding the pair of first wells 101 (shown in fig. 1), according to some embodiments of the present invention. In some embodiments, the pair of third wells 105 have the first conductivity type and may have the same doping and concentration as the second well 102, and thus are not described herein again. In some embodiments, a heavily doped region 210 having the same conductivity type as the third well 105 may be formed near the upper surface of the semiconductor substrate 200, and the heavily doped region 210 may be electrically connected to an electrode (not shown) through an interconnection structure (not shown).

In fig. 2, an isolation structure 209 is formed between the first well 101 and the third well 105, and the isolation structure 209 is formed near the top surface of the semiconductor substrate 200 according to some embodiments of the present invention, in some embodiments, the isolation structure 209 may be made of silicon oxide and is a local oxidation of silicon (L OCOS) isolation structure 209 formed by thermal oxidation, in other embodiments, the isolation structure 209 may be a Shallow Trench Isolation (STI) structure formed by an etching and deposition process.

As shown in fig. 2, the semiconductor structure 100 includes a bulk doped region 103 located in the second well 102, according to some embodiments of the present invention. In some embodiments, the bulk doped region 103 has a first conductivity type, for example, may be p-type with dopants such as boron, aluminum, gallium, indium, boron trifluoride ion (BF)₃ ⁺) Or combinations thereof, with a doping concentration of about 10¹⁷/cm³To about 10¹⁸/cm³The range of (1). In some embodiments, the depth H1 of the bulk doped region 103 is in a range of about 0.5 micrometers (um) to about 1 micrometer (um), for example, may be 0.6 micrometers (um). In some embodiments, the body doped region 103 may be formed by an ion implantation process or a diffusion process.

As shown in fig. 2, the semiconductor structure 100 includes a first heavily doped region 104 located in a body doped region 103, according to some embodiments of the present invention. In some embodiments, the first heavily doped region 104 has a first conductivity type, for example, p-type, with dopants such as boron, gallium, aluminum, indium, boron trifluoride ion (BF)₃ ⁺) Or combinations thereof, with a doping concentration of about 10¹⁸/cm³To about 10¹⁹/cm³The range of (1). In some embodiments, the depth H2 of the first heavily doped region 104 is less than about 0.5 micrometers (um), for example, may be 0.2 micrometers (um). In some embodiments, the first heavily doped region 104 may be formed by an ion implantation process or a diffusion process.

Next, referring to fig. 2 and fig. 3, the configuration of the body doped region 103 and the first heavily doped region 104 is clearly illustrated. Referring to fig. 3, which is a cross-sectional view taken along line a2-a2 of fig. 1, the semiconductor structure 100 includes a semiconductor substrate 200, a buried layer 201, a second well 102, a body doped region 103, and a first heavily doped region 104 according to some embodiments of the present invention. It can be seen that, in some embodiments, although only the portion of the first heavily doped region 104 beyond the second well 102 along the first direction is depicted in fig. 1, the portion beyond the second well 102 includes both the first heavily doped region 104 and the body doped region 103 under the first heavily doped region 104. The configuration of the body doped region 103 and the first heavily doped region 104 provided by the embodiment of the invention can be used as a protection structure under the condition that the distance between the first wells 101 is small (for example, less than 2 micrometers (um)), so that the leakage current between the wells can be effectively improved.

As shown in fig. 2, according to some embodiments of the present invention, the semiconductor structure 100 further comprises source/drain regions 203 respectively located in the pair of first wells 101, wherein the source/drain regions 203 are formed near the upper surface of the semiconductor substrate 200. In some embodiments, the source/drain regions 203 are of a second conductivity type, e.g., n-type. The source/drain regions 203 may be electrically connected to the source/drain electrodes S/D by an interconnect structure (not shown).

In some embodiments, the source region (drain region) is a first drift distance W2 from the interface between the pair of first wells 101 and the second well 102, and the drain region (source region) is a second drift distance W3 from the interface between the pair of first wells 101 and the second well 102, wherein neither the first drift distance W2 nor the second drift distance W3 exceeds 2 μm. In some embodiments, the first drift distance W2 is the same as the second drift distance W3, so the pair of first wells 101 may be symmetrical to the first heavily doped region 104. In other embodiments, the first drift distance W2 is different from the second drift distance W3, and thus is asymmetric to the first well 101 in the first heavily doped region 104. In this case, the pair of first wells 101 have different drift distances (i.e., the pair of first wells 101 have different areas), so that the pair of first wells 101 can bear different voltages, for example, the voltage borne by one of the first wells 101 having the smaller drift distance is smaller than the voltage borne by the other first well 101 having the larger drift distance. In some embodiments of the present invention, the area size of the active region (e.g., the active region 108) of the semiconductor structure 100 may be reduced by adjusting the respective drift distance size of the pair of first wells 101 according to the requirements of the application potential.

As shown in fig. 2, according to some embodiments of the present invention, the semiconductor structure 100 further includes a pair of second heavily doped regions 204 located in the second well 102, wherein the first heavily doped region 104 is located between the pair of second heavily doped regions 204. In some embodiments, the pair of second heavily doped regions 204 has a second conductivity type, such as n-type, and the dopant thereof is, for example, nitrogen, phosphorus, arsenic, antimony ions, or a combination thereof. In some embodiments, the pair of second heavily doped regions 204 may be formed by an ion implantation process or a diffusion process. In some embodiments, the first heavily doped region 104 and the second heavily doped region 204 are connected through a surface conductor, and the first heavily doped region 104 and the second heavily doped region 204 can float (floating), so that the conduction current flows through the surface conductor without flowing through an additional interconnect structure, thereby achieving the effects of reducing the routing resistance and improving the conduction uniformity. In other embodiments, the first heavily doped region 104 and the second heavily doped region 204 may be electrically connected to electrodes (not shown) through an interconnect structure (not shown).

As shown in fig. 2, the semiconductor structure 100 further includes a pair of gate structures 220 disposed above the pair of first wells 101 and the second well 102, and partially covering the pair of second heavily doped regions 204 according to some embodiments of the present invention. In some embodiments, the pair of gate structures 220 may include a gate dielectric layer 205, a gate electrode layer 206 on the gate dielectric layer 205, an insulating layer 207, a metal layer 208, and a gate spacer 221, respectively. Gate spacer 221 is located on opposite sides of stacked gate dielectric layer 205 and gate electrode layer 206, insulating layer 207 partially covers first well 101 and extends over a portion of the top surface of gate spacer 221 and gate electrode layer 206, and metal layer 208 covers insulating layer 207 on a portion of the top surface of gate electrode layer 206 and extends onto insulating layer 207 on a portion of the top surface of first well 101. In some embodiments, the gate electrode layer 206 and the metal layer 208 may be electrically connected to the gate electrodes G1 and G2 by an interconnect structure. In some embodiments, a metal layer 208 electrically connected to the gate electrode layer 206 extends onto the insulating layer 207 on a portion of the top surface of the first well 101, which may create the effect of a lateral field plate.

In some embodiments, the material of the gate dielectric layer 205 may comprise silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, a combination thereof, or other suitable dielectric materials, in some embodiments, the gate dielectric layer 205 may be formed by thermal oxidation (thermal oxidation), Chemical Vapor Deposition (CVD), or atomic layer deposition (A L D).

The material of the gate electrode layer 206 may comprise a metal silicide, amorphous silicon, polysilicon, one or more metals, a metal nitride, a conductive metal oxide, a combination of the foregoing, or other suitable conductive materials. The conductive material layer may be formed by Chemical Vapor Deposition (CVD), sputtering, resistive heating evaporation, e-beam evaporation, or other suitable deposition methods.

The insulating layer 207 may be made of silicon nitride, silicon oxynitride, silicon carbide, silicon oxide, silicon carbonitride, other suitable materials, or combinations thereof, hi some embodiments, the insulating layer 207 may be formed by a deposition process including Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), atomic layer deposition (a L D), High Density Plasma Chemical Vapor Deposition (HDPCVD), other suitable methods, or combinations thereof.

The metal layer 208 may be formed by a deposition process, and the material thereof may include a conductive material, such as aluminum, copper, tungsten, titanium, tantalum, titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), a metal oxide, a metal alloy, other suitable conductive materials, or a combination thereof.

Please refer to fig. 1 and fig. 4. FIG. 4 is a cross-sectional view of a line A3-A3 corresponding to the semiconductor structure shown in FIG. 1, in accordance with another embodiment of the present invention. According to other embodiments of the present invention, the semiconductor structure 100 includes a pair of fourth wells 106 on the buried layer 201, disposed outside and surrounding the pair of third wells 105 (as shown in fig. 1). In some embodiments, the pair of fourth wells 106 has the second conductivity type and may have the same doping and concentration as the first well 101, and thus, the description thereof is omitted here. In some embodiments, a heavily doped region 211 having the same conductivity type as the fourth well 106 may be formed near the upper surface of the semiconductor substrate 200, and the heavily doped region 211 may be electrically connected to the electrode E1 through an interconnection structure (not shown).

According to other embodiments of the present invention, the semiconductor structure 100 includes a pair of fifth wells 107 disposed on the epitaxial layer 413, and disposed outside and surrounding the pair of fourth wells 106 (as shown in fig. 1). In some embodiments, epitaxial layer 413 can be an epitaxial layer of the first conductivity type. In some embodiments, the pair of fifth wells 107 have the first conductivity type and may have the same doping and concentration as the second well 102 and the third well 105, and thus, the description thereof is omitted. In some embodiments, a heavily doped region 212 having the same conductivity type as the fifth well 107 may be formed near the upper surface of the semiconductor substrate 200, and the heavily doped region 212 may be electrically connected to the electrode E2 through an interconnection structure (not shown).

In fig. 4, an isolation structure 209 is formed between the third well 105, the fourth well 106, and the fifth well 107, the isolation structure 209 being formed near the upper surface of the semiconductor substrate 200 according to some embodiments of the present invention. The materials and the formation method of the isolation structure 209 shown here are substantially the same as those of the isolation structure 209 shown in fig. 2, and thus are not described again here.

FIG. 5 illustrates a partial top view of an exemplary semiconductor structure, in accordance with further embodiments of the present invention. The semiconductor structure 500 illustrated in fig. 5 is substantially the same as the semiconductor structure 100 illustrated in fig. 1, except that the end of the first heavily doped region 104 illustrated in fig. 5 is T-shaped, and the end of the first heavily doped region 104 illustrated in fig. 1 is I-shaped. FIG. 6 is a partial top view illustrating an exemplary semiconductor structure, in accordance with yet other embodiments of the present invention. The semiconductor structure 600 illustrated in fig. 6 is substantially the same as the semiconductor structure 100 illustrated in fig. 1, except that the semiconductor structure 600 in fig. 6 further includes at least one pair of additional first heavily doped regions 604 surrounding the pair of first wells 101. For example, the first heavily doped region 604 may also surround the pair of first wells 101 (not shown) along the boundary of the active region 108. The pair of additional first heavily doped regions 604 may or may not be connected to the first heavily doped region 104, respectively. In some embodiments, when the pair of additional first heavily doped regions 604 is connected to the first heavily doped region 104, although fig. 6 only illustrates the pair of additional first heavily doped regions 604 around the first well 101, the pair of additional first heavily doped regions 604 may also include doped regions such as the body doped region 103. In some embodiments, the additional first heavily doped region 604 and the first heavily doped region 104 may be connected by, for example, contacts or metal (not shown). According to some embodiments of the present invention, the shape of the first heavily doped region 104 and/or the additional first heavily doped region 604 included in the exemplary semiconductor structures 100, 500, and 600 illustrated in fig. 1 and 5-6, respectively, may depend on circuit layout, process conditions, and design rules, and the shape of the first heavily doped region 104 is not limited to the shape disclosed in the embodiments of the present invention.

According to fig. 1 to 6, embodiments of the present invention provide a semiconductor structure 100, 500, 600 including a body doped region 103 and a first heavily doped region 104 between a plurality of first wells 101 and extending along a first direction. With such a configuration of the doped region and the well, the conduction uniformity of the semiconductor structure can be improved, the leakage current between the wells can be improved, and the resistance and the wiring area of the active region (e.g., the active region 108) can be reduced.

Referring to fig. 7 in conjunction with fig. 8-9, another aspect of a semiconductor structure 700 is illustrated. The active region 710 of the semiconductor structure 700 of fig. 7 may be understood as a structure formed by connecting a pair of active regions 108 of the semiconductor structure 100 of fig. 2 back to back (e.g., "drain-source" - "source-drain", or "source-drain" - "drain-source"), according to some embodiments of the present invention. It is to be noted that, for the sake of clarity and understanding of the embodiments, the active region 710 of the semiconductor structure 700 shown in fig. 7 only includes one pair of the active regions 108 of the semiconductor structure 100 shown in fig. 2, but the present invention is not limited thereto, and in other words, the active region 710 of the semiconductor structure 700 may also include two or more pairs of the active regions 108 of the semiconductor structure 100.

Fig. 7 is a partial top view of an exemplary semiconductor structure 700, fig. 8 is a cross-sectional view taken along line B1-B1 of fig. 1, and fig. 9 is a cross-sectional view taken along line B2-B2 of fig. 1, in accordance with some embodiments of the present invention. It should be understood that, for simplicity and clarity in describing embodiments of the present invention, not all of the elements of the semiconductor structure 700 are illustrated in fig. 7-9, nor are all of the elements in the cross-sectional views illustrated in fig. 8 and 9 illustrated in fig. 7.

As shown in fig. 7, a partial top view of an exemplary semiconductor structure 700 is provided in accordance with some embodiments of the present invention. According to some embodiments of the present invention, the semiconductor structure 700 comprises a pair of first wells 701, a pair of second wells 702 between the pair of first wells 701, a pair of body-doped regions 703 and a pair of first heavily-doped regions 704 respectively located within the pair of second wells 702, a third well 705 between the pair of second wells 702, and a second heavily-doped region 706 in the third well 705, wherein the end shapes of the pair of first heavily-doped regions 704 are I-type.

In the top view, the pair of first heavily doped regions 704 and the pair of first wells 701 both extend along the first direction according to some embodiments of the present invention, wherein the pair of first heavily doped regions 704 extend along the first direction beyond two opposite edges of the pair of first wells 701, in some embodiments, the pair of second wells 702 have a first length L extending along the first direction, and the pair of first wells 701 have a second length L extending along the first direction, wherein the first length L1 is less than the second length L. in the top view, in some embodiments according to the present invention, the distance that the pair of first heavily doped regions 704 exceeds the first edge of the pair of second wells 702 along the first direction is a first distance D1, the distance that the pair of first wells 701 exceeds the first edge of the pair of second wells 702 along the first direction is a second distance D2, wherein the first distance D1 is greater than the second distance D2., and it is noted that the relationship between the first length D1 and the second length 4831, the second length 462 is not repeated as shown in the first and the second distance in the same numerical values as the first distance and second distance in the second length 465, L, 3872.

According to some embodiments of the present invention, the semiconductor structure 700 includes a body-doped region 703 and a first heavily doped region 704 located between a pair of first wells 701 and extending along a specific direction, and a protection structure formed by the configuration of the body-doped region 703 and the first heavily doped region 704 can reduce or prevent leakage current between the pair of first wells 701. In some embodiments, when the distance between the pair of first wells 701 (e.g., the width W1 in fig. 7) is less than 2 micrometers (um), the configuration of the body-doped region 703 and the first heavily doped region 704 may be utilized to avoid generating leakage current. It should be understood that not all elements of the semiconductor structure 700 are shown in fig. 7 for the sake of brevity and to highlight features thereof.

As shown in fig. 7, in the semiconductor structure 700, the pair of first wells 701 is surrounded by the fourth well 707, the fourth well 707 is surrounded by the fifth well 708, and the fifth well 708 is surrounded by the sixth well 709, according to some embodiments of the present invention. In some embodiments, the pair of first, third, and fifth wells 701, 705, and 708 have a second conductivity type, and the second, fourth, and sixth wells 702, 707, and 709 have a first conductivity type opposite the second conductivity type. In some embodiments, the first conductivity type is p-type, for example, and the second conductivity type is n-type, for example, but the invention is not limited thereto.

As shown in fig. 8, and in conjunction with the top view shown in fig. 7, according to some embodiments of the present invention, a semiconductor structure 700 mainly includes a semiconductor substrate 800 having a first conductivity type, a buried layer 801 having a second conductivity type on the semiconductor substrate 800, a pair of first wells 701 on the buried layer 801, a pair of second wells 702 on the buried layer 801 and between the pair of first wells 701, a pair of body-doped regions 703 respectively in the pair of second wells 702, a pair of first heavily-doped regions 704 respectively in the pair of body-doped regions 703, and a third well 705 on the buried layer 801 and between the pair of second wells 702. In some embodiments, the pair of first wells 701 and the pair of third wells 705 have the same second conductivity type as the buried layer 801, and the pair of second wells 702, the pair of body doped regions 703, and the pair of first heavily doped regions 704 have the same first conductivity type as the semiconductor substrate 800. In some embodiments, the first conductivity type is, for example, p-type, and the second conductivity type opposite the first conductivity type is n-type. In some embodiments, the pair of second wells 702 has a first doping concentration, the pair of body doped regions 703 has a second doping concentration, and the pair of first heavily doped regions 704 has a third doping concentration, wherein the third doping concentration is greater than the second doping concentration, and the second doping concentration is greater than the first doping concentration.

As shown in fig. 8, in some embodiments, the semiconductor substrate 800 may be a silicon substrate, but the embodiments of the invention are not limited thereto. For example, the material, conductivity type, and doping concentration of the semiconductor substrate 800 are substantially the same as those of the semiconductor substrate 200 shown in fig. 2, and thus are not described herein again.

As shown in fig. 8, a semiconductor structure 700 includes a buried layer 801 on a semiconductor substrate 800, according to some embodiments of the invention. In some embodiments, the material, thickness, conductivity type, and doping concentration of the buried layer 801 are substantially the same as those of the buried layer 201 illustrated in fig. 2, and thus are not described herein again.

As shown in fig. 8, a semiconductor structure 700 includes a pair of first wells 701 on a buried layer 801, according to some embodiments of the invention. In some embodiments, the material, conductivity type, and doping concentration of the pair of first wells 701 are substantially the same as those of the first well 101 illustrated in fig. 2, and thus are not repeated herein. In some embodiments, the pair of first wells 701 may directly contact the buried layer 801. In other embodiments, the pair of first wells 701 and the buried layer 801 include the first conductive type region 802 therebetween, and the first conductive type region 202 may have the same doping and concentration as the semiconductor substrate 800, and thus, the description thereof is omitted.

As shown in fig. 8, a semiconductor structure 700 includes a pair of second wells 702 located on a buried layer 801 and between the pair of first wells 701, according to some embodiments of the invention. In some embodiments, the material, conductivity type, and doping concentration of the pair of second wells 702 are substantially the same as those of the second well 102 illustrated in fig. 2, and thus are not repeated herein. In a top view, such as depicted in fig. 7, in some embodiments, the width W1 of the pair of second wells 702 along the second direction does not exceed 2 microns (um), such as may be 2 microns (um) or 1 micron (um).

As shown in fig. 8, a semiconductor structure 700 includes a pair of fourth wells 707 on a buried layer 801 disposed outside and surrounding the pair of first wells 701 according to some embodiments of the present invention (as shown in fig. 7). In some embodiments, the pair of fourth wells 707 has the first conductivity type and may have the same doping and concentration as the pair of second wells 702, and thus, will not be described herein again. In some embodiments, a heavily doped region 810 having the same conductivity type as the fourth well 707 may be formed near the upper surface of the semiconductor substrate 800, and the heavily doped region 810 may be electrically connected to an electrode (not shown) through an interconnection structure (not shown).

In fig. 8, an isolation structure 809 is formed between the first well 701 and the fourth well 707, the isolation structure 809 being formed near the upper surface of the semiconductor substrate 800 according to some embodiments of the present invention, in some embodiments, the isolation structure 809 may be made of silicon oxide and is a silicon partial oxidation (L OCOS) isolation structure 809 formed by thermal oxidation, in other embodiments, the isolation structure 809 may be a Shallow Trench Isolation (STI) structure formed by an etching and deposition process.

As shown in fig. 8, the semiconductor structure 700 includes a pair of body-doped regions 703 respectively located in the pair of second wells 702 according to some embodiments of the present invention. In some embodiments, the material, conductivity type, and doping concentration of the body-doped region 703 are substantially the same as those of the body-doped region 103 illustrated in fig. 2, and thus are not repeated herein. In some embodiments, the depth H1 of the pair of body-doped regions 703 is in a range of about 0.5 micrometers (um) to about 1 micrometer (um). In some embodiments, the pair of body doped regions 703 may be formed by an ion implantation process or a diffusion process.

As shown in fig. 8, the semiconductor structure 700 includes a pair of first heavily doped regions 704 respectively located in the pair of body doped regions 703, according to some embodiments of the present invention. In some embodiments, the material, conductivity type, and doping concentration of the pair of first heavily doped regions 704 are substantially the same as those of the first heavily doped region 104 illustrated in fig. 2, and thus are not repeated herein. In some embodiments, the depth H2 of the pair of first heavily doped regions 704 is less than about 0.5 micrometers (um), such as may be 0.2 micrometers (um). In some embodiments, the pair of first heavily doped regions 704 may be formed by an ion implantation process or a diffusion process.

To more specifically describe the configuration of the pair of body-doped regions 703 and the pair of first heavily-doped regions 704, fig. 7 and 3 can be used together. In fig. 7, although only a portion of the pair of first heavily doped regions 704 extending beyond the pair of second wells 702 along the first direction is shown in fig. 7, the portion extending beyond the pair of second wells 702 includes both the first heavily doped regions 704 and the body doped regions 703 under the first heavily doped regions 704 (as shown in fig. 3, and thus is not described herein again). The configuration of the body doped region 703 and the first heavily doped region 704 provided by the embodiment of the present invention can be used as a protection structure under the condition that the distance between the first wells 101 is small (for example, smaller than 2 micrometers (um)), so as to effectively improve the leakage current between the wells.

As shown in fig. 8, a semiconductor structure 700 includes a third well 705 on a buried layer 801, wherein the third well 705 is located between the pair of second wells 702, according to some embodiments of the invention. In some embodiments, the third well 705 has the second conductivity type and may have the same doping and concentration as the pair of first wells 701, and thus, the description thereof is omitted here. In some embodiments, a second heavily doped region 706 having the same conductivity type as the third well 705 may be formed adjacent to the upper surface of the semiconductor substrate 800. In some embodiments, the second heavily doped region 706 may be electrically connected to the source/drain electrode S/D by an interconnect structure (not shown).

As shown in fig. 8, the semiconductor structure 700 further comprises source/drain regions 803 respectively located in the pair of first wells 701, wherein the source/drain regions 803 are formed near the upper surface of the semiconductor substrate 800, according to some embodiments of the present invention. In some embodiments, the source/drain regions 803 have a second conductivity type, e.g., n-type. The source/drain regions 803 may be electrically connected to the source/drain electrodes S/D by an interconnect structure (not shown).

In some embodiments, the source region (drain region) is a first drift distance W2 from the interface between the pair of first and second wells 701 and 702, and the second heavily doped region 706 is a second drift distance W3 from the interface between the third and second wells 705 and 702, wherein neither the first drift distance W2 nor the second drift distance W3 exceeds 2 microns. In some embodiments, the first drift distance W2 is different from the second drift distance W3, so that the first well 701 and the third well 705 have different drift distances (i.e., the first well 701 and the third well 705 have different areas), so that the first well 701 and the third well 705 can bear different voltages, respectively, for example, the voltage borne by one of the first wells 701 comprising the smaller drift distance is also smaller than the voltage borne by the third well 705 comprising the larger drift distance. In some embodiments of the present invention, the area size of the active region (e.g., the active region 710) of the semiconductor structure 700 may be reduced by adjusting the respective drift distances of the pair of the first well 701 and the third well 705 according to the requirements of the application potential.

As shown in fig. 8, the pair of second wells 702 included in the semiconductor structure 700 further respectively include a pair of third heavily doped regions 804, wherein one of the pair of first heavily doped regions 704 is located between the pair of third heavily doped regions 804 according to some embodiments of the present invention. In some embodiments, the pair of third heavily doped regions 804 has a second conductivity type, such as n-type, and the dopant thereof is, for example, nitrogen, phosphorus, arsenic, antimony ions, or a combination thereof. In some embodiments, the pair of third heavily doped regions 804 may be formed by an ion implantation process or a diffusion process. In some embodiments, the first heavily doped region 704 and the third heavily doped region 804 may float (floating), and the conduction current flows through the surface conductor without flowing through an additional interconnect structure, thereby achieving the effects of reducing the routing resistance and improving the conduction uniformity. In other embodiments, the first heavily doped region 704 and the third heavily doped region 804 may be electrically connected to electrodes (not shown) through an interconnection structure (not shown).

As shown in fig. 8, the semiconductor structure 700 further includes a plurality of pairs of gate structures 820 disposed over the first and second wells 701, 702 and the second and third wells 702, 705, partially covering the pair of third heavily doped regions 804, according to some embodiments of the present invention. In some embodiments, the plurality of pairs of gate structures 820 may include a gate dielectric layer 805, a gate electrode layer 806 on the gate dielectric layer 805, an insulating layer 807, a metal layer 808, and a gate spacer 821, respectively. Gate spacer 821 is on opposite sides of the stacked gate dielectric layer 805 and gate electrode layer 806, insulating layer 807 partially covers first well 701 and extends over a portion of the top surface of gate spacer 821 and gate electrode layer 806, and metal layer 808 covers insulating layer 807 over a portion of the top surface of gate electrode layer 806 and extends over insulating layer 807 over a portion of the top surface of first well 701. In some embodiments, the gate electrode layer 806 and the metal layer 808 may be electrically connected to the gate electrodes G1 and G2 by an interconnect structure. In some embodiments, a metal layer 808 electrically connected to the gate electrode layer 806 extends onto the insulating layer 807 on a portion of the top surface of the first well 701, which may create the effect of a lateral field plate (lateral field plate). In some embodiments, the material and the forming method of the gate structure 820 are substantially the same as those of the gate structure 220 illustrated in fig. 2, and thus are not repeated herein.

Please refer to fig. 7 and 9. FIG. 9 is a cross-sectional view of the semiconductor structure shown in FIG. 7 according to another embodiment of the present invention. According to other embodiments of the present invention, the semiconductor structure 700 includes a pair of fifth wells 708 on the buried layer 801, disposed outside and surrounding the pair of fourth wells 707 (as shown in FIG. 7). In some embodiments, the pair of fifth wells 708 has the second conductivity type and may have the same doping and concentration as the first well 701 and the third well 705, and thus, the description thereof is omitted. In some embodiments, a heavily doped region 811 having the same conductivity type as the fifth well 708 may be formed near the upper surface of the semiconductor substrate 800, and the heavily doped region 811 may be electrically connected to the electrode E1 (not shown) through an interconnection structure (not shown).

According to other embodiments of the present invention, the semiconductor structure 700 includes a pair of sixth wells 709 disposed on the epitaxial layer 913, outside and surrounding the pair of fifth wells 708 (as shown in fig. 7). In some embodiments, the epitaxial layer 913 may be an epitaxial layer of the first conductivity type. In some embodiments, the pair of sixth wells 709 has the first conductivity type and may have the same doping and concentration as the second well 702 and the fourth well 707, and thus, the description thereof is omitted here. In some embodiments, a heavily doped region 812 having the same conductivity type as the sixth well 709 may be formed near the upper surface of the semiconductor substrate 800, and the heavily doped region 812 may be electrically connected to the electrode E2 (not shown) through an interconnection structure (not shown).

In fig. 9, isolation structures 809 are formed between the fourth well 707, the fifth well 708, and the sixth well 709, the isolation structures 809 being formed proximate to the upper surface of the semiconductor substrate 800, according to some embodiments of the invention. The material and the forming method of the isolation structure 809 illustrated herein are substantially the same as those of the isolation structure 809 illustrated in fig. 8, and thus are not described herein again.

Fig. 10 illustrates a partial top view of an exemplary semiconductor structure 1000, and fig. 11 is a cross-sectional view taken along line C-C of fig. 10, in accordance with some embodiments of the present invention. It should be understood that, for simplicity and clarity in describing embodiments of the present invention, not all of the elements of the semiconductor structure 1000 are illustrated in fig. 10-11, nor are all of the elements in the cross-sectional view illustrated in fig. 11 illustrated in fig. 10.

According to some embodiments of the present invention, the semiconductor structure 1000 shown in fig. 10 is different from the semiconductor structure 700 shown in fig. 7 in that the semiconductor structure 1000 further includes a pair of additional second wells 702 respectively disposed outside the pair of first wells 701, and a pair of body-doped regions 703 and a pair of first heavily-doped regions 704 respectively located in the pair of second wells 702.

As shown in fig. 11 in combination with the top view shown in fig. 10, according to some embodiments of the present invention, the cross-section of the semiconductor structure 1000 shown in fig. 11 is different from the cross-section of the semiconductor structure 700 shown in fig. 8 in that the semiconductor structure 1000 further includes a pair of additional second wells 702 respectively disposed between the pair of first wells 701 and the pair of fourth wells 707 and on the buried layer 801, and a pair of bulk-doped regions 703 respectively disposed in the pair of second wells 702, and a pair of first heavily-doped regions 704 and a third heavily-doped region 804 respectively disposed in the pair of bulk-doped regions 703. In some embodiments, the materials, conductivity types, and doping concentrations of the additional second well 702, the body doped region 703, the first heavily doped region 704, and the third heavily doped region 804 are substantially the same as those of the structure illustrated in fig. 8, and thus are not repeated herein.

FIG. 12 illustrates a partial top view of an exemplary semiconductor structure, in accordance with further embodiments of the present invention. The semiconductor structure 1200 shown in fig. 12 is substantially the same as the semiconductor structure 700 shown in fig. 7, except that the end of the first heavily doped region 704 shown in fig. 12 is T-shaped, and the end of the first heavily doped region 704 shown in fig. 7 is I-shaped. The semiconductor structures 1300 and 1400 illustrated in fig. 13-14 are substantially the same as the semiconductor structure 700 illustrated in fig. 7, except that the semiconductor structures 1300 and 1400 illustrated in fig. 13-14 further include at least one pair of additional first heavily doped regions 1104 and 1204 surrounding the pair of first wells 701. As shown in fig. 13, in some embodiments, the additional first heavily doped region 1104 and the first heavily doped region 704 may be connected by, for example, a contact or a metal (not shown). As shown in fig. 14, the pair of additional first heavily doped regions 1204 may or may not be connected with the first heavily doped region 704, respectively. In some embodiments, when the pair of additional first heavily doped regions 1104 and 1204 are respectively connected to the first heavily doped region 704, although fig. 13-14 only illustrate the pair of additional first heavily doped regions 1104 and 1204 around the first well 701, the pair of additional first heavily doped regions 1104 and 1204 may also include doped regions such as the body doped region 703 underneath. According to some embodiments of the present invention, the shape of the first heavily doped region 704 and/or the additional first heavily doped regions 1104, 1204 included in the exemplary semiconductor structures 700, 1200, 1300, 1400 illustrated in fig. 7 and 12-14, respectively, may depend on circuit layout, process conditions, and design rules, and the shape of the first heavily doped region 704 is not limited to the shape disclosed in the embodiments of the present invention.

Referring to fig. 7-14, the semiconductor structures 700, 1000, 1200, 1300, and 1400 according to the embodiments of the present invention include a pair of body doped regions 703 and a pair of first heavily doped regions 704 between a plurality of first wells 701 and extending along a first direction, and by using the configuration of the body doped regions and the wells, the conduction uniformity of the semiconductor structure can be improved, the leakage current between the wells can be improved, and the resistance and the wiring area of the active region (e.g., the active region 710) can be reduced.

Embodiments of the semiconductor structure provided herein may be understood as a bi-directionally conducting semiconductor structure comprising one or more floating body double gate metal oxide semiconductor field effect transistors (FBDG MOSFETs) connected back-to-back. The semiconductor structure provided by the embodiment of the invention can be applied to a battery separation type switch (such as a lithium ion battery separation type switch). In some embodiments, the number of back-to-back connected floating body double gate metal oxide semiconductor field effect transistors (FBDG MOSFETs) included in the semiconductor structure depends on the driving capability required for the battery-operated split switch. According to the embodiment of the invention, the semiconductor structure comprises a pair of body doping regions and a pair of first heavily doped regions which are arranged among the plurality of first wells and extend along a specific direction, and the configuration of the doping regions and the wells can effectively improve the conduction uniformity of the semiconductor structure, improve the leakage current among the wells and reduce the resistance and the wiring area of the active region.

The foregoing outlines several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.