阅读说明：本技术 存储单元结构及存储器阵列结构、电压偏置方法 (Memory cell structure, memory array structure and voltage bias method ) 是由 吕杭炳 杨建国 许晓欣 刘明 于 2020-04-14 设计创作，主要内容包括：本发明公开了一种存储单元结构及存储器阵列结构、电压偏置方法,其中,存储单元结构包括：衬底层、阱层和晶体管,衬底层用于支撑存储单元结构；阱层嵌设于衬底层上,阱层的上表面与衬底层的上表面持平,晶体管设置于阱层上。本发明通过对存储单元结构进行了深阱偏置,使得存储单元的阱电压可以单独偏置为特定的电压,结合重新设计的存储单元阵列结构,将施加的编程电压大部分落在存储单元结构上,实现了对存储单元的编程电压的降低,同时可以避免选通晶体管因承受过大电压而被击穿,从而确保器件更好的可靠性以及存储单元阵列结构的面积效率更高。(The invention discloses a memory cell structure, a memory array structure and a voltage bias method, wherein the memory cell structure comprises: the device comprises a substrate layer, a well layer and a transistor, wherein the substrate layer is used for supporting a storage unit structure; the well layer is embedded on the substrate layer, the upper surface of the well layer is flush with the upper surface of the substrate layer, and the transistor is arranged on the well layer. The invention carries out deep well bias on the memory cell structure, so that the well voltage of the memory cell can be independently biased to a specific voltage, and the applied programming voltage mostly falls on the memory cell structure by combining the redesigned memory cell array structure, thereby realizing the reduction of the programming voltage of the memory cell, and simultaneously avoiding the breakdown of a gating transistor due to the bearing of overlarge voltage, thereby ensuring better reliability of a device and higher area efficiency of the memory cell array structure.)

1. A memory cell structure, comprising:

a substrate layer for providing support for the memory cell structure;

the well layer is embedded in the substrate layer, and the upper surface of the well layer is flush with the upper surface of the substrate layer; and

and the transistor is arranged inside and on the surface of the well layer.

2. The memory cell structure of claim 1, wherein the well layer comprises:

the first well layer is embedded in the substrate layer, and the upper surface of the first well layer is flush with the upper surface of the substrate layer;

the second well layer is arranged between the first well layer and the substrate layer, the upper surface of the second well layer is flush with the upper surface of the substrate layer, and the second well layer is used for spacing the first well layer and the substrate layer;

wherein the transistor is disposed inside and on a surface of the first well layer.

3. The memory cell structure of claim 2,

the substrate layer is a non-P type or N type doped structural layer;

the first well layer is a P-type doped structure layer and is used for forming a P-type well layer;

the second well layer is an N-type doped structure layer and is used for forming an N-type well layer and used as isolation between the substrate layer and the P-type well layer.

4. The memory cell structure of claim 2, wherein the transistor comprises:

the grid is arranged on the upper surface of the first well layer;

the source electrode is embedded in the first well layer, and the upper surface of the source electrode is exposed to the first well layer;

and the drain electrode is embedded in the first well layer, and the upper surface of the drain electrode is exposed to the first well layer.

5. The memory cell structure of claim 4,

the drain electrode and the source electrode are spaced at a certain distance;

the gate is disposed on an upper surface of the first well layer between the drain and the source.

6. The memory cell structure of claim 5, further comprising:

the first resistance change unit is positioned above the drain electrode or the source electrode;

the first interconnection layer comprises a plurality of interconnection sublayers, the first resistance change unit is in contact with the upper surface of the drain electrode or the source electrode, and the interconnection sublayers are positioned above the first resistance change unit;

and the first connecting wire is arranged along the arrangement direction of the first interconnection layer and the first resistance change unit and is used for connecting the first interconnection layer and the first resistance change unit with the source electrode or the drain electrode.

7. The memory cell structure of claim 5, further comprising:

the second resistance change unit is positioned above the drain electrode or the source electrode;

the second interconnection layer comprises a plurality of interconnection sublayers, at least one interconnection sublayer of the plurality of interconnection sublayers is positioned between the second resistance change unit and the drain electrode or the source electrode, and the rest interconnection sublayers are positioned above the second resistance change unit;

and the second connecting line is arranged along the arrangement direction of the second interconnection layer and the second resistance change unit and is used for connecting the second resistance change unit and the second interconnection layer with the source electrode or the drain electrode.

8. The memory cell structure of claim 2, further comprising:

the first well electrode is embedded in the first well layer, and the upper surface of the first well electrode is exposed out of the first well layer;

and the second well electrode is embedded in the second well layer, and the upper surface of the second well electrode is exposed to the second well layer.

9. A memory array structure, comprising:

a plurality of memory cell array groups arranged in parallel with each other in a first direction, each memory cell array group including a plurality of memory cell arrays arranged in parallel with each other in a second direction; each memory cell array comprising a plurality of the memory cell structures of any one of claims 1-8;

a plurality of bit lines arranged in parallel with each other along a first direction, at least two bit lines respectively connected to both ends of the plurality of memory cell arrays along a second direction; and

and the word lines are arranged in parallel along a first direction and are parallel to the bit lines, and each word line is connected with the grid electrode of the storage unit structure at the corresponding position in the storage unit arrays along a second direction.

10. The memory array structure of claim 9,

the first direction is perpendicular to the second direction.

11. The memory array structure of claim 9, wherein the memory cell array comprises at least:

a first memory cell structure having a drain connected to a bit line;

the drain end of the second storage unit structure is connected with the other bit line, and the source electrode of the second storage unit structure is connected with the source electrode of the first storage unit structure to form a common end;

the drain end further comprises a resistance change unit connected with the drain electrode of the first storage unit structure or the second storage unit structure.

12. The memory array structure of claim 11, further comprising:

a plurality of source lines arranged in parallel with each other along the second direction, each source line being connected to a common terminal in the corresponding memory cell array along the first direction;

wherein the source line is perpendicular to both the bit line and the word line.

13. A voltage bias method applied to the memory array structure of any one of claims 9-12, wherein the voltage bias method comprises:

applying a bias voltage to the first well layer of the determined memory cell structure in the memory array structure;

applying a source terminal voltage to a source line corresponding to a common terminal of the memory cell structure, and simultaneously applying a drain terminal voltage to a bit line corresponding to a drain terminal of the memory cell structure;

the bias voltage value is a negative value smaller than zero, and the source end voltage and the drain end voltage value are larger than or equal to the bias voltage value.

Technical Field

The invention relates to the technical field of memories, in particular to a memory cell structure, a memory array structure and a voltage bias method.

Background

With the development of semiconductor manufacturing process, the conventional embedded memory (mainly flash memory) faces technical bottlenecks of sharply increased process complexity, increased cost, decreased performance and the like below a 28nm process node, so that a novel embedded memory technology is urgently needed. In the prior art, a novel embedded memory includes a Resistive Random Access Memory (RRAM), a phase change memory (PCRAM), a Magnetic Random Access Memory (MRAM), etc., which has the advantages of compatibility with a CMOS process, high scalability, low cost, etc., and has been widely researched and paid attention in recent years.

In the prior art, due to the limitation of process and material, the programming voltage of the novel embedded memory is lower than that of the traditional embedded memory, but still cannot be reduced to the level of the core voltage of the CMOS transistor of the advanced process node (28nm and below). In the embedded application field, the novel memory mostly adopts a structure of 1T1R, that is, one gating transistor is matched with one memory cell, if the programming voltage of the memory cell cannot be reduced, a gating tube with a high withstand voltage value is needed, which undoubtedly increases the area of the memory cell, leads to the increase of the cost, and has low area efficiency of the array structure.

Disclosure of Invention

Technical problem to be solved

The invention provides a storage unit structure, a storage array structure and a voltage bias method, and aims to solve the technical problems that under the condition of controlling the area size and the cost of a storage under the condition of an existing advanced process node, the programming voltage of a novel embedded storage cannot be effectively reduced, and the reliability and the area efficiency of the novel embedded storage are poor.

(II) technical scheme

One aspect of the present invention discloses a memory cell structure, which includes: the memory cell structure comprises a substrate layer, a well layer and a transistor, wherein the substrate layer is used for providing support for the memory cell structure; the well layer is embedded in the substrate layer, the upper surface of the well layer is flush with the upper surface of the substrate layer, and the transistor is arranged inside and on the surface of the well layer.

According to an embodiment of the present invention, wherein the well layer includes: the first well layer is embedded in the substrate layer, and the upper surface of the first well layer is flush with the upper surface of the substrate layer; the second well layer is arranged between the first well layer and the substrate layer, and the upper surface of the second well layer is flush with the upper surface of the substrate layer and used for spacing the first well layer and the substrate layer; the transistor is arranged in the first well layer and on the surface of the first well layer.

According to an embodiment of the invention, wherein the substrate layer is a non-P-type or N-type doped structural layer; the first well layer is a P-type doped structure layer and is used for forming a P-type well layer; the second well layer is an N-type doped structure layer and is used for forming an N-type well layer to serve as isolation between the substrate layer and the P-type well layer.

According to an embodiment of the present invention, wherein the transistor includes: the grid electrode is arranged on the upper surface of the first well layer; the source electrode is embedded in the first well layer, and the upper surface of the source electrode is exposed in the first well layer; the drain electrode is embedded in the first well layer, and the upper surface of the drain electrode is exposed to the first well layer.

According to the embodiment of the invention, the drain electrode and the source electrode are separated by a certain distance; the gate is arranged on the upper surface of the first well layer between the drain and the source.

According to an embodiment of the present invention, wherein the memory cell structure further comprises: the first resistance change unit is positioned above the drain electrode or the source electrode; the first interconnection layer comprises a plurality of interconnection sublayers, the first resistance change unit is in contact with the upper surface of the drain electrode or the source electrode, and the plurality of interconnection sublayers are positioned above the first resistance change unit; the first connecting line is arranged along the arrangement direction of the first interconnection layer and the first resistance change unit and is used for connecting the first interconnection layer and the first resistance change unit with the source electrode or the drain electrode.

According to an embodiment of the present invention, wherein the memory cell structure further comprises: the second resistance change unit is positioned above the drain electrode or the source electrode; the second interconnection layer comprises a plurality of interconnection sublayers, at least one interconnection sublayer of the plurality of interconnection sublayers is positioned between the second resistance change unit and the drain electrode or the source electrode, and the rest interconnection sublayers are positioned above the second resistance change unit; the second connecting line is arranged along the arrangement direction of the second interconnection layer and the second resistance change unit and is used for connecting the second resistance change unit and the second interconnection layer with the source electrode or the drain electrode. According to an embodiment of the present invention, wherein the memory cell structure further comprises: the first well electrode is embedded in the first well layer, and the upper surface of the first well electrode is exposed in the first well layer; the second well electrode is embedded in the second well layer, and the upper surface of the second well electrode is exposed on the second well layer.

Another aspect of the invention discloses a memory array structure, comprising: a plurality of memory cell array groups, a plurality of bit lines, and a plurality of word lines, the plurality of memory cell array groups being arranged in parallel with each other in a first direction, each memory cell array group comprising: a plurality of memory cell arrays arranged in parallel with each other along a second direction, the memory cell arrays including a plurality of the above-described memory cell structures; the bit lines are arranged in parallel along a first direction, and at least two bit lines are respectively connected with two ends of the memory cell arrays along a second direction; and a plurality of word lines arranged in parallel with each other along a first direction and parallel with the plurality of bit lines, each word line connecting gates of the memory cell structures at corresponding positions in the plurality of memory cell arrays along a second direction.

According to an embodiment of the invention, wherein the first direction is perpendicular to the second direction.

According to an embodiment of the present invention, wherein the memory cell array comprises at least: the memory comprises a first memory cell structure and a second memory cell structure, wherein the drain terminal of the first memory cell structure is connected with a bit line; the drain end of the second storage unit structure is connected with the other bit line, and the source electrode of the second storage unit structure is connected with the source electrode of the first storage unit structure to form a common end; the drain end further comprises a resistance change unit connected with the drain electrode of the first storage unit structure or the second storage unit structure.

According to the embodiment of the invention, the method further comprises the following steps: a plurality of source lines arranged in parallel with each other along the second direction, each source line being connected to a common terminal in the corresponding memory cell array along the first direction; the source line is perpendicular to the bit line and the word line.

In another aspect of the present invention, a voltage bias method is applied to the above memory array structure, wherein the voltage bias method includes: applying a bias voltage to a first well layer of a memory cell structure in the determined memory array structure; applying a source terminal voltage to a source line corresponding to a common terminal of the memory cell structure, and simultaneously applying a drain terminal voltage to a bit line corresponding to a drain terminal of the memory cell structure; the bias voltage value is a negative value less than zero, and the source terminal voltage and the drain terminal voltage value are values greater than or equal to the bias voltage value.

(III) advantageous effects

The invention discloses a memory cell structure and a memory array structure, wherein the memory cell structure comprises: the device comprises a substrate layer, a well layer and a transistor, wherein the substrate layer is used for supporting a storage unit structure; the well layer is embedded on the substrate layer, the upper surface of the well layer is flush with the upper surface of the substrate layer, and the transistor is arranged on the well layer. The invention carries out deep well bias on the memory cell structure, so that the well voltage of the memory cell can be independently biased to a specific voltage, and the applied programming voltage mostly falls on the memory cell structure by combining the redesigned memory cell array structure, thereby realizing the reduction of the programming voltage of the memory cell, and simultaneously avoiding the breakdown of a gating transistor due to the bearing of overlarge voltage, thereby ensuring better reliability of a device and higher area efficiency of the memory cell array structure.

Drawings

FIG. 1A is a schematic cross-sectional view of a memory cell structure according to an embodiment of the present invention;

FIG. 1B is a schematic cross-sectional view of a memory cell structure according to another embodiment of the present invention;

FIG. 2 is a schematic diagram of an equivalent circuit corresponding to the memory cell structure shown in FIG. 1A or FIG. 1B according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a prior art memory cell array structure;

FIG. 4 is a schematic diagram of the structure of a memory cell array according to an embodiment of the present invention;

FIG. 5 is a schematic voltage bias diagram corresponding to the memory cell array structure shown in FIG. 4 according to an embodiment of the present invention;

FIG. 6 is a flowchart illustrating a method for biasing a memory cell array structure according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.

The invention provides a storage unit structure, a storage array structure and a voltage bias method, and aims to solve the technical problem that under the condition of controlling the area size and the cost of a storage under the existing advanced process node, the programming voltage of a novel embedded storage cannot be effectively reduced, and the reliability of the novel embedded storage structure is poor.

To clearly illustrate the technical solution of the present invention, the memory of the present invention may be a novel embedded memory, such as a Resistive Random Access Memory (RRAM), and further may be a resistive random access memory having a basic structural unit of 1T 1R. However, those skilled in the art will appreciate that it is not intended to limit the scope of the claims of the present invention.

Programming of a new embedded memory may include various operations, for example, programming of a Resistive Random Access Memory (RRAM) is largely classified into three types: initialization (formulation), set (set), set (reset) operations.

In the timing of the resistive operation, the resistive switching element CE LL is programmed from an initial super-high resistance state (M Ω or more) to a relatively low resistance state (about several hundred K Ω), in which case a large programming voltage is applied to the drain terminal corresponding to the bit line B L, a gate voltage VG is applied to the gate terminal corresponding to the word line W L to turn on the gate transistor (i.e., a gate transistor), and the source terminal corresponding to the source line S L is at a low level.

When set operation is performed, a source end is connected with a high level, a drain end is connected with a low level, although the voltage required by the set operation is less than the voltage required by the forming operation, because the resistance of the resistance change unit CE LL is small, and the substrate bias effect exists in the gate tube, the voltage applied to the source end is large, and if a reasonable voltage bias mode is not adopted, the voltage applied to the transistor can exceed the maximum limit value thereof, so that the gate transistor is easy to break down, and the reliability problem is caused.

In reset operation, the set voltage is applied to the drain terminal, the source terminal is connected to the low level, and since the memory cell is in the low resistance state, a large portion of the voltage will still fall on the gate line, and thus the gate line will face the same reliability problem.

One aspect of the present invention discloses a memory cell structure, wherein as shown in fig. 1A and 1B, the memory cell structure comprises: a substrate layer 100, a well layer 200 and a transistor, the substrate layer 100 being used to provide support for the memory cell structure.

The well layer 200 is embedded in the substrate layer 100, the upper surface of the well layer 200 is flush with the upper surface of the substrate layer 100, the substrate layer 100 is provided with a groove which is recessed downwards from the upper surface of the substrate layer, and the well layer 200 can be formed in the groove through a chemical vapor deposition process.

The transistors are arranged in and on the surface of the well layer 200, and can be gate tubes, and are used for controlling data reading and writing and signal output in the memory cells, isolating interference of adjacent memory cells better, and being more compatible with a CMOS (complementary metal oxide semiconductor) process.

According to an embodiment of the present invention, wherein as shown in fig. 1A and 1B, the well layer 200 includes: the first well layer 210 is embedded in the substrate layer 100, and the upper surface of the first well layer 210 is flush with the upper surface of the substrate layer 100, so as to form a transistor structure, wherein the transistor is arranged in the first well layer and on the surface of the first well layer. The second well layer 220 is disposed between the first well layer 210 and the substrate layer 100, and an upper surface of the second well layer 220 is flush with an upper surface of the substrate layer 100, and is used for spacing the first well layer 210 and the substrate layer 100.

In other words, the second well layer 220 is formed on the inner surface of the groove of the substrate layer 100, and specifically, the second well layer 220 may be formed on the inner surface of the groove by a chemical vapor deposition process, and directly contact with the inner surface of the groove. The first well layer 210 is formed on the second well layer 220, i.e., the outer surface of the second well layer 220 comes into contact with the inner surface of the first well layer 210 (i.e., the side surface and the lower surface except the upper surface of the first well layer 210). Therefore, the second well layer 220 may form an isolation layer between the first well layer 210 and the substrate layer 100, preventing the first well layer 210 from contacting the substrate layer.

Further, the substrate layer 100 may be a non-P-type or N-type doped structural layer, and the first well layer 210 may be a P-type doped structural layer for forming a P-type well layer and forming a transistor accordingly; the second well layer 220 may be an N-type doped structural layer for forming an N-type well layer for forming isolation between the substrate layer 100 and the P-type well layer. Therefore, it constitutes the deep well bias structure of the present invention, the first well layer 210 as the P-type well layer can be biased to a negative voltage VB, the second well layer 220 as the N-type well layer can be biased to a power supply voltage VCC, and the substrate layer 100 can be biased to a ground voltage Vsub, as shown in fig. 2, so that the problem of PN forward conduction does not occur when the drain and source terminals are applied with a negative voltage.

Therefore, the invention adopts the deep well biasing technology, selects the deep well process transistor, biases the well potential in a negative voltage state, and can connect a negative voltage at the source end or the drain end of the transistor, thereby reducing the voltage value applied at the drain end or the source end, only ensuring that the voltage difference falling on the memory cell meets the requirement, simultaneously ensuring that the voltage difference at different ends of the transistor does not exceed the breakdown voltage of the transistor, and preventing the reliability problem caused by the breakdown of the resistance change unit CE LL of the transistor.

According to an embodiment of the present invention, wherein as shown in fig. 1A, 1B and 2, the transistor includes a gate 310, a source 320 and a drain 330, the gate 310 is disposed on an upper surface of the first well layer 210, and is used to form a corresponding gate terminal in connection with the word line W L and apply a gate voltage VG to turn on the transistor, as shown in fig. 2.

The source electrode 320 is embedded in the first well layer 210, and the upper surface of the source electrode 320 is exposed to the first well layer 210, and the upper surface of the source electrode 320 may be flush with the upper surface of the first well layer 210, and is used for connecting with the source line S L to form a corresponding source terminal and applying a source terminal voltage VS, as shown in fig. 2.

The drain 330 is embedded in the first well layer 210, and the upper surface of the drain 330 is exposed to the first well layer 210, and the upper surface of the drain 330 may be flush with the upper surface of the first well layer 210, and is used to connect with the bit line B L to form a corresponding drain, and to apply a drain voltage VD, as shown in fig. 2.

Wherein the gate 310, the source 320, the drain 330 and the first well layer 210 form a transistor of the memory cell structure. Note that there may be a plurality of transistors provided in the first well layer 210, and a transistor array is formed on the first well layer 210. Specifically, a gate may be correspondingly disposed on the upper surface of the first well layer 210 on the other side of the source 320, and the gate and the transistor structure share the source 320. Accordingly, other gates may be disposed on the upper surface of the first well layer 210 to form a plurality of transistor structures that can be turned on, so as to ensure that the size and area of the memory cell structure are smaller and the transistor integration is higher.

According to an embodiment of the present invention, as shown in fig. 1A, 1B and 2, the drain 330 is spaced apart from the source 320 by a certain distance to prevent short circuit of the contact of the structure; the gate 310 is disposed on the upper surface of the first well layer 210 between the drain 330 and the source 320. In other words, the first well layer 210 is spaced by a certain thickness between the drain electrode 330 and the source electrode 320, the gate electrode 310 is correspondingly disposed on the upper surface of the portion of the first well layer 210, one end of the gate electrode 310 corresponds to the drain electrode 330, and the other end corresponds to the source electrode 320, as shown in fig. 1A and 1B.

According to the embodiment of the invention, as shown in fig. 1A, the memory cell structure further includes a first resistance change unit CE LL 1, a first interconnection layer 340 and a first connection line L1, the first resistance change unit CE LL 1 is located above the drain 330 or the source 320, the first interconnection layer 340 includes a plurality of interconnection sublayers, the first resistance change unit CE LL 1 is in contact with the upper surface of the drain 330 or the source 320, the plurality of interconnection sublayers are located above the first resistance change unit CE LL 1, and the first connection line L1 is arranged along the arrangement direction of the first interconnection layer 340 and the first resistance change unit CE LL 1 and is used for connecting the first interconnection layer 340 and the first resistance change unit CE LL 1 with the source 320 or the drain 330.

Specifically, the first interconnection layer 340 may include a plurality of interconnection sublayers, each of which may be a metal layer and is used for electrical connection between the constituent structures of the memory cell structure, for example, the interconnection sublayers may form a bit line, a word line, a source line, or the like, the first resistive switching cell CE LL is in contact with the upper surface of the drain 330 or the source 320, and may be understood as being directly connected to the drain 330 or the source 320, and the two are not connected to each other through a structure other than the first connection line L, and therefore, the first interconnection layer 340 needs to be disposed above the first resistive switching cell CE LL, as shown in fig. 1A, the plurality of interconnection sublayers at least include a first interconnection sublayer 341, a second interconnection sublayer, and a third interconnection sublayer 342, which are sequentially disposed from bottom to top, wherein the first resistive switching cell CE LL is disposed below the first interconnection sublayer 341 and is connected to the drain 330, and the first connection line L sequentially connects the first resistive switching cell CE 4831, the first interconnection sublayer 341, the second interconnection sublayer, the third interconnection sublayer 341, the third interconnection sublayer and the resistive switching cell CE 861, and the interconnection sublayer may also form a resistive switching cell structure 3663.

According to another embodiment of the invention, as shown in fig. 1B, the memory cell structure further includes a second resistance change unit CE LL 2, a second interconnection layer 350 and a second connection line L2, the second resistance change unit CE LL 2 is located above the drain 330 or the source 320, the second interconnection layer 350 includes a plurality of interconnection sublayers, at least one of the interconnection sublayers is located between the second resistance change unit CE LL 2 and the drain 330 or the source 320, the remaining interconnection sublayers are located above the second resistance change unit CE LL 2, and the second connection line L2 is arranged along the arrangement direction of the second interconnection layer 350 and the second resistance change unit CE LL 2 and is used for connecting the second resistance change unit CE LL 2, the second interconnection layer 350 and the source 320 or the drain 330.

As shown in fig. 1B, the plurality of interconnection sublayers at least include a first interconnection sublayer 351, a second interconnection sublayer 352, a third interconnection sublayer 353, and a fourth interconnection sublayer 354 which are sequentially disposed from bottom to top at intervals, wherein at least the first interconnection sublayer 351 and the second interconnection sublayer 352 are disposed between the second resistive switching unit CE 36 and the drain 330 or the source 320, the remaining interconnection sublayers include the third interconnection sublayer 353 and the fourth interconnection sublayer 354 are disposed above the second resistive switching unit CE LL, that is, the second resistive switching unit CE LL disposed below the third interconnection sublayer 353 and above the second interconnection sublayer 352 is not directly connected to the drain 330, in addition, the second connection line L sequentially connects the second interconnection 351, the second interconnection 352, the second resistive switching unit CE 6757, and the fourth interconnection sublayer 353 from the vertical direction, so that the resistive switching unit T1 of the present invention can be formed by the interconnection sublayers.

In addition, the resistance change unit CE LL can meet the design requirements of different memory cell structures, the preparation requirements of different preparation processes, and the design of different positions of the source electrode or the drain electrode, and is beneficial to the preparation of a memory cell structure device with a 1T1R type structure.

In the embodiment of the present invention, the terms "first" and "second" are only used as limiting words to make the schemes more clear, and are not used to refer to memory cell structures in which the two are different, for example, the first resistive switching unit CE LL 1 and the second resistive switching unit CE LL 2 may be resistive switching units of the same type, or resistive switching units of different types, and the types of the resistive switching units are determined by different constituent structures (for example, transistor designs) of the corresponding memory cell structures.

According to an embodiment of the present invention, as shown in fig. 1A, 1B and 2, the memory cell structure further includes: the first well electrode 410 is embedded in the first well layer 210, an upper surface of the first well electrode 410 is exposed to the first well layer 210, and an upper surface of the first well electrode 410 may be flush with an upper surface of the first well layer 210. The first well electrode 410 is spaced apart from the transistor structure, and the upper surface of the first well electrode 410 is also flush with the upper surface of the substrate layer 100.

The second well electrode 420 is embedded in the second well layer 220, the upper surface of the second well electrode 420 is exposed to the second well layer 220, and the upper surface of the second well electrode 420 may be flush with the upper surface of the second well layer 220 and flush with the upper surface of the substrate layer 100.

Therefore, the present invention adopts a deep well bias process, as shown in fig. 1A, fig. 1B and fig. 2, a transistor (e.g., an NMOS transistor) is formed inside and on the surface of the first well layer 210 of the deep well structure, so that a separate bias voltage can be applied to the first well layer 210, i.e., a negative voltage VB is applied, so that a negative voltage can be applied to the drain terminal or the source terminal, and the PN forward conduction problem does not occur in the case where the negative voltage VB is more negative than the negative voltage applied to the drain terminal or the source terminal. Specifically, referring to fig. 1A, 1B and 2, according to the three basic operation methods of the above memory cell structure: initialization (initializing), set (set), and set (reset) operations, the present invention is further described as follows:

the Forming operation process is that the Forming operation direction is from a drain end to a source end, as shown in fig. 1A, fig. 1B and fig. 2, the first well layer 210 is biased to a negative voltage, namely, a negative voltage VB, and the source end is biased to a negative voltage VS, in order to prevent PN forward conduction of the substrate layer 100 and the source end, it is required to ensure that the negative voltage VB and the negative voltage VS are more negative relative to the latter, at this time, the voltage applied to the drain end is VD, and the voltage falling on the resistive switching unit CE LL is VD-VS.

As shown in fig. 1A, 1B and 2, the first well layer 210 is biased to a negative voltage, i.e., a negative voltage VB, and the drain terminal is biased to a negative voltage VD, at this time, in order to prevent the substrate layer 100 and the drain terminal from being turned on in the PN forward direction, it is required to ensure that the voltage VB and the voltage VD are more negative relative to the latter, at this time, the voltage applied by the source terminal is VS, the voltage VD falling on the resistive switching unit CE LL is VG-Vth, and Vth is the threshold voltage of the resistive switching unit CE LL.

Reset operation procedure: since the reset operation and the forming operation are in the same direction and the required voltage is the same, the reset operation method may be the same as the forming, and is not described herein.

It should be further noted that, based on a conventional memory structure, such as the NOR-NOR memory structure shown in fig. 3, a word line wl and a source line sl of a memory cell array are generally parallel and perpendicular to a bit line bl, however, when the memory cell structure therein adopts the memory cell structure of the deep-well negative-pressure bias structure of the present invention, the array structure may have a problem that a gate line of a half-selected cell is subjected to a large voltage to cause breakdown.

As shown in fig. 3, assuming that a Forming operation or a reset operation (set operation is similar and will not be described again) is performed on the memory cell structure 301 in the second row and the second column (i.e., the selected cell 301 is not illustrated), at this time, because the source terminal of the corresponding source line sl1 is biased to the negative voltage vs1, the voltage vg1 applied to the gate terminal of the corresponding word line wl2 is larger than the source terminal negative voltage vs1 by a threshold voltage, for the unselected memory cell structures 302 and 303, for the gate terminal of the corresponding word line wl1 of the memory cell structure 303, the applied gate terminal voltage vg3 needs to turn off the resistive cell CE LL of the memory cell structure 303 in the first row, so the voltage biased by the corresponding source line sl1 can be selected to be equal to vs1, and at this time, the voltage applied to the drain terminal of the corresponding bit line bl2 is the high voltage vd, the resistive cell CE LL of the selected memory cell structure 301 is turned on, the corresponding memory cell structure 301 is turned on, and the drain terminal of the corresponding resistive cell structure is not turned on, but the drain terminal of the corresponding memory cell is smaller than the drain terminal of the corresponding drain transistor 73742, so that the selected memory cell structure 301 is not turned on.

In order to solve the reliability problem of the memory cell array structure caused by the deep well bias structure adopted in the present invention, another aspect of the present invention discloses a memory cell array structure, wherein as shown in fig. 4, the memory cell array structure comprises: the memory device includes a plurality of memory cell array groups arranged in parallel with each other in a first direction, a plurality of bit lines, and a plurality of word lines. As shown in fig. 4, the memory array structure is a partial structure of a memory array structure, and specifically, the memory array structure includes four rows and four columns of memory cells, which includes two memory cell array groups 401 and 402, and the memory cell array group 402 is arranged in parallel with respect to the memory cell array group 401 in a first direction. Wherein each memory cell array group includes: and a plurality of memory cell arrays arranged in parallel with each other along the second direction, each memory cell array including a plurality of the above-described memory cell structures. As shown in fig. 4, the memory cell array group 401 includes 4 memory cell arrays 510, 520, 530 and 540, and the memory cell arrays 510, 520, 530 and 540 are arranged in parallel with each other in the second direction to form a two-row and 4-column memory cell array structure.

As shown in fig. 4, bit lines B L and B L may exist in correspondence to the memory cell array group 401, wherein B L and B L are arranged in parallel to each other in the first direction, B L21 may be connected to the upper ends of the memory cell arrays 510, 520, 530, and 540, i.e., to the drain ends of the memory cell structures 511, 521, 531, and 541, and B L may be connected to the lower ends of the memory cell arrays 510, 520, 530, and 540, i.e., to the drain ends of the memory cell structures 512, 522, 532, and 542.

As shown in fig. 4, word lines W L and W L may be present in a group 401 corresponding to the memory cell array, where W L and W L12 are arranged in parallel with each other in the first direction, and W L is connected to the gates (i.e., gate ends) of the memory cell structures 865, 521, 541 in corresponding positions of the memory cell arrays 510, 520, 530, and 540 in the second direction, and W5832 is repeated in the second direction and connected to the gates (i.e., gate ends) of the memory cell structures 865, 522, 532, and 542 in corresponding positions of the memory cell arrays 510, 520, 530, and 540 in the embodiment of the present invention, the memory cell structure 511 of the memory cell array 510 is located in the first row of the group 401 of memory cells, and in the group 401, the memory cell structures corresponding to the memory cell structures 521 and 521 of the memory cell array 520 are located in one direction of the memory cell array 520, and the memory cell structures 5392, and the word line structures of the memory cell arrays 402 and 5394 are not described above with reference to the relationship that the word lines W633, W464, W3, and.

Therefore, in the memory array structure of the present invention, the bit lines B L1, B L2, B L3, and B L4 and the word lines W L1, W L2, W L3, and W L4 are arranged in parallel to each other in the first direction, that is, the bit lines and the word lines are arranged in parallel to each other.

According to an embodiment of the present invention, wherein the first direction is perpendicular to the second direction, as shown in fig. 4.

According to an embodiment of the present invention, as shown in fig. 4, the memory cell array at least includes: the memory comprises a first memory cell structure and a second memory cell structure, wherein the drain terminal of the first memory cell structure is connected with a bit line; the drain terminal of the second memory cell structure is connected with the other bit line, and the source terminal of the second memory cell structure is connected with the source terminal of the first memory cell structure to form a common terminal. Specifically, the memory cell array 510 may at least include a first memory cell structure 511 and a second memory cell structure 512, where "first" and "second" are only used as terms for making the scheme clearer, and are not used to indicate that the first memory cell structure 511 and the second memory cell structure 512 are different memory cell structures, in other words, the first memory cell structure 511 and the second memory cell structure 512 may be the same type of deep well offset structure, or different types of deep well offset structures, and the types of the deep well offset structures are determined by the design differences of the first well layer 210 and the second well layer 220, the transistors, and the like.

As shown in fig. 4, the drain of the first memory cell structure 511 is connected to a resistance change cell connected to a bit line B L1 to form a drain between the resistance change cell and the bit line B L1, the drain of the second memory cell structure 512 is connected to a resistance change cell connected to another bit line B L2 to form a drain between the resistance change cell and the bit line B L2, the source of the second memory cell structure 512 is connected to the source of the first memory cell structure 511 to form a common terminal a for connecting to the source line S L1 to form a common source terminal, correspondingly, the memory cell array 520 may include the first memory cell structure 521 and the second memory cell structure 522 and a common terminal B of the first memory cell structure 521 and the second memory cell structure 522, and the memory cell array 530 may include the first memory cell structure 531 and the second memory cell structure 532 c, and the memory cell array may include the common terminal 542 d and the second memory cell structure 542 d, which are not described herein.

According to an embodiment of the present invention, as shown in fig. 4, a plurality of source lines, each of which is arranged parallel to each other in a second direction, each of which is connected to a common terminal in a corresponding memory cell array in the first direction, wherein the source lines are simultaneously perpendicular to bit lines and word lines, specifically, source lines S L1, S L2, S L3 and S L4 are arranged parallel to each other in the second direction, wherein source line S L1 connects a common terminal a of memory cell array 510 and a common terminal of a corresponding memory cell array of memory cell array group 402 in the first direction, source line S L2 connects a common terminal b of memory cell array 520 and a common terminal of a corresponding memory cell array of memory cell array group 402 in the first direction, source line S L3 connects a common terminal c of memory cell array 530 and a common terminal of a corresponding memory cell array of memory cell array group 402 in the first direction, source line S L4 connects a common terminal d of memory cell array 540 and a common terminal of a corresponding memory cell array group 402 in the first direction, a word line structure is designed to be perpendicular to a bit line array and a word line structure, a word line structure and a word line structure are simultaneously perpendicular to a bit line and a word line structure, a word line structure are designed perpendicular to each other, and a word line structure is designed in a word line structure, which is designed perpendicular to a memory cell array, a word line structure is designed perpendicular to a memory cell array, a word line structure is designed perpendicular to a word line structure, a memory cell array and a word line.

To further illustrate the technical effects of the memory array structure, referring to fig. 4 and 5, another aspect of the present invention discloses a voltage bias method applied to the memory array structure, wherein, as shown in fig. 6, the voltage bias method includes:

s610: applying a bias voltage VB to a first well layer of a memory cell structure in the determined memory array structure; the memory cell structure determined in the embodiments of the present invention corresponds to the memory cell structure having the deep well bias structure described above, wherein the determination may be understood as "selecting", i.e., selecting the memory cell structure, such as the memory cell structure 522 shown in fig. 4 or 5. Further, the first well electrode 410 of the first well layer 210 is used for applying a bias voltage VB, which may be a negative voltage, for example, the bias voltage VB is-0.8V, as shown in fig. 1A, 1B, and 5. Therefore, the arrangement of the first well layer 210 is the arrangement position provided by the first well electrode 410, the bias voltage VB applied to the first well electrode 410 does not affect other memory composition structures except the selected memory cell structure, thereby further improving the pertinence and accuracy of voltage bias, and simultaneously preventing the risk of large voltage breakdown of the transistors of other memory cell structures except the selected memory cell structure.

S620, applying a source terminal voltage VS to a source line corresponding to the common terminal of the memory cell structure, and simultaneously applying a drain terminal voltage VD to a bit line corresponding to the drain terminal of the memory cell structure, as shown in fig. 1A or fig. 1B, the common terminal may be the common terminal B of the memory cell structure 522 shown in fig. 4, the source terminal voltage VS shown in fig. 5 may be applied to the source line S L2 corresponding thereto, the drain terminal may be the drain terminal of the memory cell structure 522 shown in fig. 4, and the drain terminal voltage VD shown in fig. 5 may be applied to the bit line B L2 corresponding thereto, the drain terminal voltage VD shown in fig. 5 may be applied to 1.7V.

The value of the bias voltage VB is a negative value less than zero, the values of the source terminal voltage VS and the drain terminal voltage VD are values equal to or greater than the bias voltage VB, where the voltage values are values that distinguish between positive and negative values, rather than absolute values of the positive and negative values, where a negative value may also indicate that the corresponding negative voltage is a reverse voltage, for example, the bias voltage VB-0.8V is a bias voltage whose reverse voltage is 0.8V. When the source-side voltage VS and the drain-side voltage VD are equal to or greater than the bias voltage VB, for example, when the source-side voltage VS is equal to-0.6V and the drain-side voltage VD is equal to 1.7V, the values of the source-side voltage VS and the drain-side voltage VD are both greater than the bias voltage VB, so that the voltage values on the corresponding source line and bit line are both low, that is, the voltages corresponding to the source and drain ends of unselected memory cell structures (for example, the memory cell structures 512, 532, 542 and the like shown in fig. 5) are also low, which not only ensures that the selected memory cell structure 522 does not have the forward conduction problem of the PN junction, but also prevents the transistor breakdown problem caused by the over-high voltage of the unselected or half-selected memory cell structures, and reduces the influence on other unselected memory cell structures to the minimum.

To explain the voltage bias method of the memory cell array structure more clearly, the present invention is further explained as follows:

the present invention further provides a memory array structure, as shown in fig. 4 and 5, in which a word line W L and a bit line B L are arranged in parallel and are perpendicular to a source line S L, in view of the problem of large voltage faced by unselected transistors due to the deep well negative voltage bias structure, and the memory array structure can effectively avoid the problem of high voltage experienced by CE LL of the half-selected memory cell structure.

As shown in fig. 5, when the memory cell structures in the second row and the second column are subjected to a Forming operation or a reset operation, that is, the memory cell structure 522 in fig. 4 is operated, at this time, because the bias voltage at the source end of the memory cell structure is the negative voltage VS L, the gate voltage VG applied to the gate end of the memory cell structure 521 corresponding to the word line W L2 is greater than the threshold voltage VS L, and the bias voltage of the unselected row (for example, the row corresponding to the word line W L1) is selected to be equal to VS L because the gate voltage applied to the resistive cell CE LL of the memory cell structure 521 corresponding to the first row is required to be turned off, at this time, the drain end of the bit line B L2 is the high voltage VD, the gate tube of the resistive cell CE LL of the selected memory cell structure 522 is turned on, and due to the presence of the resistive cell CE LL, a considerable voltage falls on the resistive cell CE LL, and the voltage falling on the gate tube is much smaller than VD tube, so that the source drain end and the gate end of the gate tube are relatively small.

Therefore, unlike the conventional memory array structure, the bit line B L is placed in parallel with the word line W L, and the voltage applied by the bit line B L0 is only applied to the resistive cell CE L L (corresponding to the word line W L shown in fig. 5) of the memory cell structure in the row selected by the word line W L1, that is, the resistive cell CE LL of the memory cell structures 512, 532 and 542 in fig. 4 is a half-selected cell, at this time, since the source terminal can be biased by a single voltage, as long as a relatively negative voltage is applied to the source terminal (i.e., the common terminal B shown in fig. 4) of the column (i.e., the memory cell array 520) where the resistive cell CE LL of the memory cell structure 522 needs to be operated, so as to ensure the voltage difference requirement of the resistive cell CE LL, for the cells that do not need to be programmed, that is the memory cell arrays 510, 530 and 540 where the memory cell structures 512, 532 and 542 in fig. 4 are located, a relatively negative voltage that can make the non-selected resistive cell CE LL be in the column (i.e., the source-drain voltage of the first column of the memory cell array 510, SL 5, the first row, and the high-drain voltage of the first row (the first transistor) can not be broken down, and the transistor 1 in the first row of.

In such a memory array structure, during the timing of the forwarding operation, a large voltage may be applied between the drain of the half-selected cell (i.e., the memory cell structures 512, 532, and 542 in fig. 4) and the negative voltage of the deep well bias, during the timing of the forwarding operation, the drain voltage VD of the drain is high, since the transistor is turned off, the drain voltage of the half-selected resistive cell CE LL is equal to VD. since the deep well bias structure will configure a negative voltage on the half-selected resistive cell CE LL, which will cause the drain and the PN junction of the first well layer to experience a large reverse bias voltage, but the transistor is sensitive to the large voltage, i.e., a source-drain voltage, a gate-source voltage, and a gate-drain voltage, while the reverse bias voltage of the PN junction is generally large, which will not cause the breakdown of the transistor.

Referring to fig. 4, as shown in fig. 5, in the embodiment of the present invention, a resistive memory cell structure (i.e. memory cell structure 522 in fig. 4) is subjected to a forming operation or reset operation, assuming that the required operating voltage is greater than 2.5V, it is assumed that a voltage falling on a resistive cell CE LL of the resistive memory cell structure is required to be about 2.5V to complete the forming operation, if a conventional process (non-deep well negative voltage bias) is adopted, such a large voltage is not easily transmitted into the memory cell array, and meanwhile, the design of the conventional array structure in which W L and B L0 are perpendicular to each other causes a transistor of an unselected memory cell to be broken down by a large voltage, as shown in fig. 3, a selected memory cell structure 303 and 302 above and below a selected memory cell structure 301 is a semi-selected memory cell structure, and 302, since the transistor is not opened at this time, a high voltage is completely biased on the transistor, thereby possibly causing the transistor to be broken down, while a memory cell structure employing a deep well word line structure with a high voltage applied to a transistor 522 which is not broken down, such as a well-2V structure 522, a transistor structure which is not opened, such as a well-2V structure, and a transistor structure which is capable of forming a reliable gate node 522, such a transistor 522, such as a transistor, such a transistor structure which is not opened, such as a transistor structure which is capable of breaking down when a transistor 522 is applied to be broken down, such as a transistor structure which is applied to a relatively high voltage of a relatively high voltage falling on a relatively high voltage of a transistor structure which is applied to a relatively high voltage of a transistor structure which is applied to a relatively high voltage of a transistor structure 522, such as a relatively high voltage of a relatively high voltage.

Therefore, the array structure of the memory array is more stable and reliable, the size and the area size of the memory array are well controlled, the scheme design is subversive in the field of the memory, the application and the popularization of the embedded memory reach a brand new height, and the embedded memory has high commercial value and scientific research value.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.