阅读说明：本技术 用于最大瞬时峰值功率的矢量生成 (Vector generation for maximum instantaneous peak power ) 是由 高又新 苏清 M·巴布纳 于 2021-04-19 设计创作，主要内容包括：本公开涉及用于最大瞬时峰值功率的矢量生成。公开了一种用于执行集成电路(IC)设计的操作状态分析的系统和方法。该方法包括：使用与一个或多个用户指定的约束相对应的多个矢量,来仿真IC设计的一个或多个单元从第一操作状态到第二操作状态的切换操作。该方法包括：针对一个或多个单元中的每个单元将操作状态从第一操作状态改变为第二操作状态,生成基于时间的波形；并且基于所生成的基于时间的波形,标识一个或多个操作状态改变,该改变对应于操作状态分析以及关联的时序窗口和单元信息。该方法包括：由IC设计的一个或多个单元中的每个单元验证一个或多个操作状态改变满足一个或多个用户指定的约束以用于生成分析报告。(The present disclosure relates to vector generation for maximum instantaneous peak power. A system and method for performing an operational state analysis of an Integrated Circuit (IC) design is disclosed. The method comprises the following steps: switching operation of one or more cells of the IC design from a first operating state to a second operating state is simulated using a plurality of vectors corresponding to one or more user-specified constraints. The method comprises the following steps: generating a time-based waveform for each of the one or more cells to change an operating state from a first operating state to a second operating state; and identifying one or more operating state changes based on the generated time-based waveform, the changes corresponding to the operating state analysis and associated timing windows and cell information. The method comprises the following steps: verifying, by each of the one or more units of the IC design, that the one or more operational state changes satisfy the one or more user-specified constraints for generating the analysis report.)

1. A computer-implemented method for performing an operational state analysis of an Integrated Circuit (IC) design, the method comprising:

simulating a switching operation for one or more cells of the IC design from a first operating state to a second operating state using a plurality of vectors corresponding to one or more user-specified constraints;

generating, for each of the one or more cells of the IC design, a time-based waveform that changes operating state from the first operating state to the second operating state during the switching operation;

identifying, by the each of the one or more cells of the IC design, one or more operating state changes based on the generated time-based waveform, the one or more operating state changes corresponding to the operating state analysis and associated timing windows and cell information;

verifying, by the each of the one or more cells of the IC design, that the one or more operational state changes satisfy the one or more user-specified constraints; and

generating an analysis report comprising a subset of the plurality of vectors corresponding to the one or more operational state changes verified by the each of the one or more cells of the IC design.

2. The computer-implemented method of claim 1, wherein the operational state analysis performed is a maximum simultaneous power consumption of the one or more units of the IC design.

3. The computer-implemented method of claim 1, wherein the operational state analysis performed is a maximum voltage drop of the one or more cells of the IC design.

4. The computer-implemented method of claim 1, wherein the operational state analysis performed is a timing path analysis for one or more clock paths of the IC design.

5. The computer-implemented method of claim 1, wherein verifying the one or more operational state changes comprises:

verifying, for the cell state of said each of said one or more cells of said IC design, that the cell state matches a pin condition according to said user-specified constraint; and

propagating the cell state after verification of the cell state according to the user-specified constraint.

6. The computer-implemented method of claim 5, wherein verifying the one or more operational state changes further comprises:

verifying a logical conflict during propagation of the cell state; and

excluding the cell state that caused the logical conflict during propagation of the cell state.

7. The computer-implemented method of claim 1, wherein generating the analysis report comprises: the analysis report is generated in either a value change dump VCD format or a fast signal database FSDB format.

8. The computer-implemented method of claim 1, wherein the user-specified constraints include high fan-out HFNs, reset logic, and integrated clock-gated ICG efficiencies.

9. The computer-implemented method of claim 1, wherein generating the analysis report comprises: the analysis report is generated for one clock cycle.

10. The computer-implemented method of claim 1, wherein generating the analysis report comprises: generating the analysis report for a plurality of clock cycles.

11. The computer-implemented method of claim 10, wherein one or more clock cycles of the plurality of clock cycles are discontinuous.

12. A system for performing operational state analysis of an integrated circuit IC design, comprising:

a memory configured to store operations; and

one or more processors configured to perform the operations comprising:

simulating a switching operation for one or more cells of the IC design from a first operating state to a second operating state using a plurality of vectors corresponding to one or more user-specified constraints;

generating, for each of the one or more cells of the IC design, a time-based waveform that changes operating state from the first operating state to the second operating state during the switching operation;

identifying, by the each of the one or more cells of the IC design, one or more operating state changes based on the generated time-based waveform, the one or more operating state changes corresponding to the operating state analysis and associated timing windows and cell information;

verifying, by the each of the one or more cells of the IC design, that the one or more operational state changes satisfy the one or more user-specified constraints; and

generating an analysis report comprising a subset of the plurality of vectors corresponding to the one or more operational state changes verified by the each of the one or more cells of the IC design.

13. The system of claim 12, wherein the operational state analysis performed on the IC design comprises one of: a maximum simultaneous power consumption of the one or more cells of the IC design, a maximum voltage drop of the one or more cells of the IC design, and a timing path analysis for one or more clock paths of the IC design.

14. The system of claim 12, wherein to verify the one or more operational state changes, the operations comprise:

verifying, for the cell state of said each of said one or more cells of said IC design, that the cell state matches a pin condition according to said user-specified constraint; and

propagating the cell state after verification of the cell state according to the user-specified constraint.

15. The system of claim 14, wherein to verify the one or more operational state changes, the operations further comprise:

verifying a logical conflict during propagation of the cell state; and

excluding the cell state that caused the logical conflict during propagation of the cell state.

16. The system of claim 12, wherein to generate the analysis report, the operations further comprise: the analysis report is generated in either a value change dump VCD format or a fast signal database FSDB format.

17. The system of claim 12, wherein the user-specified constraints include high fan-out HFN, reset logic, and integrated clock-gated ICG efficiency.

18. The system of claim 12, wherein to generate the analysis report, the operations comprise: generating the analysis report for one or more of a plurality of clock cycles.

19. The system of claim 18, wherein two or more clock cycles of the plurality of clock cycles are discontinuous.

20. A non-transitory tangible computer-readable device having instructions stored thereon that, when executed by at least one computing device, cause the at least one computing device to perform operations for operational state analysis of an Integrated Circuit (IC) design, the operations comprising:

simulating a switching operation for one or more cells of the IC design from a first operating state to a second operating state using a plurality of vectors corresponding to one or more user-specified constraints;

generating, for each of the one or more cells of the IC design, a time-based waveform that changes operating state from the first operating state to the second operating state during the switching operation;

identifying, by the each of the one or more cells of the IC design, one or more operating state changes based on the generated time-based waveform, the one or more operating state changes corresponding to the operating state analysis and associated timing windows and cell information;

verifying, by the each of the one or more cells of the IC design, that the one or more operational state changes satisfy the one or more user-specified constraints; and

generating an analysis report comprising a subset of the plurality of vectors corresponding to one or more operational state changes verified by the each of the one or more cells of the IC design.

Technical Field

The present disclosure relates generally to integrated circuit design analysis and verification. In particular, the present disclosure relates to power and voltage usage of integrated circuits using vectors.

Background

In Integrated Circuit (IC) design, two critical factors for power integrity are worst case power consumption analysis and voltage drop analysis. Integrated circuit designers therefore need to resort to worst-case power consumption analysis and worst-case voltage drop analysis to find any weaknesses in the IC design. However, determining the worst-case power consumption and/or worst-case voltage drop for an IC design is very difficult. One of the methods currently used to assist IC designers in identifying vulnerabilities in IC designs to find circuit vulnerabilities is to capture the true circuit behavior from a real scene simulation. The output of such simulations may include data on how the various elements of the IC design switch over billions of clock cycles. Another method currently used to assist IC designers in identifying weaknesses in IC designs is based on logic simulation. Based on a given primary input, as many input conditions as possible will be enumerated and then propagated down the IC design components. Similar to the first approach, in the logic simulation based approach, the generated data may correspond to millions of clock cycle results. In a third approach, long vectors are generated over time in millions or billions of clock cycles based on simulation data. The generated long vectors are fed into a power or voltage drop analysis tool. The third method is typically used in gate level analysis tools where switching vectors are generated based on switching activity using some algorithm, followed by local power and voltage drop analysis. In this method, a random number generator is used to determine whether a cell is switching to determine switching activity. The switching condition is a determination made at the primary input or output of the register, followed by a downward logic propagation. Finally, almost all cell states can be determined. The same process may be repeated for multiple clock cycles with different random seeds. Performing power and/or voltage drop analysis using the current methods mentioned above is very expensive in terms of time and money.

Disclosure of Invention

In one embodiment, a method is disclosed. The method is performed by one or more processors. The method comprises the following steps: switching operation from a first operating state to a second operating state for one or more cells of an IC design is simulated using a plurality of vectors corresponding to one or more user-specified constraints. The method comprises the following steps: a time-based waveform is generated for each of one or more cells of an IC design to change an operating state from a first operating state to a second operating state during a switching operation. The method comprises the following steps: based on the generated time-based waveform, one or more operating state changes are identified by each of one or more cells of the IC design, the one or more operating state changes corresponding to the operating state analysis and associated timing windows and cell information. The method comprises the following steps: verifying, by each of the one or more cells of the IC design, that the one or more operational state changes satisfy the one or more user-specified constraints; and generating an analysis report that includes a subset of the plurality of vectors corresponding to the one or more operating state changes verified by each of the one or more cells of the IC design.

In another embodiment, a system for performing an operational state analysis of an Integrated Circuit (IC) design is disclosed. The system comprises: a memory configured to store operations; one or more processors configured to perform the operations comprising: switching operation from a first operating state to a second operating state for one or more cells of the IC design is simulated using a plurality of vectors corresponding to one or more user-specified constraints. The operation includes: a time-based waveform is generated for each of one or more cells of an IC design to change an operating state from a first operating state to a second operating state during a switching operation. The operation comprises the following steps: based on the generated time-based waveform, one or more operating state changes are identified by each of one or more cells of the IC design, the changes corresponding to the operating state analysis and associated timing windows and cell information. The operation comprises the following steps: verifying, by each of the one or more cells of the IC design, that the one or more operational state changes satisfy the one or more user-specified constraints; and generating an analysis report that includes a subset of the plurality of vectors corresponding to the one or more operating state changes verified by each of the one or more cells of the IC design.

In yet another embodiment, a non-transitory tangible computer-readable device having instructions stored thereon is disclosed. The instructions, when executed by at least one computing device, cause the at least one computing device to perform operations for operational state analysis of an Integrated Circuit (IC) design. The operation comprises the following steps: switching operation from a first operating state to a second operating state for one or more cells of the IC design is simulated using a plurality of vectors corresponding to one or more user-specified constraints. The operation includes: a time-based waveform is generated for each of one or more cells of an IC design to change an operating state from a first operating state to a second operating state during a switching operation. The operation comprises the following steps: based on the generated time-based waveform, one or more operating state changes are identified by each of one or more cells of the IC design, the changes corresponding to the operating state analysis and associated timing windows and cell information. The operation comprises the following steps: verifying, by each of the one or more cells of the IC design, that the one or more operational state changes satisfy the one or more user-specified constraints; and generating an analysis report that includes a subset of the plurality of vectors corresponding to the one or more operating state changes verified by each of the one or more cells of the IC design.

Drawings

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of embodiments of the disclosure. The drawings are used to provide a knowledge and understanding of the embodiments of the present disclosure, and do not limit the scope of the present disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

FIG. 1 illustrates a high-level flow diagram for vector generation for power or voltage drop analysis, according to some embodiments.

Fig. 2 illustrates a flow diagram of an embodiment of the flow diagram of fig. 1, in accordance with some embodiments.

Fig. 3 illustrates a flow diagram of another embodiment of the flow diagram of fig. 1, in accordance with some embodiments.

Fig. 4 illustrates a simulation of an Integrated Circuit (IC) design using compliant (compliant) vectors, in accordance with some embodiments.

FIG. 5 illustrates time-based power consumption waveforms for a plurality of cells on an IC design, in accordance with some embodiments.

FIG. 6 illustrates peak power consumption over time calculated according to some embodiments.

FIG. 7 illustrates application of user constraints for vector generation, in accordance with some embodiments.

Fig. 8A illustrates logical correlation and event propagation for maximum instantaneous peak power determination, in accordance with some embodiments.

Fig. 8B illustrates a graph showing power consumption over time for a plurality of clock cycles, in accordance with some embodiments.

FIG. 9 illustrates activity propagation over multiple clock paths in accordance with some embodiments.

FIG. 10 illustrates a conflict resolution scheme for vector generation, according to some embodiments.

FIG. 11 illustrates maximization of clock network power, according to some embodiments.

FIG. 12 illustrates a D flip-flop with active low preset and clear in accordance with some embodiments.

Fig. 13 illustrates a process for high fan out nets (HFNs) according to some embodiments.

FIG. 14 illustrates a flow diagram of various processes used during design and manufacture of integrated circuits, in accordance with some embodiments.

FIG. 15 shows a diagram of an example computer system in which embodiments of the present disclosure may operate.

To readily identify the discussion of any particular element or act, one or more of the most significant digits in a reference number refer to the figure number in which that element is first introduced.

Detailed Description

Due to the complexity and size of Integrated Circuits (ICs), it is not possible to enumerate all possible vectors for power and voltage drop analysis that are generated using the currently known methods mentioned above in this disclosure to identify the worst case of power consumption and voltage drop analysis. However, the systems and methods described herein for generating a set of vectors for power and voltage drop analysis may be used to identify a worst-case power and voltage drop analysis.

FIG. 1 illustrates a high-level flow diagram for vector generation for power or voltage drop analysis, according to some embodiments. An integrated circuit may include a plurality of cells. Each of the plurality of cells may not switch during a clock cycle. In addition, each cell has a different cell state over time in a different clock cycle. The methods described herein may begin with all of the cells in an IC design, taking as an example maximizing instantaneous peak power and/or voltage drop. Thus, for power and voltage drop analysis, the IC design may be simulated, as shown at 110, and only vectors generated that satisfy the user-specified constraints are considered for power and voltage drop analysis. As a non-limiting example, the user-specified constraints may include information about nets with constant logical zero or one values (i.e., nets that do not switch). The user-specified constraints may also include clock definitions describing clock frequency, rising and/or falling edges of the clock. User-specified constraints may also include how often a cell switches based on clock gating. As a non-limiting example, user-specified constraints may be applied to a subset of the plurality of cells. Thus, prior to vector generation, user-specified constraints may be applied to the entire IC design, such that all elements of the IC design that are under the user-specified constraints are processed in accordance with those constraints. Thus, the circuit operation for an IC design is simulated according to user-specified constraints.

At 120, a time-based power and/or current waveform may be generated for each state change in a plurality of cells of an IC design. The time-based power and/or current waveforms may be generated based on the simulation results of 110 above. For time-based power and/or current waveforms, the consumed power and/or current flowing through each cell for each state of the cell may be determined for each timing window of the cell's clock. All the switching conditions for each cell may be enumerated by the user. A power value for each handover condition may then be calculated. Each switching condition in a cell is referred to as a cell state. The power number is then associated with the timing window from which the pin starts to rise or fall. The timing window includes minimum and maximum arrival times. Finally, each cell state is represented by a rectangular box, where the width represents the timing window and the height represents the power. The timing window represents a time interval in which a switching condition rise or fall may occur. When this occurs, the power value indicates how much power it will consume. Finally, the accumulated time-based power may be calculated from all cell states represented by the rectangular box.

At 130, based on the generated power and/or current waveforms for each state change in the plurality of cells of the IC design, a peak power and/or current usage and a corresponding timing window may be identified. Additionally, based on the generated power and/or current waveforms, one or more units contributing to peak power and/or current usage may also be determined. The peak power and/or current usage for a timing window may be determined based on the power and/or current usage for each cell during a given timing window. Thus, the cell and corresponding cell state during peak power and/or current usage may be determined. Thus, from the time-based power waveform, one or more peaks over time at which peak power consumption occurs may be calculated. For each peak and peak time, all cell states may be analyzed or scanned so that only those cell states whose timing windows overlap with the peak time are retained to form a list of cell states. The list may then be sorted by power value from highest power to lowest power.

At 140, the power and/or current usage of each cell during the timing window in which peak power and/or current usage occurs may be verified to be within user-specified constraints. If the power and/or current usage of any cell during the timing window in which the peak power and/or current usage occurs is not within user-specified constraints, the cell and corresponding cell state may also be identified for use in notifying the user. As a non-limiting example, the user may be notified using a token in a Value Change Dump (VCD) file.

According to some embodiments, a cell state for vector generation may be determined. In this step, user-specified constraints may be used for vector generation. As non-limiting examples, user-specified constraints may also include one or more nets that will never switch (so they have a constant logic zero or one value), clock definition in terms of cycles, and rising/falling edges, and how often the clock gating cell should switch. Prior to vector generation, the user-specified constraints are followed and propagated first through the entire design so that all elements that are under the user-specified constraints are processed correctly. From the list of cell states, the cell states from highest power usage to lowest power usage may also be identified. The cell state is checked against user constraints and current pin conditions propagated so far, and it is determined whether such cell state can be retained or filtered out. If the cell state is to be preserved, its pin state will propagate forward and/or backward. After propagation, if no logical conflict is found, the cell state is finally preserved. Otherwise, the cell state will be filtered out. This filtering process is repeated for each cell state in the list until no states remain.

At 150, an analysis report may be generated that includes a vector corresponding to each cell state of a plurality of cells of the IC design. Vectors corresponding to all cell states are generated. The final list of cell states will satisfy both the user-specified constraints and logical consistency. Unit states that do not satisfy user-specified constraints and/or logical consistency can be excluded from the analysis report. The analysis report may be in a VCD file format. By way of non-limiting example, the analysis report may also be generated using a Fast Signal Database (FSDB) file format. This analysis report may then be used by the IC designer to determine the maximum instantaneous peak power of the IC design. The unit states in the analysis report may be sorted by the maximum arrival time from shortest to longest. The vectors in the analysis report may be ordered in order of arrival time of the units. The arrival time of a unit may be referred to as an event time in the analysis report.

As described above, based on the high-level flow diagram shown in FIG. 1, the method begins by calculating the power of all enumerated individual cell states for each cell of the IC design. The worst power usage may also correspond to those cell states and cells enumerated, since the number of individual states from the cells is small throughout the design. Thus, the generation of vectors as described herein using fig. 1 is faster and more accurate than currently known methods for power and voltage drop analysis. The accuracy of the power and voltage drop analysis based on vectors generated using the method described herein using fig. 1 is because the disclosed method does not use random numbers to determine the vectors. Thus, power and voltage drop analysis using the method described herein using fig. 1 may be closer to the worst case than other methods using random numbers.

By comparison, currently known vector-free based solutions are based on handover activity and use a random number generator to determine whether to perform a net handover. Therefore, the nets with high handover activity are more likely to be handed over, and events for vector generation are generated. However, power and/or voltage drop analysis requires a vector that can generate worst-case power or voltage drops. Thus, whenever the net is switching at the same time, high instantaneous power or voltage drops may occur regardless of the switching activity. The methods described herein according to some embodiments do not use random numbers to determine whether to perform a network switch. Whether a cell switches depends on whether its power contributes to the total accumulated instantaneous power. Thus, the methods described herein according to some embodiments naturally follow user-specified constraints. Since all logical conflict unit states are filtered in the method, it also preserves logical consistency.

Fig. 2 illustrates a flow diagram of an embodiment of the flow diagram of fig. 1. In particular, the embodiment depicted in fig. 2 is associated with a worst case or maximum power usage analysis. As shown in FIG. 2, at 210, user-specified constraints on the logic constants of one or more nets may be mapped to one or more pin conditions of one or more cells of the IC design under test. As previously described, user-specified constraints are first considered and applied to the entire IC design during simulation. As a non-limiting example, the entire IC design may be split into two or more parts; for example, each portion may be referred to as a grid. Thus, the entire IC design may be divided into multiple grids. Thus, user-specified constraints may be applied to one or more grids of the overall IC design. At 220, as described above, user-specified constraints for one or more clock waveforms may be applied to the entire IC design and/or to one or more grids of the IC design. Rising and/or falling edges of one or more clock waveforms may cause switching of one or more cells and power consumption of one or more cells. Thus, at 230, the power consumed by one or more cells during the timing window of the applied one or more clock waveforms may be calculated. Thus, the power consumed by one or more cells for each state of the cell may be determined and associated with a timing window.

At 240, a time-based power waveform may be generated. The time-based power waveform represents the total amount of power used by one or more cells or grids of the IC design. At 250, from the time-based power waveform, a peak power and a corresponding time may also be determined. In addition, one or more units contributing to peak power may also be identified at 260. Since peak power is a result of accumulated power usage by one or more cells of the IC design, the cell state list of one or more cells contributing to peak power usage may also be determined using the time-based power waveform.

At 270, the cell state list may be checked against current pin conditions of one or more pins of one or more cells based on user-specified constraints. If a cell state from the list of cell states meets user-specified constraints, the cell state may be propagated in the forward and/or backward direction. Furthermore, if the propagation of the cell state does not cause any logical conflict, the cell state may be accepted for use in generating the vector. Otherwise, the cell state may be excluded from the generated vector.

At 280, an analysis report may be generated that includes the generated vectors corresponding to the accepted unit states. As described above, the analysis report may be in a VCD or FSDB file format.

Fig. 3 illustrates a flow diagram of another embodiment of the flow diagram of fig. 1. In particular, the embodiment depicted in FIG. 3 is associated with a worst case or maximum voltage drop analysis. As shown in FIG. 3, at 310, user-specified constraints on the logic constants of one or more nets may be mapped to one or more pin conditions of one or more cells of the IC design under test. As previously described, user-specified constraints are first considered and applied to the entire IC design during simulation. As a non-limiting example, at 330, the entire IC design may be split into two or more portions; for example, each portion may be referred to as a grid. Thus, the entire IC design may be divided into multiple grids. Thus, user-specified constraints may be applied to one or more grids of the overall IC design. Thus, as described above, when user-specified constraints for one or more clock waveforms may be applied to the entire IC design and/or to one or more grids of the IC design, rising and/or falling edges of the one or more clock waveforms may cause switching of one or more cells and cause current to flow through the one or more cells. Thus, at 340, the current flowing through one or more cells during the timing window of the applied one or more clock waveforms may be calculated. Thus, the peak current through one or more cells for each state of the cell may be determined and associated with a timing window.

At 350, a time-based current waveform may be generated for one or more grids or the entire IC design. The time-based current waveform represents the total amount of current flowing through one or more cells or grids of the IC design. From the time-based current waveform, a peak current and a corresponding time may also be determined. Further, one or more cells or grids contributing to the peak current drawn may also be identified at 350. Since the peak current is a result of the cumulative current drawn by one or more cells or grids of the IC design, the list of cell states of one or more cells contributing to the peak current may also be determined using the time-based current waveform.

At 360, the cell state list can be checked against current pin conditions of one or more pins of one or more cells based on user-specified constraints. If a cell state from the list of cell states meets user-specified constraints, the cell state may be propagated in the forward and/or backward direction. Furthermore, if the propagation of the cell state does not cause any logical conflict, the cell state may be accepted for use in generating the vector. Otherwise, the cell state may be excluded from the generated vector.

At 370, an analysis report may be generated that includes the generated vectors corresponding to the accepted unit states. As described above, the analysis report may be in a VCD or FSDB file format. Thus, the analysis report helps the IC designer identify the maximum voltage drop of the IC design and the corresponding cell states of one or more IC design cells. There may be multiple VCD or FSDB files generated, and each VCD or FSDB file may correspond to a single clock cycle.

According to some embodiments, the vector generation for maximum voltage drop analysis differs from the vector generation for maximum power usage in two ways. First, instead of calculating the power for each cell state in the design, the current waveform can be calculated for each cell state. Second, the time-based current waveform may be generated from a group of cells in the same neighborhood, rather than all IC design cells. To accomplish this, as described above, the entire IC design may be divided into multiple grids, and then the cells grouped into different grids based on their physical location on the IC. As a non-limiting example, vector generation may be performed at each grid or from multiple grids together.

According to some embodiments, as a non-limiting example, the steps described above using fig. 2 and/or fig. 3 may also be applied to generate a vector to achieve maximum voltage drop feedback on the timing path to make its delay impact the worst. In this disclosure, when generating a vector for maximum power usage, the cost function is therefore power. Similarly, when the vector is generated for the maximum voltage drop, the cost function is therefore the peak current, whereas when the vector is generated for the maximum voltage drop feedback, the cost function is the delay caused by the voltage drop. A vector for maximum voltage drop feedback may be generated along a timing path for a group of cells in the same neighborhood or vicinity on an IC.

FIG. 4 illustrates a simulation of an Integrated Circuit (IC) design using compliant vectors, in accordance with some embodiments. As described above and shown in FIG. 4, an IC design 416 described using a hardware description language (e.g., Verilog, etc.) may include a plurality of cells 412. The plurality of cells 412 may be connected via a plurality of signal paths 414. When the clock waveform is applied to one or more of the plurality of cells 412, it may cause a switching of the net of one or more of the plurality of cells 412, according to user-specified constraints. Switching of the net may cause power usage and/or current to flow through one or more cells. Further, as described above, the units may be grouped into one or more sections called grids. The cells may be grouped into grids based on their location on the IC design.

Based on cell switching, a cell may be coupled to a timing critical path, for example, in a temporal and/or spatial relationship. All cells may cause some voltage drop and their IR sensitivity may be calculated when the cells switch during rising and/or falling edges of the clock. In addition, the delay of the critical timing path may also be determined. Thus, as a non-limiting example, a switching vector may be determined in addition to the maximum power usage vector. The switching vector may describe the timing degradation for each switching event. As described above, vectors that do not meet user-specified constraints may be excluded and may not be included in the analysis report. As non-limiting examples, user-specified constraints may relate to fan-out, reset logic, Integrated Clock Gating (ICG) efficiency, scan patterns, and so forth.

FIG. 5 illustrates time-based power consumption waveforms for a plurality of cells on an IC design, in accordance with some embodiments. As described above and shown in fig. 5, timer-based power consumption waveforms 512, 514, and 516 are shown. The power consumption waveforms 512, 514, and 516 are associated with cells C1, C2, and C10, for example. For each cell C1, C2, and C10, the power consumption waveform shows the power used over time over multiple clock cycles. Power may be used by a cell when the cell state switches during the rise and/or fall of an applied clock waveform. The power used may then be represented as a rectangle, where the height of the rectangle represents the amount of power used and the width represents the timing window.

FIG. 6 illustrates peak power consumption over time calculated according to some embodiments. The time-based power waveform shown in fig. 5 for multiple cells is shown in fig. 6 along the X-axis 604 over time. Since time-based power waveforms for multiple cells are stacked on top of each other along the X-axis over time, a power consumption waveform 602 can be generated for an entire IC design and/or multiple cells, showing the total power consumed at a given time. As shown in fig. 6, the power consumption waveform 602 may thus be used to identify the peak power, the cells that contribute to the peak power, and may also identify the cell state and corresponding time when peak power usage occurs.

FIG. 7 illustrates application of user constraints for vector generation, in accordance with some embodiments. An example of a user constraint for vector generation may be an ICG efficiency of 50% or less. Without ICG efficiency constraints, all inverters can be switched in a manner that contributes to maximum instantaneous peak power usage. As shown in FIG. 7, inverters i 1708, i 2710 and i 4706 are triggered by ICG 1702, while inverters i 3712 and i 5714 are triggered by ICG 2704. Thus, inverters i 1708, i 2710, and i 4706 may cause power consumption according to rising and/or falling edges of the enable signal and clock signal CLK at ICG 1702. Similarly, inverters i 3712 and i 5714 may cause power consumption according to the enable signal and the clock signal CLK at ICG 2704. As shown in fig. 7, without the user-specified constraint describing the maximum instantaneous peak power, all inverters can switch simultaneously, resulting in a maximum simultaneous peak power, as shown at 716. As a non-limiting example, a user-specified constraint may limit the maximum simultaneous peak power usage to below 50%. The ICG 2704 trigger vector may be excluded from consideration because the ICG 2704 trigger vectors i 3712 and i 5714 consume less instantaneous peak power than the ICG 1702 trigger vectors i 1708, i 2710 and i 4706. Thus, a vector may be generated based on the simultaneous power usage of inverters i 1708, i 2710, and i 4706, as shown at 718.

Fig. 8A illustrates logical correlation and event propagation for maximum instantaneous peak power determination, in accordance with some embodiments. As a non-limiting example, the user-specified constraint may require that the input signal at inverter i1 be a rising signal. Thus, when event R802 is rising at inverter i1, the event is propagated forward to the other flip-flops. As shown in fig. 8A, some pins may have constant logic. Thus, the voltage level at those pings having constant logic may remain at 1 or 0. After event propagation, the result vector for the circuit shown in FIG. 8A may have logical dependencies for event R at inverter i1, flip-flop ff1, OR gate or1, flip-flop ff2, flip-flop ff3, XOR gate XOR1, flip-flops ff4 and ff5, and inverter i 3. Thus, vectors can be generated that satisfy logical correlations, and only those events that satisfy user-specified constraints for logical correlations can be propagated in the forward and/or reverse directions.

Fig. 8B illustrates a graph showing power consumption over time for a plurality of clock cycles, in accordance with some embodiments. As a non-limiting example, assume that all cells are clock cells and that there are no data cells in the IC design for power consumption for multiple clock cycles, as shown in fig. 8B. Assuming that cell switching occurs at the rising edge of the clock, as shown in FIG. 8B, a worst or maximum simultaneous power consumption may occur during period 1808, period 2810, and period 3812. Thus, according to user-specified constraints, only clock cycles 808, 810, and 812 may be considered for all clocks during vector generation. All other clock cycles can be ignored as they do not comply with the user specified constraints. However, when generating analysis reports for vectors for periods 808, 810, and 812, the output VCD file may appear irrelevant. As a non-limiting example, to generate an analysis report that includes a vector showing coherent logic, a dummy additional clock cycle may be generated. As a result, a single VCD or FSDB file may be generated.

FIG. 9 illustrates activity propagation over multiple clock paths in accordance with some embodiments. As a non-limiting example, the user-specified constraint may include the propagation of an event over multiple clock paths. In this case, the user-specified constraints may specify how the event propagation should be delayed. As shown in fig. 9, clock 902 is a 1GHz clock and the other clock 904 is a 500MHz clock. When an option (e.g., "set _ power _ analysis _ options-through _ mode") is enabled, then the event will propagate along multiple clock paths. Derating factors may be specified for components along the clock path to achieve maximum clock transitions at the destination.

FIG. 10 illustrates a conflict resolution scheme for vector generation, according to some embodiments. As a non-limiting example, the user-specified constraints may include one or more conditions corresponding to worst-case internal energy consumption for the multiple instances. User-specified constraints 1002 may require that propagated clock transitions and signal-to-net values be ignored as part of one or more conditions corresponding to worst-case internal energy consumption.

FIG. 11 illustrates maximization of clock network power, according to some embodiments. As non-limiting examples, the user-specified constraints may include a worst-case clock network power and a user-specified target power consumption for the IC design, one or more cells or one or more grids of the IC design. The IC design shown in FIG. 11 may include, for example, clocks CLK 1102, ICG 11104, ICG 21106, ICG 31108, and flip-flops 1110, 1112, 1114, and 1116. The cost function or parameter for the user-specified constraint may be the internal energy of the plurality of endpoints. As shown in fig. 11, an ICG feeding another ICG may be enabled with an SP value of 1.

FIG. 12 illustrates a D flip-flop with active low preset and clear in accordance with some embodiments. As a non-limiting example, user-specified constraints may include how control pins may be set to enable data to propagate output. In FIG. 12, clock pins 1204, data pins 1202 and 1206, and control pins 1208 and 1210 are shown. The control pins may be processed based on a hardware description language that specifies the presetting and clearing of the enable signals. The data pins may obtain TR and SP through user comments or rule propagation and notation. The clock pins may obtain TR and SP through node clock activity propagation.

FIG. 13 illustrates a process for a high fan-out net according to some embodiments. As a non-limiting example, the user-specified constraints may include high fan out network (HFN) processing. In IC designs, unbuffered nets may incur a significant amount of power consumption, which may mask real power issues during the Clock Tree Synthesis (CTS) or early design stages prior to buffering. User-specified constraints may define limits for HFN. For example, the HFN may be set to 10. Thus, all nets with 10 or more pins can be defined as HFNs. For the driver 1302 and receivers 1304, 1306, and 1308, the calculation of power may be based on leakage only. Slewing (slew) and load calculation for nets identified as having an HFN may be disabled according to user-specified constraints.

FIG. 14 illustrates an example set of processes 1400 used during design, verification, and manufacture of an article of manufacture, such as an integrated circuit, to transform and verify design data and instructions representing the integrated circuit. Each of these processes may be structured and enabled as a number of modules or operations. The term "EDA" refers to the term "electronic design automation". The processes begin with creating a product idea 1410 with information provided by a designer that is transformed to create an article of manufacture using a set of EDA processes 1412. After the design is complete, the design tape-out 1434, i.e., when the artwork (e.g., geometric patterns) of the integrated circuit is sent to a fabrication facility to fabricate the mask set, it is then used to fabricate the integrated circuit. After tape-out, semiconductor die 1436 is fabricated, and packaging and assembly processes 1438 are performed to produce a finished integrated circuit 1440.

The specification for a circuit or electronic structure may range from low-level transistor material layouts to high-level description languages. The high-level representation may be used to design circuits and systems using a hardware description language ('HDL') such as VHDL, Verilog, systemveilog, SystemC, MyHDL, or OpenVera. The HDL description may be converted to a logic level register transfer level ('RTL') description, a gate level description, a layout level description, or a mask level description. Each lower level representation, which is a more detailed description, adds more useful details in the design description, including, for example, more details described for the module. The representation of the lower level, which is described in more detail, may be computer generated, derived from a design library or created by another design automation process. An example of a specification language for specifying a lower level representation language for a more detailed description is SPICE, which is used to describe a circuit with many analog components in detail. The description at each representation level is enabled for use by a corresponding tool (e.g., a formal verification tool) for that layer. The design process may use the sequence depicted in fig. 14. The process is described or supported by an EDA product (or tool).

During system design 1414, the functionality of the integrated circuit to be fabricated is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and/or code lines), and cost reduction. At this stage, the design may be divided into different types of modules or components.

During logic design and functional verification 1416, modules or components in the circuit are specified in one or more description languages and the specification is checked for functional accuracy. For example, components of a circuit may be verified to generate an output that matches the specification requirements of the designed circuit or system. Functional verification may use simulators and other programs, such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, special systems, called components of "emulators" or "prototype systems", are used to accelerate functional verification.

During synthesis and design under test 1418, the HDL code is converted to a netlist. In some embodiments, the netlist may be a graph structure in which edges of the graph structure represent components of the circuit and nodes of the graph structure represent the manner of interconnection between the components. Both the HDL code and the netlist are hierarchical products of manufacture that can be used by EDA products to verify that an integrated circuit, when manufactured, performs according to a specified design. The netlist can be optimized for the target semiconductor fabrication technology. Additionally, the completed integrated circuit may be tested to verify that the integrated circuit meets the requirements of the specification.

During netlist verification 1420, the netlist is checked for compliance with timing constraints and for correspondence with HDL code. During design planning 1422, an overall floor plan of the integrated circuit is constructed and analyzed for timing and top-level routing.

During placement or physical implementation 1424, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of circuit components by multiple conductors) occurs, and cells are selected from the library so that a particular logic function can be performed. As used herein, the term "cell" may designate a set of transistors, other components, AND interconnects that provide a boolean logic function (e.g., AND, OR, NOT, XOR) OR a storage function (e.g., flip-flop OR latch). As used herein, a circuit "block" may refer to two or more units. Both units and circuit blocks may be referred to as modules or components and may be enabled as physical structures and enabled in the simulation at the same time. The selected cells are specified with parameters such as size (based on "standard cells") and made accessible in a database for use by the EDA product.

During analysis and extraction 1426, circuit functionality is verified at the layout level, which allows for improvements to the layout design. During physical verification 1428, the layout design is checked to ensure that manufacturing constraints, such as DRC constraints, electrical constraints, lithographic constraints, etc., are correct and that the circuitry functionality matches the HDL design specification. During resolution enhancement 1430, the geometry of the layout is transformed to improve the way in which the circuit design is manufactured.

During tape-out, data is created for the production of photolithographic masks (after applying photolithographic enhancements, if appropriate). During mask data preparation 1432, the "tape-out" data is used to generate the photolithographic masks used to produce the finished integrated circuit.

The storage subsystem of a computer system (such as computer system 1500 of FIG. 15) may be used to store programs and data structures used by some or all of the EDA products described herein and products used to develop cells for libraries and physical and logical designs using the libraries.

Fig. 15 illustrates an example machine of a computer system 1500 in which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or a machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while the figures illustrate a single machine, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system 1500 includes a processing device 1502, a main memory 1504 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM) such as synchronous DRAM (sdram), static memory 1506 (e.g., flash memory, Static Random Access Memory (SRAM), etc.), and a data storage device 1518, which communicate with each other via a bus 1530.

Processing device 1502 represents one or more processors, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 1002 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), network processor, or the like. The processing device 1502 may be configured to execute the instructions 1526 for performing the operations and steps described herein.

The computer system 1500 may also include a network interface device to communicate over a network 1520. Computer system 1500 can also include a video display unit 1510 (e.g., a Liquid Crystal Display (LCD) or a Cathode Ray Tube (CRT)), an alphanumeric input device 1512 (e.g., a keyboard), a cursor control device 1514 (e.g., a mouse), a graphics processing unit 1522, a signal generation device 1516 (e.g., a speaker), the graphics processing unit 1522, a video processing unit 1528, and an audio processing unit 1532.

The data storage device 1518 may include a machine-readable storage medium 1524 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 1526 or software embodying any one or more of the methodologies or functions described herein. The instructions 1526 may also reside, completely or at least partially, within the main memory 1404 and/or within the processing device 1502 during execution thereof by the computer system 1500, the main memory 1504 and the processing device 1502 also constituting machine-readable storage media.

In some implementations, the instructions 1526 include instructions to implement functionality corresponding to the present disclosure. While the machine-readable storage medium 1524 is shown in an example implementation to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and processing device 1502 to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations that lead to a desired result. The operations are those requiring physical manipulations of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the present disclosure, it is appreciated that throughout the description, certain terms refer to the operation and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, and so forth.

In the foregoing disclosure, implementations of the present disclosure have been described with reference to specific example implementations thereof. It will be evident that various modifications may be made thereto without departing from the broader scope of the disclosure as set forth in the following claims. This disclosure may refer to some elements in the singular, more than one element may be depicted in the figures, and like elements are numbered alike. The present disclosure and figures are, therefore, to be regarded as illustrative rather than restrictive.