阅读说明：本技术 数据处理方法、装置、模组及芯片 (Data processing method, device, module and chip ) 是由 蔡明飞 库仑 于 2020-05-26 设计创作，主要内容包括：本申请提供了一种数据处理方法、装置、模组及芯片。该数据处理模组包括：一AXI总线,其与存储控制器连接；一第一AHB总线,其与所述处理器连接；一AHB配置单元,其与所述第一AHB总线连接以获取所述处理器发送的第一指令；一AXI读控制单元,其与所述AXI总线连接,以用于根据所述第一指令控制所述存储控制器从外部存储器读取对应的帧配置参数；一解析单元,其与所述AXI读控制单元连接,其用于将所述帧配置参数解析成基于AHB协议的多个第一数据包；一第二AHB总线,其一端与所述解析单元连接,其另一端与所述多个功能单元连接,用于将所述多个第二数据包传输给对应的功能单元。本申请可以提高指令处理效率,降低处理器的工作压力。(The application provides a data processing method, a data processing device, a module and a chip. The data processing module includes: an AXI bus connected to the memory controller; a first AHB bus coupled to said processor; the AHB configuration unit is connected with the first AHB bus to acquire a first instruction sent by the processor; an AXI read control unit connected with the AXI bus for controlling the memory controller to read corresponding frame configuration parameters from an external memory according to the first instruction; a parsing unit connected with the AXI read control unit for parsing the frame configuration parameters into a plurality of first data packets based on an AHB protocol; and one end of the second AHB bus is connected with the analysis unit, and the other end of the second AHB bus is connected with the plurality of functional units and is used for transmitting the plurality of second data packets to the corresponding functional units. The method and the device can improve the instruction processing efficiency and reduce the working pressure of the processor.)

1. A data processing module is used in a chip, the chip further comprises a processor, a storage controller and a plurality of functional units which are respectively connected with the processor, the storage controller and an external memory, and the data processing module is characterized by comprising:

an AXI bus connected with the memory controller;

a first AHB bus coupled to said processor;

the AHB configuration unit is connected with the first AHB bus to acquire a first instruction sent by the processor;

an AXI read control unit connected with the AXI bus for controlling the memory controller to read corresponding frame configuration parameters from an external memory according to the first instruction;

a parsing unit connected with the AXI read control unit for parsing the frame configuration parameters into a plurality of first data packets based on an AHB protocol;

and one end of the second AHB bus is connected with the analysis unit, and the other end of the second AHB bus is connected with the plurality of functional units and is used for transmitting the plurality of first data packets to the corresponding functional units.

2. The data processing module of claim 1, wherein the external memory comprises a first memory area;

the AHB is used for receiving a plurality of original data packets sent by the processor, wherein the original data packets are the first instructions or second data packets used for being directly sent to corresponding functional units;

the AHB configuration unit is configured to identify an address in each original data packet, so as to screen out a first instruction therein, and send the first instruction to the AXI read control unit, where an address in the first instruction is located in an address range of the first storage area.

3. The data processing module of claim 2, further comprising an arbitration unit, wherein said parsing unit is connected to said second AHB bus via said arbitration unit;

two input ends of the arbitration unit are respectively connected with the first AHB bus and the analysis unit;

the output end of the arbitration unit is connected with the second AHB bus;

the arbitration unit is configured to receive a second data packet sent by the processor and a first data packet sent by the analysis unit, and sequentially transmit the second data packet and the first data packet to corresponding functional units in a time-division multiplexing manner.

4. A data processing module according to any one of claims 1 to 3, characterized in that said AXI read control unit comprises:

a reading control subunit, configured to read the corresponding frame configuration parameter from the storage controller according to the first instruction;

the buffer sub-unit is used for buffering the plurality of frame configuration parameters read by the reading control sub-unit and generating a buffer queue;

the analysis unit is used for reading the frame configuration parameters from the buffer queue of the buffer subunit in sequence for analysis.

5. The data processing module of claim 4, wherein the buffer queue is a first-in-first-out queue.

6. The data processing module of claim 1, wherein the frame configuration parameters comprise a frame header, a frame consecutive address parameter configuration section, and a frame discrete address parameter configuration section;

the frame continuous address parameter configuration section comprises a first address and a plurality of sequentially arranged data packets, the plurality of sequentially arranged data packets are respectively in one-to-one correspondence with a plurality of continuous addresses taking the first address as a starting point, and the plurality of continuous addresses are addresses corresponding to a plurality of functional units;

the frame discrete address parameter configuration section comprises a plurality of address-data packet combinations, and the address in the address-data packet is the address of the functional unit corresponding to the data packet.

7. The data processing module of claim 1, wherein the frame configuration parameters comprise a frame header and a frame sequential address parameter configuration section;

the frame continuous address parameter configuration section comprises a first address and a plurality of sequentially arranged data packets, and the plurality of sequentially arranged data packets are respectively in one-to-one correspondence with a plurality of continuous addresses taking the first address as a starting point.

8. A chip comprising a data processing module according to any one of claims 1 to 7.

9. A data processing method is used in a data processing module of a chip, the chip also comprises a processor, a storage controller and a plurality of functional units which are respectively connected with the data processing module, the storage controller is connected with an external memory, and the method is characterized by comprising the following steps:

acquiring a first instruction received from the processor through a first AHB bus;

reading corresponding frame configuration parameters from the memory controller according to the first instruction and through an AXI bus;

parsing the frame configuration parameters into a plurality of first packets based on an AHB protocol;

and transmitting the plurality of first data packets to corresponding functional units through a second AHB bus.

10. The data processing method according to claim 9, wherein the external memory includes a first storage area;

the AHB is used for receiving a plurality of original data packets sent by the processor;

the obtaining a first instruction received from the processor via a first AHB bus comprises:

and identifying the address of an original data packet received from the processor through the first AHB bus so as to screen out a first instruction in the original data packet, wherein the address in the first instruction is located in the address range of the first storage area.

11. The data processing method of claim 10, wherein the original data packet is the first instruction or a second data packet for direct transmission to a corresponding functional unit;

the transmitting the plurality of first data packets to the corresponding functional units through the second AHB bus includes:

and sequentially transmitting the second data packet and the first data packet to the second AHB bus in a time division multiplexing mode so as to transmit the plurality of first data packets and the second data packet to corresponding functional units through the second AHB bus.

12. The data processing method according to claim 9, wherein the frame configuration parameters comprise a frame header, a frame continuous address parameter configuration section and/or a frame discrete address parameter configuration section;

the frame continuous address parameter configuration section comprises a first address and a plurality of sequentially arranged data packets, the plurality of sequentially arranged data packets are respectively in one-to-one correspondence with a plurality of continuous addresses taking the first address as a starting point, and the plurality of continuous addresses are addresses corresponding to a plurality of functional units;

the frame discrete address parameter configuration section comprises a plurality of address-data packet combinations, and the address in the address-data packet is the address of the functional unit corresponding to the data packet.

13. A data processing device is used in a data processing module of a chip, the chip further comprises a processor, a storage controller and a plurality of functional units which are respectively connected with the data processing module, the storage controller is connected with an external memory, and the device is characterized by comprising:

the acquisition module is used for acquiring a first instruction which is received from the processor through a first AHB bus;

a read module configured to read corresponding frame configuration parameters from the memory controller according to the first instruction and through an AXI bus;

the analysis module is used for analyzing the frame configuration parameters into a plurality of first data packets based on an AHB protocol;

and the transmission module is used for transmitting the plurality of first data packets to the corresponding functional units through a second AHB bus.

Technical Field

The application relates to the technical field of chips, in particular to a data processing method, a data processing device, a data processing module and a chip.

Background

An apb (advanced peripheral bus) bus or an ahb (advanced High Performance bus) bus is usually adopted in the design of an ip (intellectual property) core of a chip to perform parameter configuration, and the commonly used data bit width does not exceed 32 bits.

In the prior art, the chip needs to issue instructions to be initiated by the processor, and the processor needs to perform a processor response once every time the processor issues an instruction through the APB bus or the AHB bus, which results in low processing efficiency for the instructions, and when the issued instructions are more, the workload of the processor is more stressed.

In view of the above problems, no effective technical solution exists at present.

Disclosure of Invention

An object of the embodiments of the present application is to provide a data processing method, device, module and chip, which can improve instruction processing efficiency and reduce the working pressure of a processor.

In a first aspect, an embodiment of the present application provides a data processing module, which is used in a chip, where the chip further includes a processor, a storage controller, and a plurality of functional units, which are respectively connected to the processor, the storage controller is connected to an external memory, and the data processing module includes:

an AXI bus connected with the memory controller;

a first AHB bus coupled to said processor;

the AHB configuration unit is connected with the first AHB bus to acquire a first instruction sent by the processor;

an AXI read control unit connected with the AXI bus for controlling the memory controller to read corresponding frame configuration parameters from an external memory according to the first instruction;

a parsing unit connected with the AXI read control unit for parsing the frame configuration parameters into a plurality of first data packets based on an AHB protocol;

and one end of the second AHB bus is connected with the analysis unit, and the other end of the second AHB bus is connected with the plurality of functional units and is used for transmitting the plurality of first data packets to the corresponding functional units.

Optionally, in the data processing module according to the embodiment of the present application, the external memory includes a first storage area;

the AHB is used for receiving a plurality of original data packets sent by the processor, wherein the original data packets are the first instructions or second data packets used for being directly sent to corresponding functional units;

the AHB configuration unit is configured to identify an address in each original data packet, so as to screen out a first instruction therein, and send the first instruction to the AXI read control unit, where an address in the first instruction is located in an address range of the first storage area.

Optionally, in the data processing module according to the embodiment of the present application, the data processing module further includes an arbitration unit, and the analysis unit is connected to the second AHB bus through the arbitration unit;

two input ends of the arbitration unit are respectively connected with the first AHB bus and the analysis unit;

the output end of the arbitration unit is connected with the second AHB bus;

the arbitration unit is configured to receive a second data packet sent by the processor and a first data packet sent by the analysis unit, and sequentially transmit the second data packet and the first data packet to corresponding functional units in a time-division multiplexing manner.

Optionally, in the data processing module according to this embodiment of the present application, the AXI read control unit includes:

a reading control subunit, configured to read the corresponding frame configuration parameter from the storage controller according to the first instruction;

the buffer sub-unit is used for buffering the plurality of frame configuration parameters read by the reading control sub-unit and generating a buffer queue;

the analysis unit is used for reading the frame configuration parameters from the buffer queue of the buffer subunit in sequence for analysis.

Optionally, in the data processing module according to the embodiment of the present application, the buffer queue is a first-in first-out queue.

Optionally, in the data processing module according to the embodiment of the present application, the frame configuration parameter includes a frame header, a frame continuous address parameter configuration section, and a frame discrete address parameter configuration section;

the frame continuous address parameter configuration section comprises a first address and a plurality of sequentially arranged data packets, the plurality of sequentially arranged data packets are respectively in one-to-one correspondence with a plurality of continuous addresses taking the first address as a starting point, and the plurality of continuous addresses are addresses corresponding to a plurality of functional units;

the frame discrete address parameter configuration section comprises a plurality of address-data packet combinations, and the address in the address-data packet is the address of the functional unit corresponding to the data packet.

Optionally, in the data processing module according to the embodiment of the present application, the frame configuration parameter includes a frame header and a frame consecutive address parameter configuration section;

the frame continuous address parameter configuration section comprises a first address and a plurality of sequentially arranged data packets, and the plurality of sequentially arranged data packets are respectively in one-to-one correspondence with a plurality of continuous addresses taking the first address as a starting point.

In a second aspect, an embodiment of the present application further provides a chip, including any one of the data processing modules described above.

In a third aspect, an embodiment of the present application further provides a data processing method, which is used in a data processing module of a chip, where the chip further includes a processor, a storage controller, and a plurality of functional units, which are respectively connected to the data processing module, and the storage controller is connected to an external memory, and the method includes:

acquiring a first instruction received from the processor through a first AHB bus;

reading corresponding frame configuration parameters from the memory controller according to the first instruction and through an AXI bus;

parsing the frame configuration parameters into a plurality of first packets based on an AHB protocol;

and transmitting the plurality of first data packets to corresponding functional units through a second AHB bus.

Optionally, in the data processing method according to the embodiment of the present application, the external memory includes a first storage area;

the AHB is used for receiving a plurality of original data packets sent by the processor;

the obtaining a first instruction received from the processor via a first AHB bus comprises:

and identifying the address of an original data packet received from the processor through the first AHB bus so as to screen out a first instruction in the original data packet, wherein the address in the first instruction is located in the address range of the first storage area.

Optionally, in the data processing method according to the embodiment of the present application, the original data packet is the first instruction, or is a second data packet for directly sending to a corresponding functional unit;

the transmitting the plurality of first data packets to the corresponding functional units through the second AHB bus includes:

and sequentially transmitting the second data packet and the first data packet to the second AHB bus in a time division multiplexing mode so as to transmit the plurality of first data packets and the second data packet to corresponding functional units through the second AHB bus.

Optionally, in the data processing method according to the embodiment of the present application, the frame configuration parameter includes a frame header, a frame continuous address parameter configuration section, and/or a frame discrete address parameter configuration section;

the frame continuous address parameter configuration section comprises a first address and a plurality of sequentially arranged data packets, the plurality of sequentially arranged data packets are respectively in one-to-one correspondence with a plurality of continuous addresses taking the first address as a starting point, and the plurality of continuous addresses are addresses corresponding to a plurality of functional units;

the frame discrete address parameter configuration section comprises a plurality of address-data packet combinations, and the address in the address-data packet is the address of the functional unit corresponding to the data packet.

In a fourth aspect, an embodiment of the present application further provides a data processing apparatus, configured in a data processing module of a chip, where the chip further includes a processor, a storage controller, and a plurality of functional units, which are respectively connected to the data processing module, and the storage controller is connected to an external memory, where the apparatus includes:

the acquisition module is used for acquiring a first instruction which is received from the processor through a first AHB bus;

a read module configured to read corresponding frame configuration parameters from the memory controller according to the first instruction and through an AXI bus;

the analysis module is used for analyzing the frame configuration parameters into a plurality of first data packets based on an AHB protocol;

and the transmission module is used for transmitting the plurality of first data packets to the corresponding functional units through a second AHB bus.

As can be seen from the above, in the embodiment of the present application, a plurality of instructions are packaged and stored in the external memory in the form of frame configuration parameters, an AXI bus is adopted to directly read the frame configuration parameters from the external memory, and then further parse and convert the frame configuration parameters into a plurality of first data packets corresponding to an AHB bus protocol, and then the plurality of first data packets are transmitted to a corresponding functional unit through the AHB bus for execution, so that when a plurality of instructions need to be sent to the functional unit, a processor does not need to perform multiple responses, and therefore, the instruction processing efficiency can be improved, and the burden of the processor can be reduced.

Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic structural diagram of a data processing module according to an embodiment of the present disclosure.

Fig. 2 is a data structure diagram of a frame sequential address parameter configuration section in the embodiment of the present application.

Fig. 3 is a data structure diagram of a frame discrete address parameter configuration section in the embodiment of the present application.

Fig. 4 is a schematic structural diagram of another data processing module according to an embodiment of the present disclosure.

Fig. 5 is a flowchart of a data processing method according to an embodiment of the present application.

Fig. 6 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a data processing module in some embodiments of the present application. The data processing module 100 is used in a chip. The chip also includes a processor 300, a memory controller 200, and a plurality of functional units 400. The processor 300 is connected to the data processing module 100, the memory controller 200 is connected to the data processing module 100, and the plurality of functional units 400 are connected to the parameter configuration module 100. The memory controller 200 is connected to an external memory. The processor 300 sends a first command to the data processing module 100, and the data processing module 100 controls the memory controller 200 to read the corresponding frame configuration parameter from the external memory according to the first command. The memory controller 200 may be a DDR memory controller, and correspondingly, the external memory is a DDR memory (double data rate synchronous dynamic random access memory), which is not limited thereto. The plurality of functional units 400 are respectively used to implement different functions.

Since the data processing module 100 and the external memory are not directly connected but connected through the memory controller, the data read by the data processing module 100 is actually realized through the memory controller, and of course, the data can also be read from the memory controller.

Specifically, the data processing module 100 includes: a first AHB bus 101, an AXI (advanced xtensibleinterface) bus 102, a second AHB bus 103, an AHB configuration unit 104, an AXI read control unit 105, and a parsing unit 106. The AXI bus 102 is connected to a memory controller 200; the first AHB bus 101 is connected with the processor 300; the AHB configuration unit 104 is connected to the first AHB bus 101, the AXI read control unit 105 is connected to the AXI bus 102, the resolution unit 106 is connected to the AXI read control unit 105, and the second AHB bus 103 has one end connected to the resolution unit 106 and the other end connected to the plurality of functional units 400.

Specifically, the first AHB bus 101 is used for receiving a first instruction based on the AHB protocol from the processor 300. The address carried in the first instruction is located in the address range of the first storage area of the external memory. Of course, it is understood that the first AHB bus 101 can also receive a second data packet based on the AHB protocol sent by the processor 300. The second data packet may be transmitted directly to the corresponding functional unit 400 via the second AHB bus 103. That is, the AHB bus is configured to receive a plurality of original data packets sent by the processor, where the original data packets are the first instruction or second data packets for directly sending to the corresponding functional unit, and the AHB configuration unit 104 identifies an address in the original data packet to extract the first instruction. The first data packet may be formed by packing a plurality of configuration parameters in combination with addresses of the functional units corresponding to the configuration parameters, or may be formed by packing a plurality of control instructions and addresses of the corresponding functional units. The second data packet may be a configuration parameter or a control command.

Specifically, the AXI read control unit 105 is configured to control the memory controller 200 to read the corresponding frame configuration parameters from the external memory according to a first instruction. The AXI read control unit 105 is connected to the memory controller 200 via an AXI bus 102, the AXI bus 102 is based on an AXI protocol for data transmission, and the AXI protocol is based on burst transmission, and is a high-performance, high-bandwidth, low-latency on-chip bus defining five channels of read address, read data, write address, write data, and write response. The transmission characteristic of the AXI protocol is that only one burst first address is needed, a plurality of burst transmission first addresses can be continuously sent without waiting for the completion of the previous burst transmission, the utilization rate of a bus is greatly improved, and the dependence on the response of a processor is reduced.

Specifically, in some embodiments, the AXI read control unit 105 includes a read control subunit and a buffer subunit, the read control subunit being configured to read the corresponding frame configuration parameters from the memory controller according to the first instruction; the buffer subunit is configured to buffer the plurality of frame configuration parameters read by the read control subunit and generate a buffer queue. The cache subunit can reduce the mismatch between the reading speed and the using speed, and can deal with the performance loss caused by the delay of the AXI bus burst transmission.

Wherein the frame configuration parameters include: frame head, frame continuous address parameter configuration section, frame discrete address parameter configuration section. Of course, it is understood that the frame configuration parameters may include only: frame head, frame continuous address parameter configuration section. Alternatively, the frame configuration parameters may include only: frame head, frame discrete address parameter configuration section.

The data structure of the frame header is fixed length byte data, which mainly represents other self-defined information such as the current frame number, the data amount of the current frame configuration parameter, and the like.

The parameter configuration section of the frame continuous address can realize the parameter configuration of the continuous address by adopting a mode of adding a plurality of instructions to the first address. For example, the frame sequential address parameter configuration segment may be in the following format: the first address 1-packet 2-packet 3-packet 4, where each packet may be 4 bytes in length. Or as shown in fig. 2, fig. 2 is a data structure of the field configured for the consecutive address parameters of the frame.

As shown in fig. 3, the frame discrete address parameter configuration section includes a plurality of "address-instruction" combinations, which can implement parameter configuration of discrete addresses, and this scenario is suitable for inter-frame configuration update of common parameter registers and the like. The AHB address unit is byte, so that the low 2-bit address line of the 32-bit data bit wide second AHB bus does not participate in address decoding and can be used as a distinguishing mark of a continuous address (2 'b 01) and a discrete address (2' b 00).

Wherein, each address in the frame continuous address parameter configuration section and the frame discrete address parameter configuration section refers to an address corresponding to a functional unit needing to be received.

The parsing unit 106 is configured to parse the frame configuration parameters into a plurality of first data packets based on the AHB protocol; the parsing unit 106 is specifically configured to sequentially read the frame configuration parameters from the buffer queue of the buffer subunit for parsing.

Second AHB bus 103 is used to transmit a plurality of second packets to corresponding functional units 400. When parsing the frame configuration parameters, the parsing unit 106 parses the frame configuration parameters into a plurality of first packets based on the AHB protocol.

For example, for the frame consecutive address parameter configuration segment, if the number of instructions included in the frame consecutive address parameter configuration segment is greater than a preset threshold, the frame consecutive address parameter configuration segment needs to be parsed into a plurality of consecutive segments, and the format of each consecutive segment is: header 1-packet data packet 2-packet data packet 3. Wherein the address 1 refers to an address of a functional unit corresponding to the packet data packet 1. The address corresponding to packet data packet 2 is the address of packet data packet 1 plus the corresponding address offset. The corresponding address of packet data packet 3 is the address of packet data packet 1 plus the corresponding address offset.

Of course, if the number of instructions included in the frame consecutive address parameter configuration segment is less than the preset threshold, the frame consecutive address parameter configuration segment does not need to be split into a plurality of consecutive segments.

For the frame discrete address parameter configuration segment, the frame discrete address parameter configuration segment needs to be analyzed to obtain a plurality of first data packets based on the AHB protocol, and the format of each first data packet is "address-data packet 4". The address in the "address packet data packet 4" refers to the address of the functional unit to which the packet data packet 4 corresponds.

As can be seen from the above, in the embodiment of the present application, a plurality of instructions are packaged and stored in the external memory in the form of frame configuration parameters, an AXI bus is adopted to directly read the frame configuration parameters from the external memory, and then further analyze and convert the frame configuration parameters into a plurality of first data packets corresponding to an AHB bus protocol, and then the plurality of first data packets are transmitted to a corresponding functional unit through the AHB bus for execution, so that when a plurality of data packets need to be sent to the functional unit, a processor does not need to perform multiple responses, the instruction processing efficiency can be improved, and the burden of the processor can be reduced; the method and the device also utilize the characteristics of large data bit width and high data transmission rate of the AXI bus, and can quickly load the address-data packet pair to be configured into the data processing module from the external memory.

It will be appreciated that in some embodiments, as shown in FIG. 4, the data processing module further comprises an arbitration unit 107. Two input ends of the arbitration unit 107 are respectively connected to the analysis unit 106 and the first AHB bus 101, one end of the second AHB bus 103 is connected to the output end of the arbitration unit 107, and the other end thereof is connected to the plurality of functional units 400, and is configured to transmit a plurality of second data packets to the corresponding functional units 400.

The arbitration unit 107 is configured to receive a second data packet sent by the processor 300 and a first data packet sent by the analysis unit 106, and sequentially transmit the second data packet and the first data packet to the corresponding functional units 400 in a time-division multiplexing manner, so as to avoid access collision. Of course, when performing the arbitration operation, the arbitration unit 107 may preferentially perform sending the second packet from the processor 300 to the corresponding functional unit, and then perform sending the second packet from the parsing unit 106. Of course, it is understood that the arbitration unit 107 may also use the first-in-first-out principle to perform the transmission operation on the first data packet and the second data packet.

Referring to fig. 5, fig. 5 is a flowchart of a data processing method according to some embodiments of the present application. The method is applied to a data processing module of a chip, as shown in fig. 6, the chip further includes a processor, a memory controller and a plurality of functional units, which are respectively connected with the data processing module, and the memory controller is connected with an external memory. The data processing method is integrated in the data processing module in the form of a computer program.

The data processing method comprises the following steps:

s201, acquiring a first instruction received from the processor through a first AHB bus.

S202, reading corresponding frame configuration parameters from the memory controller through an AXI bus according to the first instruction.

S203, the frame configuration parameters are analyzed into a plurality of first data packets based on an AHB protocol.

And S204, transmitting the first data packets to corresponding functional units through a second AHB bus.

In step S201, the address carried in the first instruction is located in the address range of the first storage area of the external memory. Of course, it is understood that the first AHB bus may also receive a second data packet based on the AHB protocol issued by the processor. The second packet may be transmitted directly to the corresponding functional unit via the second AHB bus 103.

In some embodiments, the external memory includes a first memory area; the AHB is used for receiving a plurality of original data packets sent by the processor; the step S201 specifically includes: and identifying the address of an original data packet received from the processor through the first AHB bus so as to screen out a first instruction in the original data packet, wherein the address in the first instruction is located in the address range of the first storage area.

In step S202, the step is executed to control the memory controller to read the corresponding frame configuration parameters from the external memory according to the first instruction. The AXI bus is based on AXI protocol data transmission, the AXI protocol is based on burst transmission, the AXI bus is an on-chip bus oriented to high performance, high bandwidth and low delay, and five channels of read address, read data, write address, write data and write response are defined. The transmission characteristic of the AXI protocol is that only one burst first address is needed, a plurality of burst transmission first addresses can be continuously sent without waiting for the completion of the previous burst transmission, the utilization rate of a bus is greatly improved, and the dependence on the response of a processor is reduced.

Specifically, in some embodiments, this step S202 includes:

s2021, reading corresponding frame configuration parameters from the storage controller according to the first instruction; s2022, buffering the read frame configuration parameters and generating a buffer queue. By generating the plurality of frame configuration parameters into the buffer queue, the mismatch between the reading speed and the use speed can be reduced, and the performance loss caused by the delay of the AXI bus burst transmission can be solved.

Wherein the frame configuration parameters include: frame head, frame continuous address parameter configuration section, frame discrete address parameter configuration section. Of course, it is understood that the frame configuration parameters may include only: frame head, frame continuous address parameter configuration section. Alternatively, the frame configuration parameters may include only: frame head, frame discrete address parameter configuration section.

The data structure of the frame header is fixed length byte data, which mainly represents other self-defined information such as the current frame number, the data amount of the current frame configuration parameter, and the like.

The parameter configuration section of the frame continuous address can realize the parameter configuration of the continuous address by adopting a mode of adding a plurality of instructions to the first address. For example, the frame sequential address parameter configuration segment may be in the following format: the first address 1-data packet 2-data packet 3-data packet 4, wherein each data packet is 4 bytes in length. Or as shown in fig. 2, fig. 2 is a data structure of the field configured for the consecutive address parameters of the frame.

As shown in fig. 3, the frame discrete address parameter configuration section includes a plurality of "address-data packet" combinations, and can implement parameter configuration of discrete addresses, and this scenario is suitable for inter-frame configuration update of a common parameter register and the like. The AHB address unit is byte, so that the low 2-bit address line of the 32-bit data bit wide second AHB bus does not participate in address decoding and can be used as a distinguishing mark of a continuous address (2 'b 01) and a discrete address (2' b 00).

Wherein, each address in the frame continuous address parameter configuration section and the frame discrete address parameter configuration section refers to an address corresponding to a functional unit needing to be received.

In step S203, when the specific implementation is performed, the frame configuration parameters may be sequentially read from the buffer queue for analysis. For the frame consecutive address parameter configuration segment, if the number of instructions included in the frame consecutive address parameter configuration segment is greater than a preset threshold, the frame consecutive address parameter configuration segment needs to be parsed into a plurality of consecutive segments, and the format of each consecutive segment is: first address 1-packet 2-packet 3. The address 1 refers to an address of a functional unit corresponding to the data packet 1. The address corresponding to packet 2 is the address of packet 1 plus the corresponding address offset. The address corresponding to packet 3 is the address of packet 1 plus the corresponding address offset.

Of course, if the number of instructions included in the frame consecutive address parameter configuration segment is less than the preset threshold, the frame consecutive address parameter configuration segment does not need to be split into a plurality of consecutive segments.

For the frame discrete address parameter configuration segment, the frame discrete address parameter configuration segment needs to be analyzed to obtain a plurality of first data packets based on the AHB protocol, and the format of each first data packet is "address-data packet 4". The address in the "address-packet 4" refers to the address of the functional unit to which the packet 4 corresponds.

In step S204, the original data packets sent by the processor may only include the first instruction. Of course, the plurality of original data packets may also include the first command and the plurality of second data packets; correspondingly, the step S204 includes: and sequentially transmitting the second data packet and the first data packet to the second AHB bus in a time division multiplexing mode so as to transmit the plurality of first data packets and the plurality of second data packets to corresponding functional units through the second AHB bus. In step S204, the second packet from the processor may be preferentially transmitted to the corresponding functional unit, and then the first packet obtained by analysis may be transmitted. Of course, it is understood that, in the step S204, a first-in first-out principle may also be adopted to perform a transmission operation on the first data packet and the second data packet.

As can be seen from the above, in the embodiment of the present application, a plurality of data packets are packed and stored in the external memory in the form of frame configuration parameters, and an AXI bus is adopted to directly read the frame configuration parameters from the external memory, and then further analyze and convert the frame configuration parameters into a plurality of first data packets corresponding to an AHB bus protocol, and then transmit the plurality of first data packets to a corresponding functional unit through the AHB bus for execution, so that when a plurality of data packets need to be sent to the functional unit, a processor does not need to perform multiple responses, the instruction processing efficiency can be improved, and the burden of the processor can be reduced; the method and the device also utilize the characteristics of large data bit width and high data transmission rate of the AXI bus, and can quickly load the data packet-instruction pair to be configured into the data processing module from the external memory.

Referring to fig. 6, fig. 6 is a data processing apparatus for use in a data processing module of a chip according to some embodiments of the present disclosure. The chip also comprises a processor, a storage controller and a plurality of functional units which are respectively connected with the data processing module, the storage controller is connected with an external memory, and the data processing device is integrated in the data processing module in the form of a computer program. The data processing apparatus includes: a first obtaining module 301, a reading module 302, a parsing module 303 and a transmitting module 304.

The first obtaining module 301 is configured to obtain a first instruction received from the processor through a first AHB bus.

Wherein the reading module 302 is configured to read the corresponding frame configuration parameters from the memory controller through the AXI bus according to the first instruction.

The parsing module 303 is configured to parse the frame configuration parameters into a plurality of first data packets based on the AHB protocol.

The transmission module 304 is configured to transmit the first data packets to the corresponding functional units through the second AHB bus.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated together to form an independent part, or each unit may exist separately, or two or more units may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.