阅读说明：本技术 显示面板及其制造方法 (Display panel and method for manufacturing the same ) 是由 李昶勳 金旻载 金慜熙 金泰薰 朴卿蕙 朴俊炯 梁丹雨 于 2020-02-03 设计创作，主要内容包括：提供了一种显示面板及其制造方法。所述显示面板包括上显示基底和下显示基底。上显示基底包括：基体基底；遮光图案,包括限定在遮光图案中的与像素区域对应的开口部分；滤色器,与像素区域叠置；封装层,设置在遮光图案的下侧和滤色器的下侧上；分隔壁,设置在封装层的下侧上,与遮光区域叠置,并且包括限定在分隔壁中的与像素区域对应的分隔壁开口部分；以及量子点层,设置在分隔壁开口部分的内部。分隔壁包括第一层和第二层,第一层直接设置在封装层的底表面上,第二层直接设置在第一层的下侧上并具有比第一层大的光学密度。(A display panel and a method of manufacturing the same are provided. The display panel includes an upper display substrate and a lower display substrate. The upper display substrate includes: a base substrate; a light shielding pattern including an opening portion defined in the light shielding pattern corresponding to the pixel region; a color filter overlapping the pixel region; an encapsulation layer disposed on a lower side of the light blocking pattern and a lower side of the color filter; a partition wall disposed on a lower side of the encapsulation layer, overlapping the light-shielding region, and including a partition wall opening portion defined therein corresponding to the pixel region; and a quantum dot layer disposed inside the opening portion of the partition wall. The partition wall includes a first layer disposed directly on a bottom surface of the encapsulation layer and a second layer disposed directly on a lower side of the first layer and having a greater optical density than the first layer.)

1. A display panel, the display panel comprising:

an upper display substrate including a first pixel region, a second pixel region, and a third pixel region, and a light shielding region in a periphery of the first pixel region, the second pixel region, and the third pixel region; and

a lower display substrate including first, second, and third display elements corresponding to the first, second, and third pixel regions, respectively,

wherein the upper display substrate includes:

a base substrate;

a light shielding pattern disposed on a bottom surface of the base substrate, overlapping the light shielding region, and including first, second, and third opening portions defined therein, corresponding to the first, second, and third pixel regions, respectively;

first, second, and third color filters disposed on the bottom surface of the base substrate and overlapping the first, second, and third pixel regions, respectively;

a partition wall disposed on lower sides of the first, second, and third color filters, overlapping the light-shielding region, and including first, second, and third partition wall opening portions defined in the partition wall corresponding to the first, second, and third pixel regions, respectively; and

a first color control layer, a second color control layer, and a third color control layer provided in the first partition wall opening portion, the second partition wall opening portion, and the third partition wall opening portion, respectively,

wherein the partition wall includes a first layer and a second layer that is provided directly on a lower side of the first layer and has an optical density larger than that of the first layer, and

a portion of the second layer protrudes downward from the first, second, and third color control layers in a cross-sectional view.

2. The display panel of claim 1, wherein the optical density of the second layer is from 0.15 to 0.5 when the thickness of the second layer is 1 μm.

3. The display panel of claim 1, wherein the second layer comprises a hydrophobic region and a hydrophilic region disposed between the hydrophobic region and the first layer.

4. The display panel of claim 3, wherein the second layer has a thickness of from 7 μm to 10 μm.

5. The display panel of claim 4, wherein the hydrophilic region comprises a matrix resin and a black colorant mixed with the matrix resin, and the hydrophobic region comprises a hydrophobic agent chemically bonded to the matrix resin.

6. The display panel of claim 3, wherein the hydrophobic region has a thickness from 30nm to 200 nm.

7. The display panel of claim 1, wherein each of the first, second, and third color control layers has a thickness of 15 μ ι η or greater.

8. The display panel according to claim 7, wherein a height of the partition wall in the light-shielding region is higher than a height of each of the first color control layer, the second color control layer, and the third color control layer.

9. The display panel of claim 7, wherein the first layer has a thickness of from 5 μm to 15 μm, and

the second layer has a thickness of from 5 μm to 10 μm.

10. The display panel of claim 1, wherein the first layer has a width of from 10 μ ι η to 15 μ ι η.

11. The display panel of claim 1, wherein the second layer completely overlaps the first layer in a plan view.

12. The display panel according to claim 1, wherein the light-shielding pattern includes a blue first light-shielding layer and a black second light-shielding layer, the second light-shielding layer covering at least a bottom surface of the first light-shielding layer.

13. The display panel according to claim 1, wherein each of the first display element, the second display element, and the third display element includes a first electrode, a second electrode, and an emission layer provided between the first electrode and the second electrode, and

the emission layers of the first, second, and third display elements have an integral shape and generate blue light.

14. The display panel of claim 13, wherein the first color control layer comprises first quantum dots configured to convert the blue light to red light,

the second color control layer includes second quantum dots configured to convert the blue light into green light, and

the third color control layer transmits the blue light.

15. A display panel, the display panel comprising:

an upper display substrate including a pixel region and a peripheral region adjacent to the pixel region; and

a lower display substrate including display elements disposed to correspond to the pixel regions,

wherein the upper display substrate includes:

a base substrate;

a light shielding pattern disposed on a bottom surface of the base substrate, overlapping the peripheral region, and including an opening portion defined in the light shielding pattern corresponding to the pixel region;

a color filter disposed on the bottom surface of the base substrate and overlapping the pixel region;

an encapsulation layer disposed on a lower side of the light blocking pattern and a lower side of the color filter;

a partition wall disposed on a lower side of the encapsulation layer, overlapping the peripheral region, and including a partition wall opening portion defined therein corresponding to the pixel region; and

a quantum dot layer provided in the partition wall opening portion,

wherein the partition wall includes a first layer directly disposed on a bottom surface of the encapsulation layer and a second layer directly disposed on a lower side of the first layer and having an optical density greater than that of the first layer.

16. A manufacturing method of a display panel, the manufacturing method comprising the steps of:

manufacturing a first display substrate including a display element;

manufacturing a second display substrate including a pixel region corresponding to the display element and a light shielding region in a periphery of the pixel region; and

bonding the first display substrate and the second display substrate,

wherein the manufacturing of the second display substrate comprises:

forming a light-shielding pattern on a base substrate to overlap the light-shielding region;

forming a color filter overlapping the pixel region;

forming a first initial barrier rib layer on the base substrate;

exposing the first initial barrier rib layer so that a first region of the first initial barrier rib layer overlapping the light shielding pattern is separated from a second region disposed in a periphery of the first region;

forming a second initial barrier rib layer on the first initial barrier rib layer after the exposure;

exposing the second initial barrier rib layer so that a third area of the second initial barrier rib layer corresponding to the first area is separated from a fourth area corresponding to the second area;

developing the first initial partition wall layer and the second initial partition wall layer so that partition walls and partition wall opening portions surrounded by the partition walls are formed; and

a quantum dot layer is formed in the partition wall opening portion.

17. The manufacturing method according to claim 16, wherein the forming of the second initial partition wall layer includes:

forming a composition layer including a matrix resin, a black colorant, and a hydrophobic agent on the first initial barrier rib layer;

drying the composition layer; and

primarily baking the composition layer to provide heat to the composition layer.

18. The manufacturing method according to claim 17, wherein the composition layer after the primary baking includes a hydrophilic region containing the matrix resin and the black colorant, and a hydrophobic region containing the hydrophobic agent chemically bonded to the matrix resin.

19. The manufacturing method of claim 17, further comprising the steps of:

secondarily baking the partition wall after the development to provide heat to the partition wall,

wherein the temperature in the secondary baking is higher than the temperature in the primary baking.

20. The manufacturing method according to claim 16, wherein the forming of the first initial partition wall layer includes:

forming a composition layer including a base resin on the base substrate;

drying the composition layer; and is

Baking the composition layer to provide heat to the composition layer.

Technical Field

The present disclosure herein relates to a display panel and a method of manufacturing the same, and more particularly, to a display panel including a partition wall and a method of manufacturing the same.

Background

The display panel includes a transmissive display panel that selectively transmits source light generated by the light source and an emissive display panel that generates the source light therein. The display panel may include different kinds of color control layers according to pixels to generate a color image. The color control layer may transmit only some wavelength ranges of the source light or change the color of the source light. Some color control layers may change the characteristics of the source light without changing the color of the source light.

Disclosure of Invention

The present disclosure provides a display panel in which luminance is increased and color mixing is prevented.

The present disclosure also provides a method of manufacturing a display panel in which material consumption is reduced.

Embodiments of the inventive concept provide a display panel including an upper display substrate and a lower display substrate, the upper display substrate including first, second, and third pixel regions and a light blocking region in a periphery of the first, second, and third pixel regions, the lower display substrate including first, second, and third display elements corresponding to the first, second, and third pixel regions, respectively, wherein the upper display substrate includes: a base substrate; a light shielding pattern disposed on a bottom surface of the base substrate, overlapping the light shielding region, and including first, second, and third opening portions defined therein corresponding to the first, second, and third pixel regions, respectively; first, second, and third color filters disposed on a bottom surface of the base substrate and overlapping the first, second, and third pixel regions, respectively; a partition wall disposed on lower sides of the first, second, and third color filters, overlapping the light blocking area, and including first, second, and third partition wall opening portions defined therein corresponding to the first, second, and third pixel areas, respectively; and a first color control layer, a second color control layer, and a third color control layer disposed in the first partition wall opening portion, the second partition wall opening portion, and the third partition wall opening portion, respectively, wherein the partition wall includes a first layer and a second layer, the second layer is disposed directly on a lower side of the first layer and has an optical density greater than that of the first layer, and a part of the second layer protrudes downward from the first color control layer, the second color control layer, and the third color control layer in a cross-sectional view.

In an embodiment, when the thickness of the second layer is 1 μm, the optical density of the second layer may be from about 0.15 to about 0.5.

In an embodiment, the second layer may include a hydrophobic region and a hydrophilic region disposed between the hydrophobic region and the first layer.

In an embodiment, the second layer may have a thickness from about 7 μm to about 10 μm.

In an embodiment, the hydrophilic region includes a matrix resin and a black colorant mixed with the matrix resin, and the hydrophobic region includes a hydrophobic agent chemically bonded to the matrix resin.

In an embodiment, the hydrophobic region may have a thickness from about 30nm to about 200 nm.

In an embodiment, each of the first, second, and third color control layers may have a thickness of about 15 μm or more.

In an embodiment, a height of the partition wall in the light-shielding region may be higher than a height of each of the first, second, and third color control layers.

In an embodiment, the first layer may have a thickness of from about 5 μm to about 15 μm, and the second layer may have a thickness of from about 5 μm to about 10 μm.

In an embodiment, the width of the first layer may be from about 10 μm to about 15 μm.

In an embodiment, the second layer may completely overlap the first layer in plan view.

In an embodiment, the light blocking pattern may include a blue first light blocking layer and a black second light blocking layer covering at least a bottom surface of the first light blocking layer.

In an embodiment, each of the first, second, and third display elements may include a first electrode, a second electrode, and an emission layer disposed between the first electrode and the second electrode, and the emission layers of the first, second, and third display elements may have an integrated shape and generate blue light.

In an embodiment, the first color control layer may include first quantum dots configured to convert blue light into red light, the second color control layer may include second quantum dots configured to convert blue light into green light, and the third color control layer may transmit blue light.

In an embodiment of the inventive concept, a display panel includes an upper display substrate including a pixel region and a peripheral region in a periphery of the pixel region, and a lower display substrate including display elements disposed to correspond to the pixel region, wherein the upper display substrate includes: a base substrate; a light blocking pattern disposed on a bottom surface of the base substrate, overlapping the peripheral region, and including an opening portion defined therein corresponding to the pixel region; a color filter disposed on a bottom surface of the base substrate and overlapping the pixel region; an encapsulation layer disposed on the lower sides of the light-shielding pattern and the color filter; a partition wall disposed on a lower side of the encapsulation layer, overlapping the peripheral region, and including a partition wall opening portion defined therein corresponding to the pixel region; and a quantum dot layer disposed in the partition wall opening portion, wherein the partition wall includes a first layer disposed directly on a bottom surface of the encapsulation layer and a second layer disposed directly on a lower side of the first layer and having a greater optical density than the first layer.

In an embodiment of the inventive concept, a method of manufacturing a display panel includes manufacturing a first display substrate including display elements, manufacturing a second display substrate including pixel regions corresponding to the display elements and light blocking regions in a periphery of the pixel regions, and bonding the first display substrate and the second display substrate, wherein the manufacturing of the second display substrate includes: forming a light-shielding pattern on the base substrate to overlap the light-shielding region; forming a color filter overlapping the pixel region; forming a first initial barrier rib layer on a base substrate; exposing the first initial barrier rib layer so that a first region of the first initial barrier rib layer overlapping the light shielding pattern is separated from a second region disposed in a periphery of the first region; forming a second initial barrier rib layer on the exposed first initial barrier rib layer; exposing the second initial barrier rib layer so that a third area of the second initial barrier rib layer corresponding to the first area is separated from a fourth area corresponding to the second area; developing the first initial partition wall layer and the second initial partition wall layer so that partition walls and partition wall opening portions surrounded by the partition walls are formed; and forming a quantum dot layer in the partition wall opening portion.

In an embodiment, the formation of the second initial partition wall layer may include the steps of: forming a composition layer including a matrix resin, a black colorant, and a water repellent agent on the first initial barrier rib layer; drying the composition layer; and primarily baking the composition layer to provide heat thereto.

In an embodiment, the primary baked composition layer may include hydrophilic regions comprising a matrix resin and a black colorant and hydrophobic regions comprising a hydrophobic agent chemically bonded to the matrix resin.

In an embodiment, the manufacturing method may further include: after the development, the partition walls are secondarily baked to supply heat thereto, wherein the temperature in the secondary baking is higher than that in the primary baking.

In an embodiment, the forming of the first initial partition wall layer may include: forming a composition layer including a base resin on a base substrate; drying the composition layer; and baking the composition layer to provide heat thereto.

Drawings

The accompanying drawings are included to provide a further understanding of the inventive concepts, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concepts and, together with the description, serve to explain the principles of the inventive concepts. In the drawings:

fig. 1A is a perspective view of a display panel according to an embodiment of the inventive concept;

fig. 1B is a cross-sectional view of a display panel according to an embodiment of the inventive concept;

fig. 2 is a plan view of a display panel according to an embodiment of the inventive concept;

fig. 3A is a plan view of a pixel region of a display panel according to an embodiment of the inventive concept;

fig. 3B is a cross-sectional view of a pixel region of a display panel according to an embodiment of the inventive concept;

fig. 3C is a cross-sectional view of a pixel region of an upper display substrate according to an embodiment of the inventive concept;

fig. 4 is a flowchart illustrating a method of manufacturing a display panel according to an embodiment of the inventive concept;

fig. 5A, 5B, 5C, 5D, and 5E are diagrams illustrating a method of manufacturing an upper display substrate according to an embodiment of the inventive concept;

fig. 6A and 6B are diagrams illustrating a method of manufacturing an upper display substrate according to an embodiment of the inventive concept; and

fig. 7A and 7B are cross-sectional views of a pixel region of an upper display substrate according to an embodiment of the inventive concepts.

Detailed Description

While the inventive concepts are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It will be understood, however, that the inventive concept is not intended to be limited to the particular forms set forth herein, and includes all changes, equivalents, and alternatives falling within the technical scope and spirit of the inventive concept.

Referring to the drawings, like numbers indicate like components throughout. In the drawings, the size of structures may be exaggerated or reduced for clarity of illustration. Terms such as first, second, etc. may be used to describe various components, but these components should not be limited by these terms. These terms are used only for the purpose of distinguishing one component from another. For example, a first component could be termed a second component, or, similarly, a second component could be termed a first component, without departing from the scope of the present disclosure. The singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be understood that the terms "comprises" and "comprising," when used in this specification, are intended to specify the presence of stated features, integers, steps, operations, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, or groups thereof.

Fig. 1A is a perspective view of a display panel DP according to an embodiment of the inventive concept. Fig. 1B is a cross-sectional view of the display panel DP according to an embodiment of the inventive concept. Fig. 2 is a plan view of the display panel DP according to an embodiment of the inventive concept.

Referring to fig. 1A to 2, the display panel DP may be any one of a liquid crystal display panel, an electrophoretic display panel, a Micro Electro Mechanical System (MEMS) display panel, an electrowetting display panel, and an organic light emitting display panel, but is not particularly limited thereto.

Although not separately shown, the display panel DP may further include a chassis member or a molding member, and may further include a backlight unit according to the type of the display panel DP.

The display panel DP may include a first display substrate 100 (or a lower display substrate) and a second display substrate 200 (or an upper display substrate) facing the first display substrate 100 and spaced apart from the first display substrate 100. A predetermined cell gap (cell gap) may be formed between the first display substrate 100 and the second display substrate 200. The cell gap may be maintained by a sealant SLM that combines the first display substrate 100 and the second display substrate 200. A gray scale display layer for image generation may be disposed between the first display substrate 100 and the second display substrate 200. The gray scale display layer may include a liquid crystal display layer, an organic light emitting display layer, and an electrophoretic display layer according to the type of the display panel.

As shown in fig. 1A, the display panel DP may display an image on the display surface DP-IS. The display surface DP-IS parallel to the surface defined by the first orientation axis DR1 and the second orientation axis DR 2. The display surface DP-IS may include a display area DA and a non-display area NDA. The pixels PX are disposed in the display area DA and the pixels PX are not disposed in the non-display area NDA. The non-display area NDA IS defined along an edge of the display surface DP-IS. The display area DA may be surrounded by the non-display area NDA.

The normal direction of the display surface DP-IS (i.e., the thickness direction of the display panel DP) IS indicated by a third direction axis DR 3. The front (or upper) and rear (or lower) surfaces of the respective layers or units, which will be described hereinafter, are defined by a third direction axis DR 3. However, the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 shown in the present embodiment are only examples. Hereinafter, the first direction, the second direction, and the third direction are defined as directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3, respectively, and refer to the same reference numerals.

In an embodiment of the inventive concept, the display panel DP IS shown to include the flat display surface DP-IS, but IS not limited thereto. The display panel DP may include a curved display surface or a three-dimensional display surface. The three-dimensional display surface may include a plurality of display regions facing in different directions.

Fig. 2 shows the planar arrangement relationship of the signal lines GL1 to GLn and DL1 to DLm and the pixels PX11 to PXnm. The signal lines GL1 to GLn and DL1 to DLm may include a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm.

Each of the pixels PX11 to PXnm is connected to a corresponding gate line among the plurality of gate lines GL1 to GLn and a corresponding data line among the plurality of data lines DL1 to DLm. Each of the pixels PX11 to PXnm may include a pixel driving circuit and a display element. The display panel DP may include an additional signal line according to the configuration of the pixel driving circuit of the pixels PX11 to PXnm.

The pixels PX11 to PXnm are exemplarily shown to have a matrix type, but the type of the pixels PX11 to PXnm is not limited thereto. The pixels PX11 to PXnm may be arranged in a PenTile type. The pixels PX11 to PXnm may be arranged in a diamond type. The gate driver circuit GDC may be integrated into the display panel DP through an oxide silicon gate driver circuit (OSG) process or an amorphous silicon gate driver circuit (ASG) process.

Fig. 3A is a plan view of pixel areas PXA-R, PXA-G and PXA-B of the display panel DP according to an embodiment of the inventive concept. Fig. 3B is a cross-sectional view of the pixel area PXA-G of the display panel DP according to an embodiment of the inventive concept. Fig. 3C is a cross-sectional view of the pixel areas PXA-G of the upper display substrate 200 according to an embodiment of the inventive concept.

Fig. 3A is an enlarged view of a portion of the display area DA shown in fig. 1A. In the figure, three types of pixel areas PXA-R, PXA-G and PXA-B are mainly shown. The three types of pixel areas PXA-R, PXA-G and PXA-B shown in fig. 3A may be repeatedly disposed in the entire display area DA.

The light-shielding area or peripheral area NPXA is disposed on the periphery of the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B. The light shielding area NPXA may be defined as a peripheral area. The light shielding area NPXA is disposed at the boundary of the first, second, and third pixel areas PXA-R, PXA-G, and PXA-B, and prevents color mixing among the first, second, and third pixel areas PXA-R, PXA-G, and PXA-B.

In the present embodiment, the first, second, and third pixel regions PXA-R, PXA-G, and PXA-B are shown to have the same planar area, but are not limited thereto. At least two of the first, second, and third pixel regions PXA-R, PXA-G, and PXA-B may be different in area. The first, second, and third pixel areas PXA-R, PXA-G, and PXA-B are illustrated in a plan view as having a rectangular shape with rounded corner areas, but are not limited thereto. The first, second, and third pixel areas PXA-R, PXA-G, and PXA-B may have another polygonal shape such as a diamond shape or a pentagonal shape in a plan view.

One of the first, second, and third pixel regions PXA-R, PXA-G, and PXA-B provides first color light corresponding to the source light, another provides second color light different from the first color light, and the remaining one provides third color light different from the first and second color light. In the present embodiment, the first pixel area PXA-R may provide red light, the second pixel area PXA-G may provide green light, and the third pixel area PXA-B may provide blue light.

The partition wall overlaps the light shielding region NPXA. First partition wall opening portions OP-R, second partition wall opening portions OP-G, and third partition wall opening portions OP-B corresponding to the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B, respectively, are defined in the partition walls.

Fig. 3B is a sectional view taken along line I-I' of fig. 3A. Fig. 3B illustrates a cross section of the display panel DP corresponding to the second pixel areas PXA-G. Fig. 3B exemplarily shows a cross section corresponding to the driving transistor T-D and the organic light emitting element (hereinafter, referred to as light emitting element) OLED. The upper display substrate 200 and the lower display substrate 100 may provide a predetermined gap GP.

As shown in fig. 3B, the lower display substrate 100 includes a first base substrate BS1, a circuit element layer DP-CL disposed on the first base substrate BS1, and a display element layer DP-OLED disposed on the circuit element layer DP-CL.

The first base substrate BS1 may include a synthetic resin substrate or a glass substrate. The circuit element layer DP-CL includes circuit elements and at least one insulating layer. The circuit elements include signal lines, driver circuits for pixels, and the like. The circuit element layer DP-CL may be formed by a process of providing an insulating layer, a semiconductor layer, and a conductive layer through coating, deposition, or the like, and a process of patterning the insulating layer, the semiconductor layer, and the conductive layer through a photolithography process.

In the present embodiment, the circuit element layer DP-CL may include the buffer layer BFL, the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The first and second insulating layers 10 and 20 may be inorganic layers, and the third insulating layer 30 may be an organic layer.

Fig. 3B exemplarily shows an arrangement relationship among the semiconductor pattern OSP, the control electrode GE, the input electrode DE, and the output electrode SE constituting the driving transistor T-D. Also shown as an example are a first via CH1, a second via CH2, and a third via CH 3.

The display element layer DP-OLED includes a light emitting element OLED. The light emitting element OLED may generate the source light described above. The light emitting element OLED includes a first electrode, a second electrode, and an emission layer interposed between the first electrode and the second electrode. In this embodiment, the display element layer DP-OLED may include an organic light emitting diode as a light emitting element. The display element layer DP-OLED includes a pixel defining layer PDL. For example, the pixel defining layer PDL may be an organic layer.

The first electrode AE is disposed on the third insulating layer 30. The first electrode AE is connected to the output electrode SE through a third via CH3 configured to penetrate through the third insulating layer 30. An opening portion OP is defined in the pixel defining layer PDL. The opening portion OP of the pixel defining layer PDL exposes at least a portion of the first electrode AE.

The hole control layer HCL, the emission layer EML, and the electron control layer ECL may be commonly disposed in the second pixel area PXA-G and the light-shielding area NPXA. The hole control layer HCL, the emission layer EML, and the electron control layer ECL may be commonly disposed in the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B (see fig. 3A).

The hole control layer HCL may include a hole transport layer, and may further include a hole injection layer. The emission layer EML may generate blue light. The blue light may include wavelengths of 410nm to 480 nm. The emission spectrum of blue light may have a maximum peak within 440nm to 460 nm. The electron control layer ECL may include an electron transport layer and may also include an electron injection layer.

The second electrode CE is disposed on the electron control layer ECL. The second electrode CE may be commonly disposed in the first, second, and third pixel areas PXA-R, PXA-G, and PXA-B. Therefore, the second electrode CE has an area larger than that of the first electrode AE. A capping layer CL configured to protect the second electrode CE may be further disposed on the second electrode CE. The capping layer CL may include an organic material or an inorganic material.

The lower display substrate 100 may include first, second, and third display elements corresponding to the first, second, and third pixel areas PXA-R, PXA-G, and PXA-B, respectively, as shown in fig. 3A. The stacked structures of the first display element, the second display element, and the third display element may be identical to each other, and have a stacked structure of the light emitting element OLED as shown in fig. 3B. However, the stacked structures of the first, second, and third display elements may be different from each other, for example, the emission layers EML in the first, second, and third display elements may emit different colors of light.

As shown in FIG. 3B, the upper display substrate 200 may include a second base substrate BS2, a light blocking pattern BM disposed on a bottom surface of the second base substrate BS2, a color filter CF-G, partition walls WP, and a color control layer CCF-G.

The second base substrate BS2 may include a synthetic resin substrate or a glass substrate. The light shielding pattern BM is disposed on the bottom surface of the second base substrate BS 2. The light-shielding pattern BM is disposed in the light-shielding region NPXA. Opening portions BM-OP corresponding to the first, second, and third pixel areas PXA-R, PXA-G, and PXA-B, respectively, are defined in the light shielding pattern BM. In the present embodiment, the second pixel area PXA-G is defined to correspond to the opening portion BM-OP of the light shielding pattern BM.

The color filter CF-G is disposed on the light-shielding pattern BM on the bottom surface of the second base substrate BS 2. The color filter CF-G includes a matrix resin and a dye and/or pigment dispersed in the matrix resin. The matrix resin is a material in which a dye and/or a pigment is dispersed, and may be composed of various resin compositions generally called binders. The color filter CF-G is stacked on the pixel area PXA-G. The edge area of the color filter CF-G may overlap the light-shielding area NPXA. A portion of the light blocking pattern BM may be disposed between the color filter CF-G and the bottom surface of the second base substrate BS 2.

With respect to fig. 3A and 3B, the first, second, and third color filters CF-R, CF-G, and CF-B are disposed to correspond to the first, second, and third pixel areas PXA-R, PXA-G, and PXA-B, respectively. The first, second, and third color filters CF-R, CF-G, and CF-B include dyes and/or pigments configured to absorb light of different wavelength bands. The first color filter CF-R may be a red color filter, the second color filter CF-G may be a green color filter, and the third color filter CF-B may be a blue color filter.

The first, second, and third color filters CF-R, CF-G, and CF-B reduce the reflection ratio of external light. Each of the first, second, and third color filters CF-R, CF-G, and CF-B transmits light in a specific wavelength range and absorbs or intercepts light having a wavelength other than a specific wavelength band. Each of the first, second, and third color filters CF-R, CF-G, and CF-B may absorb light having a wavelength other than a specific wavelength range.

The first encapsulation layer ENL1 is disposed on the color filter CF-G. The first encapsulation layer ENL1 encapsulates the color filter CF-G. The first encapsulation layer ENL1 may be commonly disposed in the first, second, and third pixel areas PXA-R, PXA-G, and PXA-B.

The first encapsulation layer ENL1 may include an inorganic layer. The first encapsulation layer ENL1 may include any one of silicon oxide, silicon nitride, and silicon oxynitride. The first encapsulation layer ENL1 may also include an organic layer configured to form a flat bottom surface.

The partition walls WP are disposed on the bottom surface of the first package layer ENL 1. The partition wall WP may completely overlap the light shielding pattern BM disposed on the light shielding region NPXA. The partition walls WP define first, second, and third inner areas (or first, second, and third inner spaces) corresponding to the first, second, and third pixel areas PXA-R, PXA-G, and PXA-B in fig. 3A, respectively.

The partition wall WP prevents the color control layers CCF-R, CCF-G and CCF-B from mixing among the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B in FIG. 3A when the color control layers CCF-R, CCF-G and CCF-B are formed.

The color control layer CCF-G is disposed inside the partition wall WP. In the present embodiment, the color control layer CCF-G may absorb the first color light generated by the light emitting element OLED and then generate other color light. The color control layer CCF-G may transmit or/and scatter the first color light.

The color control layer CCF-G may include a matrix resin and quantum dots mixed with (or dispersed in) the matrix resin. In the present embodiment, the color control layer CCF-G may be defined as a quantum dot layer. The matrix resin is a material or medium in which the quantum dots are dispersed, and may include various resins commonly referred to as binders. However, the matrix resin herein is not limited thereto, and in the present specification, a material in which the quantum dots may be uniformly dispersed may be referred to as a matrix resin regardless of its name, additional other functions, materials, and the like. The matrix resin may be a polymer resin. For example, the matrix resin may be an acrylic resin, a urethane resin, a silicone resin, an epoxy resin, or the like. The matrix resin may be a transparent resin.

Quantum dots may be particles configured to convert the wavelength of incident light. Quantum dots are materials having a crystal structure with a size of several nanometers, are composed of several hundreds to several thousands of atoms, and exhibit a quantum confinement effect in which an energy band gap is increased due to their small size. When light having a wavelength higher than the band gap is incident on the quantum dot, the quantum dot absorbs the light to become an excited state, and falls to a ground state while emitting light of a specific wavelength. The emitted light of a particular wavelength has a value corresponding to the band gap. When the size and composition of the quantum dot are adjusted, emission characteristics can be adjusted due to a quantum confinement effect.

The quantum dots may be selected from group II-VI compounds, group I-III-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof.

The II-VI compound may include one selected from the group consisting of: a binary compound selected from the group consisting of CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof; a ternary compound selected from the group consisting of AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; a quaternary compound selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, and mixtures thereof; and combinations thereof.

The group I-III-VI compound includes one selected from the group consisting of: ternary compound selected from the group consisting of AgInS₂、CuInS₂、AgGaS₂、CuGaS₂And mixtures thereof; a quaternary compound selected from the group consisting of AgInGaS₂、CuInGaS₂And mixtures thereof; and combinations thereof.

The III-V compound includes one selected from the group consisting of: a binary compound selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; a ternary compound selected from the group consisting of GaNP, GaNAs, GaNSb, GaGaAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb, and mixtures thereof; a quaternary compound selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, gainp, GaInNAs, gainsb, GaInPAs, GaInPSb, inalnnp, InAlNAs, InAlNSb, inaipas, InAlPSb, and mixtures thereof; and combinations thereof. Meanwhile, the III-V compound may further include a II group metal. For example, InZnP or the like can be selected as the group III-II-V compound.

The group IV-VI compound includes one selected from the group consisting of: a binary compound selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof; a ternary compound selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof; a quaternary compound selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof; and combinations thereof. The group IV element may be selected from the group consisting of Si, Ge and mixtures thereof. The group IV compound may be a binary compound selected from the group consisting of SiC, SiGe, and mixtures thereof.

Here, the binary compound, the ternary compound, or the quaternary compound may be present in the inside of the particle at a uniform concentration, or may be present in the inside of the same particle at a concentration distribution divided into locally different states.

The quantum dot may have a core-shell structure including a core and a shell surrounding the core. Furthermore, a core-shell structure may be possible in which one quantum dot surrounds another quantum dot. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the core.

The quantum dots may be particles having a nano-scale size. The quantum dot may have a full width at half maximum (FWHM) of an emission wavelength spectrum of about 45nm or less (preferably, about 40nm or less, more preferably, about 30nm or less), and in this range, color purity or color gamut may be improved. In addition, light emitted by such quantum dots is emitted in all directions, and thus a viewing angle can be improved.

Further, the type of the quantum dot is not particularly limited to one commonly used in the art, but more specifically, a type of spherical, pyramidal, multi-armed, or cubic nanoparticle, nanotube, nanowire, nanofiber, or nanoplanar particle, or the like may be used.

With respect to fig. 3A and 3B, the first color control layer CCF-R, the second color control layer CCF-G, and the third color control layer CCF-B are disposed to correspond to the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B. The first color control layer CCF-R absorbs blue light to produce red light and the second color control layer CCF-G absorbs blue light to produce green light. In other words, the first color control layer CCF-R and the second color control layer CCF-G may include quantum dots different from each other. The third color control layer CCF-B may transmit blue light.

The first, second and third color control layers CCF-R, CCF-G and CCF-B may also include scattering particles. The scattering particles may be titanium oxide (TiO)₂) Or silica-based nanoparticles, and the like.

The second encapsulation layer ENL2 is disposed on the partition wall WP and the color control layer CCF-G. The second encapsulation layer ENL2 encapsulates the partition wall WP and the color control layer CCF-G. The second encapsulation layer ENL2 may be commonly disposed in the first, second, and third pixel areas PXA-R, PXA-G, and PXA-B (see fig. 3A).

The second encapsulation layer ENL2 may include an inorganic layer configured to contact the partition wall WP and the color control layer CCF-G. The inorganic layer may include any one of silicon oxide, silicon nitride, and silicon oxynitride. The second encapsulation layer ENL2 may also include an organic layer disposed on the inorganic layer. The organic layer may form a flat bottom surface. The first encapsulation layer ENL1 may include silicon oxide, and the second encapsulation layer ENL2 may include silicon nitride.

The color control layer CCF-G shown in fig. 3B includes a matrix resin and quantum dots, and the weight% (weight percentage) of the quantum dots over the entire color control layer CCF-G is less than a reference value. When the weight% of the quantum dots is greater than the reference value, the bonding force of the color control layer CCF-G with the partition wall WP and the first encapsulation layer ENL1 is reduced, thereby causing defects.

In order to improve the photoelectric conversion efficiency, the weight of the quantum dot should be greater than a reference weight. By increasing the thickness of the color control layer CCF-G, the weight of the quantum dot can be adjusted to be greater than the reference weight. In the present embodiment, the thickness of the color control layer CCF-G may be 15 μm or more. The upper limit value of the thickness of the color control layer CCF-G is not particularly limited, but is formed to have a height lower than that of the partition walls WP.

The height of the partition wall WP may be higher than the height of each of the first color control layer CCF-R, the second color control layer CCF-G and the third color control layer CCF-B. The height of the color control layer CCF-G and the height of the partition wall WP are values measured on the third direction axis DR 3. The partition wall WP prevents different compositions from being mixed when the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B (see fig. 3A) are formed.

The partition wall WP may comprise two layers. The first layer WP1 may be disposed directly on the first package layer ENL 1. The second layer WP2 may be disposed directly on the first layer WP 1. The first layer WP1 and the second layer WP2 are formed by different processes and thus have boundaries. In cross-sectional view, a portion of the second layer WP2 protrudes downward from the first, second, and third color control layers CCF-R, CCF-G, and CCF-B.

The first layer WP1 and the second layer WP2 may have different materials. The first layer WP1 and the second layer WP2 may commonly include a matrix resin, a coupling agent, and a photoinitiator. The matrix resin may include various resins that may be commonly referred to as binders. The first layer WP1 and the second layer WP2 may further comprise a dispersant. Second layer WP2 may also include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof.

The first layer WP1 may not include a black colorant, or may include a black colorant having a lesser weight% compared to the second layer WP 2. Thus, the optical density of the second layer WP2 may have a value greater than or equal to the optical density of the first layer WP 1. In the present embodiment, the optical density of the second layer WP2 can be from about 0.15 to about 0.5 when the thickness of the second layer WP2 is 1 μm. The second layer WP2 may prevent the first color light generated in the light emitting element OLED from being incident on the adjacent pixel areas PXA-R and PXA-B (see fig. 3A).

Each of the first layer WP1 and the second layer WP2 may be formed through an exposure process and a development process. The partition walls WP collectively having an optical density of from about 0.2 to about 0.5 have a low transmittance, and therefore, when the thickness of the partition walls WP is thicker than a reference value, the exposure efficiency of light becomes lower. In the process of manufacturing the partition wall WP consisting of only the second layer WP2 having a thickness thicker than the reference value, the region adjacent to the first encapsulation layer ENL1 may be in an exposed state to cause defects.

In the present embodiment, the thickness of the second layer WP2 may be from about 5 μm to about 10 μm, so that exposure is sufficiently performed. The thickness of the first layer WP1 can be from about 5 μm to about 15 μm. Since the first layer WP1 has a lower optical density, the exposure efficiency of the first layer WP1 is high. Further, the exposure can be performed twice when forming the partition wall WP, defects in the partition wall WP can be reduced.

With respect to fig. 3C, the light shielding pattern BM may include a first light shielding layer BM1 and a second light shielding layer BM 2. The first light-shielding layer BM1 may be formed directly on the bottom surface of the second base substrate BS 2. The first light-shielding layer BM1 may include the same material as the blue color filter.

The second light-shielding layer BM2 may cover at least the bottom surface of the first light-shielding layer BM 1. As shown in fig. 3C, the second light-shielding layer BM2 may also cover the side surface of the first light-shielding layer BM 1.

The second light-shielding layer BM2 may be a typical black matrix. The second light-shielding layer BM2 has black color. The second light shielding layer BM2 may include a base resin and a black colorant mixed with the base resin. When the thickness of the second light-shielding layer BM2 is 1 μm, the optical density of the second light-shielding layer BM2 may be from about 1 to about 3.

Since the refractive index difference between the first light-shielding layer BM1 and the second base substrate BS2 is smaller than the refractive index difference between the second light-shielding layer BM2 and the second base substrate BS2, the first light-shielding layer BM1 having the same material as the blue color filter can reduce the reflection of external light.

Referring to fig. 3C, the first layer WP1 has a smaller width than the light shielding pattern BM. The width W1 of the first layer WP1 may be from about 10 μm to about 15 μm. The width W2 of the second layer WP2 may be less than the width W1 of the first layer WP 1. The width W2 of the second layer WP2 and the width W1 of the first layer WP1 are measured in the second direction DR 2. The second layer WP2 may completely overlap the first layer WP1 in plan view. The first layer WP1 may completely overlap the light shielding pattern BM in a plan view.

However, the embodiments of the inventive concept are not limited to the above numerical ranges. The width of the light shielding area NPXA may be differently set according to the resolution of the display panel, and the width W1 of the first layer WP1 may be wider or narrower than the above range.

The corner regions of the first layer WP1 are partially removed by the developer, and thus the corners may not be substantially defined in the first layer WP 1. FIG. 3C illustrates corner regions of the first layer WP1 described above. In cross-section, the corners may not be formed substantially in first layer WP 1. The chamfer is disposed in first layer WP 1.

With respect to FIG. 3C, the second layer WP2 may include two regions in cross-section having different properties. The second layer WP2 can include hydrophilic regions WP2-A1 and hydrophobic regions WP 2-A2.

Hydrophobic regions WP2-A2 are disposed farther away from first layer WP1 than hydrophilic regions WP 2-A1. Hydrophilic regions WP2-A1 are disposed between hydrophobic regions WP2-A2 and first layer WP 1. The hydrophobic regions WP2-A2 prevents the different color control layers CCF-R, CCF-G and CCF-B from mixing at the boundaries between the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B (see FIG. 3A).

The thickness of the second layer WP2, including hydrophilic regions WP2-A1 and hydrophobic regions WP2-A2, can be from about 7 μm to about 10 μm. The hydrophilic regions WP2-A1 may include a matrix resin and a black colorant mixed with the matrix resin. Hydrophobic region WP2-A2 may include a matrix resin and a hydrophobic agent chemically bonded to the matrix resin. The water repellent agent is phase separated in the process for providing the second layer WP2 and then densely concentrated on the bottom surface of the second layer WP 2. The thickness of hydrophobic region WP2-A2 can be from about 30nm to about 200 nm.

The hydrophobizing agent may include fluorine-based epoxy series materials and perfluoroether series system materials. Water repellents of the product names S-656, S-611, S-386 or S-243 of Asahi Kasei Corporation, the product name RS-56 or RS-76NS of DIC Corporation, the product name DAC-HP of Daikin industries (Daikin industries) or the product name FS-7024 of Fluorotech Corporation may be used to form the partition wall WP.

Fig. 4 is a flowchart illustrating a method of manufacturing the display panel DP according to an embodiment of the inventive concept. Fig. 5A to 5E illustrate a method of manufacturing the upper display substrate 200 according to an embodiment of the inventive concept. Hereinafter, detailed descriptions about the same components as those described with reference to fig. 1A to 3C will be omitted.

As shown in fig. 4, a first display substrate including first to third display elements is manufactured (operation S10). The first display substrate may be the lower display substrate 100, i.e., the array substrate, described with reference to fig. 1A to 3B. The first display substrate may be manufactured according to a typical manufacturing method.

In addition, a second display substrate is manufactured (operation S20). The order of manufacturing the first display substrate and the second display substrate is not particularly limited.

Then, the first display substrate and the second display substrate are combined (operation S30). An initial sealant is formed in the non-display area NDA (see fig. 1A) on one of the first display substrate and the second display substrate, and then the first display substrate may be combined with the second display substrate. After bonding, the initial encapsulant may be cured.

A method of manufacturing the second display substrate 200 will be described in more detail with reference to fig. 5A to 5E. Fig. 5A to 5E show cross sections corresponding to the drawings in fig. 3C.

As shown in fig. 5A, a light shielding pattern BM is formed on the second base substrate BS 2. In the present embodiment, the light shielding pattern BM may be formed by printing an inorganic material of a specific color on a specific region of the second base substrate BS 2. In the embodiments of the inventive concept, an organic layer of a specific color is formed on one surface of the second base substrate BS2, and then the organic layer is exposed and developed to form the first light-shielding layer BM 1.

After the first light-shielding layer BM1 is formed, the second light-shielding layer BM2 may be formed to form a light-shielding pattern BM having a double-layer structure. A second preliminary barrier rib layer may be formed, and then the second preliminary barrier rib layer may be exposed and developed to form the second light shielding layer BM 2.

As shown in FIG. 5B, color filters CF-R, CF-G and CF-B are formed on the second base substrate BS 2. In the present embodiment of the inventive concept, an organic layer having a predetermined color is formed on one surface of the second base substrate BS2, and then the organic layer is exposed and developed to form the color filters CF-R, CF-G and CF-B. In order to form three kinds of color filters, one cycle process of forming an organic layer, exposing the organic layer, and developing may be performed three times.

As shown in FIG. 5B, a first encapsulation layer ENL1 is formed on the color filters CF-R, CF-G and CF-B. Inorganic material is deposited to form a first encapsulation layer ENL 1.

As shown in fig. 5B, a first preliminary partition wall layer WPL1 is formed on the first encapsulation layer ENL 1. The first composition may be coated to form a first preliminary partition wall layer WPL 1. The first composition may include a base resin, a coupling agent, and a photoinitiator. The first composition may also include a black colorant. The first composition may also include a dispersant.

As shown in fig. 5B, the first preliminary partition wall layer WPL1 may be exposed such that the first region W-a1 overlapping the light blocking pattern BM is exposed to light. Since the first preliminary partition wall layer WPL1 exposed to light is not developed and the other portions of the first preliminary partition wall layer WPL1 are developed, the second region W-a2 may be surrounded by the first region W-a 1. The first preliminary partition wall layer WPL1 may be exposed using a first mask MSK1 formed with an opening area corresponding to the first region W-a 1.

Before the exposure, the second base substrate BS2 on which the first initial partition wall layer WPL1 is formed is set in a vacuum chamber to dry the first initial partition wall layer WPL 1. The dried first preliminary barrier wall layer WPL1 may be baked at a first temperature. The first temperature may be from about 90 ℃ to about 130 ℃. Then, the above exposure process may be performed.

As shown in fig. 5C, a second preliminary partition wall layer WPL2 is formed on the first preliminary partition wall layer WPL1 after exposure. The second preliminary partition wall layer WPL2 may be formed by coating with the second composition. The second composition may include a base resin, a coupling agent, and a photoinitiator. The second composition may also include a black colorant. The second composition may also include a dispersant. The wt% of the black colorant of the second composition may be greater than the wt% of the black colorant of the first composition.

As shown in fig. 5C, second preliminary partition wall layer WPL2 may be exposed such that third region W-a10 overlapping first region W-a1 of first preliminary partition wall layer WPL1 is exposed to light. Since the second preliminary partition wall layer WPL2 exposed to light is not developed, the third region W-a10 may surround the fourth region W-a20 disposed to overlap the second region W-a 2. The second preliminary partition wall layer WPL2 may be exposed using a second mask MSK2 formed with opening regions corresponding to the third regions W-a 10.

Using the second mask MSK2 including the third region W-a10 having a smaller width than the first region W-a1, the first layer WP1 may be prevented from being misaligned with the second layer WP2, which is caused by a process error. In other words, the second layer WP2 may completely overlap the first layer WP1 in plan view.

In an embodiment of the inventive concept, the second preliminary partition wall layer WPL2 may be exposed using the first mask MSK1 instead of the second mask MSK 2.

Before the exposure, the second base substrate BS2 on which the second initial partition wall layer WPL2 is formed may be set in a vacuum chamber to dry the second initial partition wall layer WPL 2. The dried second preliminary barrier wall layer WPL2 may be baked at a second temperature. The second temperature may be set higher than the first temperature. The second temperature may be from about 100 ℃ to about 140 ℃. Then, the above exposure process may be performed.

Although not shown in detail in fig. 5C, the third region W-a10 may include hydrophilic regions WP2-a1 (see fig. 3C) and hydrophobic regions WP2-a2 (see fig. 3C) disposed on the hydrophilic regions WP2-a1 in the third direction DR 3. The second composition may further comprise a hydrophobic agent. Phase separation occurs after the second preliminary partition wall layer WPL2 is applied. The water repellent agent is separated from the hydrophilic material and moves toward the top surface of the second initial partition wall layer WPL 2. Such phase separation is accelerated by the baking process at the second temperature.

In order to form the hydrophobic region WP2-a2 having a thickness of from about 30nm to about 200nm, a second initial partition wall layer WPL2 having a thickness of about 7 μm or more is formed. The maximum weight% of hydrophobizing agent is limited by the adverse effect of the hydrophobizing agent, which increases with increasing hydrophobizing agent. Therefore, in order to increase the water repellent agent included in the entire second initial partition wall layer WPL2, the second initial partition wall layer WPL2 is formed to have a thickness equal to or greater than a predetermined thickness.

The polymer and monomer of the second composition are polymerized during the exposure process, and the hydrophobic agent may also be chemically bound to the polymer and/or monomer. In this way, the hydrophobic region WP2-A2 is formed in a region adjacent to the top surface of the third region W-A10.

As shown in fig. 5D, first and second preliminary partition wall layers WPL1 and WPL2 may be developed to remove second and fourth areas W-a2 and W-a 20. The second area W-a2 and the fourth area W-a20 having the same base material can be developed in one development process by using the same developer.

After the developing process, the partition walls WP may be baked at a third temperature. The third temperature may be from about 200 ℃ to about 250 ℃. The partition walls WP are baked at a high temperature to increase the strength thereof.

Referring to fig. 5A through 5D, since second preliminary partition wall layer WPL2 is formed and then second preliminary partition wall layer WPL2 is exposed before first preliminary partition wall layer WPL1 is developed, first area W-a1 overlapping third area W-a10 may have a substantially flat surface.

As shown in fig. 5E, a second color control layer CCF-G is formed inside the second partition wall opening portion OP-G. The color control layers CCF-R, CCF-G and CCF-B are sequentially formed to correspond to the first partition wall opening portion OP-R, the second partition wall opening portion OP-G, and the third partition wall opening portion OP-B shown in fig. 3A, and hereinafter, a method of manufacturing one color control layer CCF-G will be described. A composition (hereinafter, color composition) for constituting the second color control layer CCF-G inside the second partition wall opening portions OP-G is formed.

The color composition may be formed inside the second partition wall opening portion OP-G using an inkjet process. The hydrophobic region WP2-A2 (see FIG. 3C) formed on the top surface of the partition wall WP prevents the color composition from being formed on the partition wall WP, thereby forming the color composition only in the second partition wall opening portion OP-G.

The color composition includes a matrix resin and quantum dots. The matrix resin may include an epoxy-based polymer and/or a monomer. The color composition may also include scattering particles. The color composition was dried under vacuum. Then, a first baking process and a second baking process are performed.

The first baking temperature may be from about 90 ℃ to about 130 ℃. The second baking temperature may be from about 180 ℃ to about 240 ℃. The color control layer can be uniformly dried by a two-step baking process.

Then, a second encapsulation layer ENL2 is formed on the color control layers CCF-R, CCF-G and CCF-B. An inorganic material is deposited to form an encapsulating inorganic layer. Organic materials may be deposited or coated to form an encapsulating organic layer.

Although not separately shown, at least one of processes for forming the color filter CF-G, the first encapsulation layer ENL1, and the second encapsulation layer ENL2 may be omitted.

Fig. 6A and 6B are diagrams illustrating a method of manufacturing an upper display substrate 200 according to an embodiment of the inventive concept.

Fig. 6A illustrates the second display substrate 200 after performing the process of fig. 5B and a developing process after the process of fig. 5B. The first layer WP1 of the partition wall WP is formed on the first package layer ENL 1.

Then, as shown in fig. 6B, a second initial partition wall layer WPL2 may be formed on the first encapsulation layer ENL1 and the first layer WP 1. Even when coating is performed such that the second composition has an upper surface as a dotted line, the second composition flows after it is coated due to the fluidity of the second composition to form an upper surface as a solid line. In order to form the second initial partition wall layer WPL2 having the thickness shown in fig. 5C, a larger amount of the second composition is required.

The second preliminary partition wall layer WPL2 is exposed to light using the second mask MSK2, and the fourth region W-a20 is removed by a developing process. In this process, a greater amount of the second composition is needed to form the second layer WP2 having the same thickness as disclosed in fig. 5A-5E.

Fig. 7A and 7B are cross-sectional views of a pixel region of an upper display substrate 200 according to an embodiment of the inventive concept. Hereinafter, detailed description about the same configuration as that described with respect to fig. 1A to 6B will be omitted.

As shown in fig. 7A, the first light-shielding layer BM1 and the second light-shielding layer BM2 may have the same width. After sequentially forming the first and second initial light-shielding layers, the first and second initial light-shielding layers may be patterned using a single exposure and a single development process. Alternatively, the first and second initial light-shielding layers may be sequentially exposed.

As shown in fig. 7B, a side surface of the first layer WP1 and a side surface of the second layer WP2 may be aligned along a substantially straight line. Compared to the first layer WP1 in fig. 3C, the first layer WP1 has an inclined portion toward one side of the second layer WP 2.

As described above, according to the embodiment, the color control layer may have a thickness greater than the reference value, and thus the amount of light changed in the color control layer increases. Therefore, the luminance of the display panel can be increased.

The light-shielding layer including the blue color filter and the black matrix may reduce the reflection amount of external light.

The partition wall may have a two-layer structure and thus have a thickness greater than a reference value. A second layer having a greater absorbance than the first layer is disposed adjacent to the lower display substrate, as compared to the first layer of the two-layer structure, to prevent color mixing between pixels.

Before the first initial partition wall layer is developed, a second initial partition wall layer is formed, and then the second initial partition wall layer is exposed to light. The developing process is simplified by developing the first initial barrier rib layer and the second initial barrier rib layer substantially simultaneously. The consumption of the composition for producing the second initial barrier wall layer can be reduced.

Although the present invention has been described with reference to the exemplary embodiments thereof, it will be apparent to those skilled in the art to which the present invention pertains that various changes and modifications may be made to the described embodiments without departing from the spirit and technical scope of the invention as defined in the appended claims and their equivalents.

Accordingly, the scope of the inventive concept should not be limited or restricted by the foregoing description, but should be determined by the broadest permissible interpretation of the following claims.