阅读说明：本技术 执行相位匹配操作的系统 (System for performing phase matching operations ) 是由 朴珉秀 朴民奎 崔谨镐 于 2020-07-31 设计创作，主要内容包括：用于执行相位匹配操作的系统包括控制器,该控制器被配置为输出时钟、命令和选通信号并且输入/输出数据。该系统还包括半导体器件,该半导体器件被配置为根据所述时钟通过对所述命令和选通信号的相位进行匹配来生成内部选通信号,并且同步于所述内部选通信号来输入/输出所述数据,其中,该半导体器件通过补偿输入所述命令的第一路径的延迟量和输入所述选通信号的第二路径的延迟量,从所述选通信号生成所述内部选通信号。(The system for performing the phase matching operation includes a controller configured to output clock, command and strobe signals and input/output data. The system further includes a semiconductor device configured to generate an internal strobe signal by matching phases of the command and strobe signals according to the clock, and input/output the data in synchronization with the internal strobe signal, wherein the semiconductor device generates the internal strobe signal from the strobe signal by compensating for a delay amount of a first path in which the command is input and a delay amount of a second path in which the strobe signal is input.)

1. A system for performing a phase matching operation, the system comprising:

a controller configured to: outputting clock, command and strobe signals, and inputting/outputting data; and

a semiconductor device configured to: and generating an internal strobe signal by matching phases of the command and the strobe signal according to the clock, and inputting/outputting the data in synchronization with the internal strobe signal, wherein the semiconductor device generates the internal strobe signal from the strobe signal by compensating for a delay amount of a first path to which the command is input and a delay amount of a second path to which the strobe signal is input.

2. The system of claim 1, wherein the semiconductor device is configured to generate the internal strobe signal by dividing a frequency of the strobe signal.

3. The system of claim 1, wherein the semiconductor device comprises:

a DLL circuit configured to generate a DLL clock by controlling a phase of the clock;

an input/output control circuit configured to: generating the internal strobe signal from the strobe signal by compensating for delay amounts of the first path and the second path according to the DLL clock;

a data input/output circuit configured to: generating internal data from the data in synchronization with the internal strobe signal during a write operation or generating the data from the internal data in synchronization with the internal strobe signal during a read operation; and

a core circuit configured to: the internal data is stored during the write operation, and the internal data stored in the core circuit is output during the read operation.

4. The system of claim 3, wherein the DLL circuit comprises:

a divided clock generation circuit configured to generate a divided clock by dividing a frequency of the clock;

a variable delay circuit configured to generate a delay signal by delaying the divided clock by a delay amount controlled by a delay control signal;

a replica delay circuit configured to generate a feedback clock by delaying the delay signal by a preset delay amount;

a delay control signal generation circuit configured to generate the delay control signal by comparing phases of the feedback clock and the clock; and

a DLL clock generation circuit configured to generate the DLL clock by delaying the delay signal.

5. The system of claim 3, wherein the input/output control circuit comprises:

a command control circuit configured to generate a data input control signal by delaying the command by a first delay amount in synchronization with the DLL clock;

an internal delay circuit configured to generate an input delay clock by delaying the DLL clock;

a strobe signal input circuit configured to generate a transmission strobe signal by delaying the strobe signal by a second delay amount in synchronization with the input delay clock;

a delay amount compensation circuit configured to generate a write delay signal by delaying the data input control signal by a third delay amount; and

a phase control circuit configured to generate the internal strobe signal by controlling a phase of the transmission strobe signal in synchronization with the write delay signal.

6. The system of claim 5, wherein the command control circuit is set to the first path and the strobe signal input circuit is set to the second path.

7. The system according to claim 5, wherein the third delay amount of the delay amount compensation circuit is set to a delay amount larger than the second delay amount.

8. The system of claim 5, wherein the command control circuit comprises:

a drive signal generation circuit configured to generate a drive signal from the command in synchronization with the DLL clock; and

a repeater configured to generate a data input control signal by delaying the driving signal by the first delay amount.

9. The system of claim 5, wherein the strobe signal input circuit comprises:

an input control circuit configured to generate an input strobe signal by delaying the strobe signal in synchronization with the input delay clock; and

a receiver configured to generate the transmission strobe signal by delaying the input strobe signal.

10. The system of claim 9, wherein a sum of delay amounts of the input control circuit and the receiver is set to the second delay amount.

11. A system for performing a phase matching operation, the system comprising:

a DLL circuit configured to generate a DLL clock by controlling a phase of a clock; and

an input/output control circuit configured to generate first, second, third, and fourth internal strobe signals by matching phases of a command and a strobe signal according to the DLL clock, wherein the input/output control circuit generates the first to fourth internal strobe signals from the strobe signal by compensating for a delay amount of a first path in which the command is input and a delay amount of a second path in which the strobe signal is input.

12. The system of claim 11, wherein the input/output control circuit is configured to generate the first through fourth internal strobe signals by dividing a phase of the strobe signal.

13. The system of claim 11, wherein the first through fourth internal strobe signals have different phases from each other.

14. The system of claim 11, wherein the DLL circuit comprises:

a divided clock generation circuit configured to generate a divided clock by dividing a frequency of a clock;

a variable delay circuit configured to generate a delay signal by delaying the divided clock by a delay amount controlled by a delay control signal;

a replica delay circuit configured to generate a feedback clock by delaying the delay signal by a preset delay amount;

a delay control signal generation circuit configured to generate the delay control signal by comparing phases of the feedback clock and the clock; and

a DLL clock generation circuit configured to generate the DLL clock by delaying the delay signal.

15. The system of claim 11, wherein the input/output control circuit comprises:

a command control circuit configured to generate a data input control signal by delaying the command by a first delay amount in synchronization with the DLL clock;

an internal delay circuit configured to generate an input delay clock by delaying the DLL clock;

a strobe signal input circuit configured to generate a transmission strobe signal by delaying the strobe signal by a second delay amount in synchronization with the input delay clock;

a delay amount compensation circuit configured to generate a write delay signal by delaying the data input control signal by a third delay amount; and

a phase control circuit configured to generate the internal strobe signal by controlling a phase of the transmission strobe signal in synchronization with the write delay signal.

16. The system of claim 15, wherein the command control circuit is set to the first path and the strobe signal input circuit is set to the second path.

17. The system according to claim 15, wherein the third delay amount of the delay amount compensation circuit is set to a delay amount larger than the second delay amount.

18. The system of claim 15, wherein the command control circuit comprises:

a drive signal generation circuit configured to generate a drive signal from the command in synchronization with the DLL clock; and

a repeater configured to generate a data input control signal by delaying the driving signal by the first delay amount.

19. The system of claim 15, wherein the strobe signal input circuit comprises:

an input control circuit configured to generate an input strobe signal by delaying the strobe signal in synchronization with the input delay clock; and

a receiver configured to generate the transmission strobe signal by delaying the input strobe signal.

20. The system of claim 19, wherein a sum of delay amounts of the input control circuit and the receiver is set to the second delay amount.

Technical Field

Embodiments of the present disclosure relate to a system for matching phases of a command and a strobe signal in synchronization with a clock by compensating for delay amounts of paths in which the command and the strobe signal are input.

Background

Recently, as the operating speed of semiconductor systems increases, high transfer rates are required between semiconductor devices included in the semiconductor systems. In order to satisfy a high transmission rate or a high bandwidth for data serially input/output between semiconductor devices, a new technique is applied. For example, clock division techniques are used for high-speed input/output data. When the clock is divided, multiphase clocks having different phases are generated. The multiphase clock is used to deserialize or serialize data for high speed input/output of data.

Disclosure of Invention

Various embodiments are directed to a system for performing a phase matching operation that: using a DLL (delay locked loop) clock, phases of a strobe signal and a command synchronized with the clock are matched in synchronization with the clock by compensating for as many delay amounts as a path of the command and a path of the strobe signal are input.

Further, various embodiments are directed to a system for performing a phase matching operation, which performs a data input/output operation by matching phases of a strobe signal and a command in synchronization with a clock.

In one embodiment, a system for performing phase matching operations may include a controller configured to: outputs clock, command and strobe signals, and inputs/outputs data. The system may also include a semiconductor device configured to: generating an internal strobe signal by matching phases of the command and the strobe signal according to the clock, and inputting/outputting the data in synchronization with the internal strobe signal, wherein the semiconductor device generates the internal strobe signal from the strobe signal by compensating for a delay amount of a first path to which the command is input and a delay amount of a second path to which the strobe signal is input.

In one embodiment, a system for performing phase matching operations may include a DLL circuit configured to generate a DLL clock by controlling a phase of a clock. The system may further include an input/output control circuit configured to generate first, second, third, and fourth internal strobe signals by matching phases of a command and a strobe signal according to the DLL clock, wherein the input/output control circuit generates the first to fourth internal strobe signals from the strobe signal by compensating for a delay amount of a first path in which the command is input and a delay amount of a second path in which the strobe signal is input.

According to the present embodiment, using the DLL clock, it is possible to match the phases of the strobe signal and the command in synchronization with the clock by compensating for the delay amount of the first path to which the command synchronized with the clock is input and the delay amount of the second path to which the strobe signal is input.

Further, since a data input/output operation is performed by matching the phases of the strobe signal and the command in synchronization with the clock, an error of the data input/output operation can be prevented.

Drawings

Fig. 1 is a block diagram showing a configuration of a system for performing a phase matching operation according to an embodiment.

Fig. 2 is a block diagram showing a configuration of a semiconductor device included in the system for performing the phase matching operation shown in fig. 1.

Fig. 3 is a block diagram showing a configuration of a DLL (delay locked loop) circuit included in the semiconductor device shown in fig. 2.

Fig. 4 is a timing diagram for describing the operation of the DLL circuit shown in fig. 3.

Fig. 5 is a block diagram showing a configuration of an input/output control circuit included in the semiconductor device shown in fig. 2.

Fig. 6 is a block diagram showing a configuration of a command control circuit included in the input/output control circuit shown in fig. 5.

Fig. 7 is a block diagram showing a configuration of a strobe signal input circuit included in the input/output control circuit shown in fig. 5.

Fig. 8 is a circuit diagram showing a configuration of a delay amount compensation circuit included in the input/output control circuit shown in fig. 5.

Fig. 9 is a timing diagram for describing a phase matching operation of the system for performing the phase matching operation according to the embodiment.

Fig. 10 is a timing diagram for describing a data input/output operation of the system for performing the phase matching operation according to the embodiment.

Fig. 11 is a diagram showing a configuration of an electronic system to which the system for performing the phase matching operation shown in fig. 1 to 10 is applied according to an embodiment.

Detailed Description

The term "preset" means: when a parameter is used in a process or algorithm, the value of the parameter is predetermined. According to various embodiments, the value of the parameter may be set before or at the beginning of the process or algorithm, or while the process or algorithm is being performed.

Terms such as "first" and "second" used to distinguish between various components are not limited by the components. For example, a first component can be referred to as a second component and vice versa. Terms such as "first" and "second" are not meant to imply a particular number or order of components unless otherwise stated.

When one component is referred to as being "coupled" or "connected" to another component, it may mean that the components are directly coupled or connected to each other or are coupled or connected to each other through another component interposed therebetween. On the other hand, when one component is referred to as being "directly coupled" or "directly connected" to another component, this may mean that the components are directly coupled or connected to each other with other components interposed therebetween.

"logic high level" and "logic low level" are used to describe the logic levels of a signal. A signal having a "logic high level" is distinguished from a signal having a "logic low level". For example, when the signal having the first voltage corresponds to a "logic high level", the signal having the second voltage may correspond to a "logic low level". According to one embodiment, the "logic high level" may be set to a voltage higher than the "logic low level". Depending on the embodiment, the logic levels of the signals may be set to different logic levels or opposite logic levels. For example, according to an embodiment, a signal having a logic high level may be set to have a logic low level, and, according to an embodiment, a signal having a logic low level may be set to have a logic high level.

Hereinafter, the present disclosure will be described in more detail by examples. The examples are merely illustrative of the present disclosure, and the scope of the present disclosure is not limited by the examples.

As shown in fig. 1, a system 1 for performing a phase matching operation according to an embodiment may include a controller 10 and a semiconductor device 20. The semiconductor device 20 may include a DLL (delay locked loop) circuit 100, an input/output control circuit 200, a data input/output circuit 300, and a core circuit 400.

The controller 10 may include a first control pin 11, a second control pin 31, a third control pin 51, and a fourth control pin 71. The semiconductor device 20 may include a first semiconductor pin 21, a second semiconductor pin 41, a third semiconductor pin 61, and a fourth semiconductor pin 81. The first transmission line L11 may be coupled between the first control pin 11 and the first semiconductor pin 21. The second transmission line L31 may be coupled between the second control pin 31 and the second semiconductor pin 41. The third transmission line L51 may be coupled between the third control pin 51 and the third semiconductor pin 61. The fourth transmission line L71 may be coupled between the fourth control pin 71 and the fourth semiconductor pin 81. To control the semiconductor device 20, the controller 10 may transmit the clock CLK to the semiconductor device 20 through the first transmission line L11. To control the semiconductor device 20, the controller 10 may send a command CMD to the semiconductor device 20 through the second transmission line L31. To control the semiconductor device 20, the controller 10 may transmit the strobe signal DQS to the semiconductor device 20 through the third transmission line L51. The controller 10 and the semiconductor device 20 may transmit and receive DATA through the fourth transmission line L71.

The controller 10 may output a clock CLK, a command CMD, a strobe signal DQS, and DATA to the semiconductor device 20 to perform a write operation. The controller 10 may control the semiconductor device 20 to perform a phase matching operation for compensating a phase difference between the strobe signal DQS and the command CMD synchronized with the clock CLK during the write operation. According to an embodiment, the controller 10 according to the present embodiment may be implemented to output a clock CLK, a command CMD, and a strobe signal DQS to the semiconductor device 20 to perform a read operation and receive DATA from the semiconductor device 20. The command CMD may be sequentially output in synchronization with the odd or even pulses included in the clock CLK. The strobe signal DQS may be set to a signal that triggers (toggle) data input/output operations regardless of the clock CLK.

The DLL circuit 100 may generate a DLL clock (DLL _ CLK of fig. 2) by controlling a phase of the clock CLK. The DLL circuit 100 may generate a DLL clock (DLL _ CLK of fig. 2) by controlling the phase of the clock CLK such that the phase of the clock CLK is suitable for an internal operation of the semiconductor device 20.

The input/output control circuit 200 may generate a first internal strobe signal (IDQS 1 of fig. 2), a second internal strobe signal (IDQS 2 of fig. 2), a third internal strobe signal (IDQS 3 of fig. 2), and a fourth internal strobe signal (IDQS 4 of fig. 2) from the strobe signal DQS according to a DLL clock (DLL _ CLK of fig. 2).

The DATA input/output circuit 300 may generate the internal DATA (ID <1: N > of fig. 2) from the DATA in synchronization with the first internal strobe signal (IDQS 1 of fig. 2), the second internal strobe signal (IDQS 2 of fig. 2), the third internal strobe signal (IDQS 3 of fig. 2), and the fourth internal strobe signal (IDQS 4 of fig. 2) during a write operation. The DATA input/output circuit 300 may generate the DATA from the internal DATA (ID <1: N > of fig. 2) in synchronization with the first internal strobe signal (IDQS 1 of fig. 2), the second internal strobe signal (IDQS 2 of fig. 2), the third internal strobe signal (IDQS 3 of fig. 2), and the fourth internal strobe signal (IDQS 4 of fig. 2) during a read operation.

The core circuit 400 may store internal data (ID <1: N > of FIG. 2) during a write operation. The core circuit 400 may output the internal data stored therein (ID <1: N > of fig. 2) during a read operation.

Fig. 2 is a block diagram showing the configuration of the semiconductor device 20 according to the embodiment. As shown in fig. 2, the semiconductor device 20 may include a DLL circuit 100, an input/output control circuit 200, a data input/output circuit 300, and a core circuit 400.

The DLL circuit 100 may generate a DLL clock DLL _ CLK by controlling a phase of the clock CLK. The DLL circuit 100 may generate a DLL clock DLL _ CLK by controlling the phase of the clock CLK such that the phase of the clock CLK is suitable for internal operations of the semiconductor device 20. The DLL circuit 100 may control a delay amount for adjusting a position of an edge of the clock CLK so that a phase of the clock CLK is suitable for an internal operation of the semiconductor device 20. The DLL circuit 100 may generate a DLL clock DLL _ CLK by delaying the clock CLK by a controlled delay amount. The DLL circuit 100 may be implemented as a conventional DLL circuit for controlling the phase of the clock CLK.

The input/output control circuit 200 may generate the first to fourth internal strobe signals IDQS1 to IDQS4 by dividing the frequency of the strobe signal DQS. The input/output control circuit 200 may generate the first to fourth internal strobe signals IDQS1 to IDQS4 from the strobe signal DQS according to a DLL clock DLL _ CLK. The input/output control circuit 200 may generate the first to fourth internal strobe signals IDQS1 to IDQS4 from the strobe signal DQS by compensating for a delay amount of a first path of the input command CMD and a delay amount of a second path of the input strobe signal DQS according to the DLL clock DLL _ CLK. The first path and the second path will be described in detail with reference to the drawings to be described.

The DATA input/output circuit 300 may generate the internal DATA ID <1: N > from the DATA DATA <1: N > in synchronization with the first through fourth internal strobe signals IDQS1 through IDQS4 during a write operation. The DATA input/output circuit 300 may generate the DATA <1: N > from the internal DATA ID <1: N > in synchronization with the first through fourth internal strobe signals IDQS1 through IDQS4 during a read operation. According to an embodiment, the number of bits N contained in each of the DATA DATA <1: N > and the internal DATA ID <1: N > may be set to various values.

Core circuit 400 may store internal data ID <1: N > during a write operation. The core circuit 400 may output the internal data ID <1: N > stored therein during a read operation.

Fig. 3 is a block diagram showing the configuration of the DLL circuit 100 according to the embodiment. As shown in fig. 3, the DLL circuit 100 may include a division clock generating circuit 110, a variable delay circuit 120, a replica delay circuit 130, a delay control signal generating circuit 140, and a DLL clock generating circuit 150.

The divided clock generation circuit 110 may generate the divided clock DCLK by dividing the frequency of the clock CLK. The divided clock generation circuit 110 may generate the divided clock DCLK having a frequency corresponding to 1/2 of the frequency of the clock CLK. The divided clock generation circuit 110 may be set to have the first delay time tD 1. The first delay time tD1 may be set as an internal delay time of the divided clock generation circuit 110.

The variable delay circuit 120 may generate the delay signal DLY by delaying the divided clock DCLK. The variable delay circuit 120 may generate the delay signal DLY by delaying the divided clock DCLK by a delay amount controlled by the delay control signal DLY _ CTR. When the delay control signal DLY _ CTR is disabled, the variable delay circuit 120 may generate the delay signal DLY by delaying the divided clock DCLK by a fixed delay amount. When the delay control signal DLY _ CTR is enabled, the variable delay circuit 120 may generate the delay signal DLY by delaying the divided clock DCLK by a delay amount, which is controlled when increasing or decreasing. According to an embodiment, the delay amount of the variable delay circuit 120 may be set to various values. The variable delay circuit 120 may be set to have the second delay time tD 2. The second delay time tD2 may be set as an internal delay time of the variable delay circuit 120.

The replica delay circuit 130 may generate the feedback clock FCLK by delaying the delay signal DLY by a preset delay amount. The replica delay circuit 130 may generate the feedback clock FCLK by delaying the delay signal DLY so that the delay signal DLY is suitable for an internal operation of the semiconductor device 20. The replica delay circuit 130 may be implemented as a conventional replica delay circuit having a delay amount set to the same amount as the internal operation of the semiconductor device 20. According to an embodiment, the delay amount of the replica delay circuit 130 may be set to various values.

The delay control signal generation circuit 140 may generate the delay control signal DLY _ CTR by detecting the phase of the feedback clock FCLK. The delay control signal generation circuit 140 may generate the delay control signal DLY _ CTR by comparing the phases of the feedback clock FCLK and the clock CLK. When the feedback clock FCLK and the clock CLK are in phase, the delay control signal generation circuit 140 may generate the disabled delay control signal DLY _ CTR. When the feedback clock FCLK and the clock CLK are out of phase, the delay control signal generation circuit 140 may generate the enabled delay control signal DLY _ CTR. When the feedback clock FCLK is generated to have a phase suitable for the internal operation of the semiconductor device 20, the delay control signal generation circuit 140 may generate the disabled delay control signal DLY _ CTR. When the phase of the feedback clock FCLK is not suitable for the internal operation of the semiconductor device 20, the delay control signal generation circuit 140 may generate the enabled delay control signal DLY _ CTR.

The DLL clock generating circuit 150 may output the delay signal DLY as a DLL clock DLL _ CLK. The DLL clock generating circuit 150 may generate a DLL clock DLL _ CLK by delaying the delay signal DLY. The DLL clock generating circuit 150 may be set to have the third delay time tD 3. The third delay time tD3 may be set as an internal delay time of the DLL clock generating circuit 150.

Referring to fig. 4, the operation of the DLL circuit 100 according to the present embodiment will be described below.

At a time point T2, the divided clock generation circuit 110 generates the divided clock DCLK from the clock CLK triggered at the time point T1. The divided clock generation circuit 110 generates the divided clock DCLK by dividing the frequency of the clock CLK. The divided clock DCLK is generated to have a frequency corresponding to 1/2 of the frequency of the clock CLK. The divided clock generation circuit 110 generates a divided clock DCLK including a pulse generated at a time point T2 when the first delay time tD1 has elapsed from the time point T1.

At a time point T3, the variable delay circuit 120 generates the delay signal DLY by delaying the divided clock DCLK of the time point T2. The variable delay circuit 120 generates a delay signal DLY including a pulse that is initially generated at a time point T3 when a second delay time tD2 has elapsed from the time point T2 by delaying the divided clock DCLK by a delay amount controlled by a delay control signal DLY _ CTR.

At a time point T4, the DLL clock generating circuit 150 generates a DLL clock DLL _ CLK by delaying the delay signal DLY of the time point T3. The DLL clock generating circuit 150 generates a DLL clock DLL _ CLK including a pulse generated at a time point T4 when a third delay time tD3 elapses from the time point T3.

At a time point T5, the replica delay circuit 130 generates the feedback clock FCLK by delaying the delay signal DLY by a preset delay amount. The replica delay circuit 130 generates the feedback clock FCLK by delaying the delay signal DLY at the time point T3 by a preset delay amount.

When the feedback clock FCLK is generated to have a phase suitable for the internal operation of the semiconductor device 20, the delay control signal generation circuit 140 generates the disabled delay control signal DLY _ CTR. When the phase of the feedback clock FCLK is not suitable for the internal operation of the semiconductor device 20, the delay control signal generation circuit 140 generates the enabled delay control signal DLY _ CTR.

The DLL circuit 100 according to the present embodiment may generate the DLL clock DLL _ CLK by controlling the phase of the clock CLK such that the phase of the clock CLK is suitable for the internal operation of the semiconductor device 20. The DLL circuit 100 may generate a DLL clock DLL _ CLK by dividing the frequency of the clock CLK. The DLL circuit 100 may generate a DLL clock DLL _ CLK having a frequency corresponding to 1/2 of the frequency of the clock CLK.

Fig. 5 is a block diagram showing the configuration of the input/output control circuit 200 according to the embodiment. As shown in fig. 5, the input/output control circuit 200 may include a command control circuit 210, an internal delay circuit 220, a strobe signal input circuit 230, a delay amount compensation circuit 240, and a phase control circuit 250.

The command control circuit 210 may generate the data input control signal DINEN by delaying the command CMD in synchronization with the DLL clock DLL _ CLK. The command control circuit 210 may generate the data input control signal DINEN by delaying the command CMD by a first delay amount in synchronization with the DLL clock DLL _ CLK. The first delay amount may be set to a delay amount of the first path of the input command CMD. The first path may be set as the command control circuit 210 to which the command CMD is input.

The internal delay circuit 220 may generate the input delay clock IDLL by delaying the DLL clock DLL _ CLK. According to an embodiment, the delay amount of the internal delay circuit 220 may be set to various values.

The strobe signal input circuit 230 may receive the strobe signal DQS in synchronization with the input delay clock IDLL and generate the transmission strobe signal TDQS. The strobe signal input circuit 230 may generate the transmission strobe signal TDQS by delaying the strobe signal DQS by a second delay amount in synchronization with the input delay clock IDLL. The second delay amount may be set to a delay amount of the second path of the input strobe signal DQS. The second path may be set as the strobe signal input circuit 230 to which the strobe signal DQS is input.

The delay amount compensation circuit 240 may generate the write delay signal WTD by delaying the data input control signal DINEN by a third delay amount. The third delay amount may be set to a delay amount larger than the second delay amount.

The phase control circuit 250 may generate the first to fourth internal strobe signals IDQS1 to IDQS4 by controlling the phase of the transmission strobe signal TDQS in synchronization with the write delay signal WTD. The phase control circuit 250 may generate the first to fourth internal strobe signals IDQS1 to IDQS4 by shifting the transmission strobe signal TDQS in synchronization with the write delay signal WTD. The first to fourth internal strobe signals IDQS1 to IDQS4 have a phase difference of 90 ° set therebetween. The 90 ° phase difference may be set to 1/4 cycles of the transmission strobe signal TDQS.

Fig. 6 is a block diagram showing the configuration of the command control circuit 210 according to the embodiment. As shown in fig. 6, the command control circuit 210 may include a driving signal generating circuit 211 and a repeater (repeater) 212.

The driving signal generation circuit 211 may generate the driving signal DRV from the command CMD in synchronization with the DLL clock DLL _ CLK. The driving signal generation circuit 211 may latch the command CMD in synchronization with an edge of the DLL clock DLL _ CLK. The drive signal generation circuit 211 may output the command CMD latched in synchronization with the edge of the DLL clock DLL _ CLK as the drive signal DRV.

The repeater 212 may generate the data input control signal DINEN by buffering the driving signal DRV. The repeater 212 may generate the data input control signal DINEN by delaying the driving signal DRV by a first delay amount a. The first delay amount a will be described in detail with reference to fig. 9 which will be described below.

Fig. 7 is a block diagram illustrating a configuration of the gate signal input circuit 230 according to the embodiment. As shown in fig. 7, the gate signal input circuit 230 may include an input control circuit 231 and a receiver 232.

The input control circuit 231 may generate the input strobe signal DDQS by delaying the strobe signal DQS in synchronization with the input delay clock IDLL. The input control circuit 231 may receive the strobe signal DQS in synchronization with an edge of the input delay clock IDLL. The input control circuit 231 may output the strobe signal DQS, which is received in synchronization with an edge of the input delay clock IDLL, as the input strobe signal DDQS.

Receiver 232 may generate the transmission strobe signal TDQS by buffering the input strobe signal DDQS. Receiver 232 may generate the transmission strobe signal TDQS by delaying the input strobe signal DDQS.

The delay amount of the input control circuit 231 and the receiver 232 may be set to the second delay amount B. The second delay amount B will be described in detail with reference to fig. 9 which will be described below.

Fig. 8 is a circuit diagram showing the configuration of the delay amount compensation circuit 240 according to the embodiment. As shown in fig. 8, the delay amount compensating circuit 240 may be implemented as an inverter chain in which a plurality of inverters IV21 through IV24 are coupled in series.

The delay amount compensation circuit 240 may generate the write delay signal WTD by delaying the data input control signal DINEN by the third delay amount X. The third delay amount X may be set to a delay amount larger than the second delay amount B. According to the embodiment, the number of inverters for setting the third delay amount X may be set to various values.

Referring to fig. 9, the phase matching operation of the system according to the present embodiment will be described below.

At a time point T11, the controller 10 may output a clock CLK, a command CMD, and DATA <1: N > to the semiconductor device 20 to perform a write operation.

At a time point T12, the DLL circuit 100 generates a DLL clock DLL _ CLK by dividing the frequency of the clock CLK input at a time point T11. The DLL circuit 100 generates a DLL clock DLL _ CLK having a frequency corresponding to 1/2 of the frequency of the clock CLK.

At a time point T13, the drive signal generation circuit 211 generates the drive signal DRV from the command CMD input at a time point T11 in synchronization with the DLL clock DLL _ CLK.

At a time point T14, the repeater 212 generates the data input control signal DINEN by delaying the driving signal DRV generated at the time point T13. The repeater 212 generates the data input control signal DINEN by buffering the driving signal DRV generated at the time point T13 by the first delay amount a. The first delay amount a is set to a time interval from a time point T13 to a time point T14.

At one point of time, the controller 10 outputs a strobe signal DQS for performing a write operation to the semiconductor device 20.

At a time point T16, the strobe signal input circuit 230 generates the transmission strobe signal TDQS by delaying the strobe signal DQS input at a time point T15. The strobe signal input circuit 230 generates the transmission strobe signal TDQS by delaying the strobe signal DQS input at a time point T15 by the second delay amount B. The second delay amount B is set to a time interval from a time point T15 to a time point T16.

The delay amount compensation circuit 240 generates the write delay signal WTD by delaying the data input control signal DINEN generated at the time point T14. The delay amount compensation circuit 240 generates the write delay signal WTD by delaying the data input control signal DINEN generated at the time point T14 by the third delay amount X.

The system for performing the phase matching operation according to the present embodiment can match the phases of the strobe signal and the clock-synchronized command by compensating as many delay amounts as a first path, in which the clock-synchronized command is input, and a second path, in which the strobe signal is input, using the DLL clock.

Referring to fig. 10, a data input/output operation of the system according to the present embodiment will be described. In the following description, a write operation will be taken as an example.

At a time point T21, the strobe signal input circuit 230 generates the transmission strobe signal TDQS by delaying the input strobe signal DQS.

The delay amount compensation circuit 240 generates the write delay signal WTD by delaying the data input control signal DINEN. Since the operation of generating the transmission strobe signal TDQS and the write delay signal WTD has been described with reference to fig. 9, a detailed description thereof will be omitted herein.

The phase control circuit 250 generates the first internal strobe signal IDQS1 by controlling the phase of the transmission strobe signal TDQS in synchronization with the write delay signal WTD.

The DATA input/output circuit 300 generates the first internal DATA ID <1> from the first DATA <1> in synchronization with the first internal strobe signal IDQS 1.

The core circuit 400 stores the first internal data ID <1 >.

At a time point T22, the phase control circuit 250 generates the second internal strobe signal IDQS2 by controlling the phase of the transmission strobe signal TDQS.

The DATA input/output circuit 300 generates the second internal DATA ID <2> from the second DATA <2> in synchronization with the second internal strobe signal IDQS 2.

The core circuit 400 stores the second internal data ID <2 >.

At a time point T23, the phase control circuit 250 generates the third internal strobe signal IDQS3 by controlling the phase of the transmission strobe signal TDQS.

The DATA input/output circuit 300 generates the third internal DATA ID <3> from the third DATA <3> in synchronization with the third internal strobe signal IDQS 3.

The core circuit 400 stores the third internal data ID <3 >.

At a time point T24, the phase control circuit 250 generates the fourth internal strobe signal IDQS4 by controlling the phase of the transmission strobe signal TDQS.

The DATA input/output circuit 300 generates the fourth internal DATA ID <4> from the fourth DATA <4> in synchronization with the fourth internal strobe signal IDQS 4.

The core circuit 400 stores the fourth internal data ID <4 >.

At a time point T25, the phase control circuit 250 generates the first internal strobe signal IDQS1 by controlling the phase of the transmission strobe signal TDQS.

The DATA input/output circuit 300 generates the fifth internal DATA ID <5> from the fifth DATA <5> in synchronization with the first internal strobe signal IDQS 1.

The core circuit 400 stores fifth internal data ID <5 >.

At a time point T26, the phase control circuit 250 generates the second internal strobe signal IDQS2 by controlling the phase of the transmission strobe signal TDQS.

The DATA input/output circuit 300 generates the sixth internal DATA ID <6> from the sixth DATA <6> in synchronization with the second internal strobe signal IDQS 2.

The core circuit 400 stores the sixth internal data ID <6 >.

At a time point T27, the phase control circuit 250 generates the third internal strobe signal IDQS3 by controlling the phase of the transmission strobe signal TDQS.

The DATA input/output circuit 300 generates the seventh internal DATA ID <7> from the seventh DATA <7> in synchronization with the third internal strobe signal IDQS 3.

The core circuit 400 stores the seventh internal data ID <7 >.

At a time point T28, the phase control circuit 250 generates the fourth internal strobe signal IDQS4 by controlling the phase of the transmission strobe signal TDQS.

The DATA input/output circuit 300 generates the eighth internal DATA ID <8> from the eighth DATA <8> in synchronization with the fourth internal strobe signal IDQS 4.

The core circuit 400 stores the eighth internal data ID <8 >.

The core circuit 400 is implemented to sequentially store the first to eighth internal data ID <1:8> from a time point T21 to a time point T28. However, the core circuit 400 may be implemented as the first to eighth internal data ID <1:8> stored at a time after the first to eighth internal data ID <1:8> are all generated.

Then, the write operation is performed in the same manner as the above-described operation. Therefore, a detailed description thereof is omitted here.

The system for performing the phase matching operation according to the present embodiment can perform the data input/output operation by matching the phases of the strobe signal and the command in synchronization with the clock, thereby preventing an error of the data input/output operation.

Fig. 11 is a block diagram illustrating a configuration of an electronic system 1000 according to an embodiment. As shown in fig. 11, the electronic system 1000 may include a host 1100 and a semiconductor system 1200.

The host 1100 and the semiconductor system 1200 may transmit/receive signals to/from each other using an interface protocol. Examples of the interface protocol used between the host 1100 and the semiconductor system 1200 may include MMC (multimedia card), ESDI (enhanced small disk interface), IDE (integrated drive electronics), PCI-E (peripheral component interconnect-express), ATA (advanced technology attachment), SATA (serial ATA), PATA (parallel ATA), SAS (serial attached SCSI), USB (universal serial bus), and the like.

The semiconductor system 1200 may include a controller 1300 and a semiconductor device 1400(K: 1). The controller 1300 may control the semiconductor device 1400(K:1) to perform a phase matching operation during a write operation. The controller 1300 may control the semiconductor device 1400(K:1) to perform a data input/output operation during a write operation. During the write operation, each semiconductor device 1400(K:1) may match the phases of the strobe signal and the command in synchronization with the clock by compensating for as many delay amounts as a first path to which the command synchronized with the clock is input and a second path to which the strobe signal is input using the DLL clock. In addition, each semiconductor device 1400(K:1) can perform a data input/output operation by matching the phases of the strobe signal and the command in synchronization with the clock, thereby preventing an error of the data input/output operation.

The controller 1300 may be implemented as the controller 10 shown in fig. 1. Each semiconductor device 1400(K:1) may be implemented as the semiconductor device 20 shown in fig. 1. According to one embodiment, the semiconductor device 20 may be implemented as one of DRAM (dynamic random access memory), PRAM (phase change random access memory), RRAM (resistive random access memory), MRAM (magnetic random access memory), and FRAM (ferroelectric random access memory).

For illustrative purposes, a limited number of possible embodiments of the present disclosure have been disclosed. Those skilled in the art will appreciate that various modifications, additions and/or substitutions are possible, without departing from the scope and spirit of the disclosure as disclosed in the accompanying claims.