阅读说明：本技术 一种中断处理方法、系统及计算机可读存储介质 (Interrupt processing method, system and computer readable storage medium ) 是由 郭晖 张楠赓 于 2018-08-21 设计创作，主要内容包括：本发明的实施方式提供了一种中断处理方法、系统及计算机可读存储介质,适用于基于RISC-V指令集架构的系统,所述方法包括：将正在执行的第一中断的优先级设为中断优先级阈值；打开处理器核心的全局中断使能；接收第二中断,判断所述第二中断的优先级是否超过所述中断优先级阈值；若所述第二中断的优先级超过所述中断优先级阈值,暂停执行所述第一中断,并开始执行所述第二中断；若所述第二中断的优先级未超过所述中断优先级阈值,则继续执行所述第一中断。使得基于RISC-Ⅴ架构的芯片能够实现中断嵌套功能,提高了系统的实时性。(The embodiment of the invention provides an interrupt processing method, a system and a computer readable storage medium, which are suitable for a system based on a RISC-V instruction set architecture, wherein the method comprises the following steps: setting a priority of a first interrupt being executed to an interrupt priority threshold; opening a global interrupt enable of a processor core; receiving a second interrupt, and judging whether the priority of the second interrupt exceeds the interrupt priority threshold; if the priority of the second interrupt exceeds the interrupt priority threshold, suspending the execution of the first interrupt and starting to execute the second interrupt; and if the priority of the second interrupt does not exceed the interrupt priority threshold, continuing to execute the first interrupt. The chip based on the RISC-V architecture can realize the interrupt nesting function, and the real-time performance of the system is improved.)

1. An interrupt processing method, adapted for use in a system based on a RISC-V instruction set architecture, the method comprising:

setting a priority of a first interrupt being executed to an interrupt priority threshold;

opening a global interrupt enable of a processor core;

receiving a second interrupt, and judging whether the priority of the second interrupt exceeds the interrupt priority threshold;

if the priority of the second interrupt exceeds the interrupt priority threshold, suspending the execution of the first interrupt and starting to execute the second interrupt;

and if the priority of the second interrupt does not exceed the interrupt priority threshold, continuing to execute the first interrupt.

2. The method of claim 1, wherein after suspending execution of the first interrupt and beginning execution of the second interrupt if the priority of the second interrupt exceeds the interrupt priority threshold, the method further comprises:

and after the second interrupt is executed, resuming the execution of the first interrupt.

3. The method of claim 2, wherein suspending execution of the first interrupt and beginning execution of the second interrupt if the priority of the second interrupt exceeds the interrupt priority threshold further comprises:

updating the interrupt priority threshold to the priority of the second interrupt when the second interrupt starts to execute; and

and after the second interrupt is executed, restoring the interrupt priority threshold value to the priority of the first interrupt.

4. The method of claim 3, wherein the restoring the interrupt priority threshold to the priority of the first interrupt specifically comprises:

when the first interrupt or the second interrupt starts to execute, backing up a current interrupt priority threshold register; and

and when the first interrupt or the second interrupt is executed completely, restoring the backup.

5. A method according to any one of claims 1 to 4, wherein the initial value of the interrupt priority threshold is 0.

6. The method of claim 1, wherein the opening global interrupt enablement in the processor core specifically comprises:

opening a machine interrupt enable bit in a machine state register of the processor core.

7. The method of claim 1, wherein prior to the at least one processor core receiving and executing the first interrupt, the method further comprises:

and when the interrupt controller is initialized, assigning a priority value for each interrupt source and storing the priority value in a corresponding priority register in the interrupt controller, wherein the interrupt source comprises the first interrupt and the second interrupt.

8. The method of claim 4, wherein the interrupt handling method is specifically applied in RISC-V machine mode.

9. An interrupt handling system, the method being applicable to a RISC-V instruction set architecture based system, the system comprising:

a threshold setting module, configured to set a priority of a first interrupt being executed as an interrupt priority threshold;

a global interrupt enabling module for opening a global interrupt in the processor core;

the interrupt judging module is used for receiving a second interrupt and judging whether the priority of the second interrupt exceeds the interrupt priority threshold;

an interrupt execution module to:

if the priority of the second interrupt exceeds the interrupt priority threshold, suspending the execution of the first interrupt and starting to execute the second interrupt;

and if the priority of the second interrupt does not exceed the interrupt priority threshold, continuing to execute the first interrupt.

10. The system of claim 9, wherein the interrupt execution module is further configured to, after suspending execution of the first interrupt and beginning execution of the second interrupt if the priority of the second interrupt exceeds the interrupt priority threshold:

and after the second interrupt is executed, resuming the execution of the first interrupt.

11. The system of claim 10, wherein if the priority of the second interrupt exceeds the interrupt priority threshold, the threshold setting module is further configured to:

updating the interrupt priority threshold to the priority of the second interrupt when the second interrupt starts to execute; and

and after the second interrupt is executed, restoring the interrupt priority threshold value to the priority of the first interrupt.

12. The system of claim 11, wherein the threshold setting module further comprises:

the backup module is used for backing up a current interrupt priority threshold register when the first interrupt or the second interrupt starts to execute; and

and the recovery module is used for recovering the backup when the first interrupt or the second interrupt is executed.

13. The system according to any one of claims 9 to 12, wherein the threshold setting module is further configured to set an initial value of the interrupt priority threshold to 0.

14. The system of claim 9, wherein the global interrupt enabling module is specifically configured to:

opening a machine interrupt enable bit in a machine state register of the processor core.

15. The system of claim 9, wherein prior to the at least one processor core receiving and executing the first interrupt, the threshold setting module is further to:

and when the interrupt controller is initialized, assigning a priority value for each interrupt source and storing the priority value in a corresponding priority register in the interrupt controller, wherein the interrupt source comprises the first interrupt and the second interrupt.

16. The system of claim 9, wherein the interrupt handling system is specifically adapted for use in RISC-V machine mode.

17. An interrupt processing system, comprising:

one or more processors;

a memory for storing one or more programs;

the one or more programs, when executed by the one or more processors, cause the one or more processors to implement:

setting a priority of a first interrupt being executed to an interrupt priority threshold;

opening a global interrupt in the processor core;

receiving a second interrupt, and judging whether the priority of the second interrupt exceeds the interrupt priority threshold;

if the priority of the second interrupt exceeds the interrupt priority threshold, suspending the execution of the first interrupt and starting to execute the second interrupt;

and if the priority of the second interrupt does not exceed the interrupt priority threshold, continuing to execute the first interrupt.

18. A computer-readable storage medium storing a program which, when executed by a processor, causes the processor to perform the method of any one of claims 1-8.