阅读说明：本技术 集成电路（ic）器件 (Integrated Circuit (IC) device ) 是由 金炫助 全众源 于 2019-03-19 设计创作，主要内容包括：提供了一种集成电路(IC)器件,该集成电路(IC)器件包括逻辑单元,该逻辑单元具有由单元边界限定的区域。逻辑单元包括第一器件区域、器件隔离区域和第二器件区域。第一器件区域和第二器件区域布置为在第一方向上彼此间隔开,第一方向垂直于第二方向。器件隔离区域在第一器件区域和第二器件区域之间。第一器件区域在第二方向上的第一最大长度小于单元边界在第二方向上的宽度,并且第二器件区域在第二方向上的第二最大长度基本上等于单元边界在第二方向上的宽度。(An Integrated Circuit (IC) device is provided that includes a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first and second device regions are arranged to be spaced apart from each other in a first direction, which is perpendicular to the second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region in the second direction is substantially equal to the width of the cell boundary in the second direction.)

1. An integrated circuit device, comprising:

a logic cell having an area defined by cell boundaries,

the logic cell includes a first device region, a device isolation region and a second device region,

the first and second device regions are arranged to be spaced apart from each other in a first direction, the first direction being perpendicular to a second direction,

the device isolation region is between the first device region and the second device region,

a first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and

a second maximum length of the second device region in the second direction is equal to a width of the cell boundary in the second direction.

2. The integrated circuit device of claim 1, wherein

The logic cell further includes a plurality of gate structures arranged at a first pitch in the second direction,

each of the plurality of gate structures extends in the first direction within the cell boundary over at least the first device region, and

the difference between the second maximum length and the first maximum length is equal to the first pitch.

3. The integrated circuit device of claim 1, wherein

The cell boundary includes a pair of vertical boundary lines,

each of the pair of vertical boundary lines extends in a height direction of the logic unit and is parallel to each other, and

the pair of vertical boundary lines define a width of the logic cell,

the first device region is spaced apart from one of the pair of vertical boundary lines, and

a pair of side surfaces of the second device region that are opposite to each other in the second direction are respectively contiguous with the pair of vertical boundary lines.

4. The integrated circuit device of claim 1, wherein

The logic cell includes one or more first fin-type active regions and a first fin separation insulating portion,

the one or more first fin-type active regions are located on the first device region and extend in the second direction,

the first fin separation insulating portion is between the one or more first fin-type active regions and the cell boundary,

the first fin separation insulating portion facing the second device region, the device isolation region being between the first fin separation insulating portion and the second device region,

the one or more first fin-type active regions are spaced apart from the cell boundary by a first distance, and

the first fin separation insulating portion is between the one or more first fin-type active regions and the cell boundary.

5. The integrated circuit device of claim 4, wherein

The logic cell further includes one or more second fin-type active regions and a second fin separation insulating portion,

the one or more second fin active regions extend over the second device region and in the second direction,

the second fin separation insulating portion includes sidewalls facing ends of the one or more second fin-type active regions,

the second fin separation insulating portion extends along the cell boundary in the first direction at a position overlapping the cell boundary,

in the second direction, the one or more second fin-shaped active regions are spaced apart from the cell boundary by a second distance,

the second fin separation insulating portion is between the one or more second fin-type active regions and the cell boundary, and

the second distance is less than the first distance.

6. The integrated circuit device of claim 1, wherein

The logic cell includes a first fin separation insulating portion and a second fin separation insulating portion,

the first fin separation insulating portion is between a vertical boundary line of the cell boundary and the first device region,

the first fin separation insulating portion has a first width in the second direction, the vertical boundary line extends in the first direction, the second fin separation insulating portion extends along the vertical boundary line in the second device region,

the second fin separation insulating portion has a second width in the second direction, and

the second width is less than the first width.

7. The integrated circuit device of claim 6, wherein

The logic cell also includes a plurality of first fin-type active regions and a plurality of second fin-type active regions,

each of the plurality of first fin-type active regions extending in the second direction in the first device region and each having a first end facing the first fin separation insulating portion,

each of the plurality of second fin-type active regions extending in the second direction in the second device region and each having a second end facing the second fin separation insulating portion,

a first distance between the vertical boundary line and the first end of each of the plurality of first fin active regions in the second direction is greater than a second distance between the vertical boundary line and the second end of each of the plurality of second fin active regions in the second direction.

8. The integrated circuit device of claim 6, wherein

The logic cell also includes a plurality of gate structures and a dummy gate structure,

each of the plurality of gate structures extends in the first direction at a location spaced apart from the vertical boundary line over the first and second device regions,

the dummy gate structure is on the first fin separation insulating portion, the dummy gate structure extends in the first direction, and

the dummy gate structure forms a straight line in the first direction together with the second fin separation insulation portion.

9. The integrated circuit device of claim 8, wherein an end of the dummy gate structure faces a sidewall of the second fin separation insulation portion.

10. The integrated circuit device of claim 8, wherein the dummy gate structure extends on the second fin separation insulating portion along the vertical boundary line.

11. An integrated circuit device, comprising:

a substrate including first and second device regions in a logic cell defined by a cell boundary, the first and second device regions defined by a trench in the substrate and spaced apart from each other in a first direction, a length of the first device region in a second direction different from a length of the second device region in the second direction, the second direction perpendicular to the first direction, the first device region including a first fin-type active region extending in the second direction, the second device region including a second fin-type active region extending in the second direction;

a device isolation region between the first device region and the second device region and in the trench in the substrate;

a first fin separation insulating portion on the substrate between the first device region and the cell boundary, the first fin separation insulating portion extending along the cell boundary in the first direction, the first fin separation insulating portion having a first width in the second direction, and the first fin separation insulating portion facing an end of the first fin-type active region; and

a second fin separation insulating portion on the second device region, the second fin separation insulating portion being spaced apart from the first fin separation insulating portion, the second fin separation insulating portion extending along the cell boundary in the first direction, the second fin separation insulating portion having a second width in the second direction, the second width being smaller than the first width in the second direction, the second fin separation insulating portion facing an end of the second fin-type active region.

12. The integrated circuit device of claim 11, wherein a first maximum length of the first device region in the second direction is less than a second maximum length of the second device region in the second direction.

13. The integrated circuit device of claim 11, wherein

The first fin separation insulating portion faces the second device region, and

the device isolation region is interposed between the first fin partition insulating portion and the second device region.

14. The integrated circuit device of claim 11, wherein a length of the first fin active region in the second direction is less than a length of the second fin active region in the second direction.

15. The integrated circuit device of claim 11, further comprising:

a dummy gate structure on the first fin separation insulating portion, wherein

The dummy gate structure extends in the first direction, an

The dummy gate structure forms a straight line in the first direction together with the second fin separation insulation portion.

16. An integrated circuit device, comprising:

a cell boundary contact portion between first and second logic cells adjacent to each other, wherein a first cell boundary defining the first logic cell and a second cell boundary defining the second logic cell meet each other at the cell boundary contact portion,

the first logic cell includes a first device region, a second device region, a first fin separation insulating portion, and a portion of a second fin separation insulating portion,

the first and second device regions are spaced apart from each other in a first direction,

the first device region includes a first fin-type active region extending in a second direction perpendicular to the first direction,

the first fin separation insulating portion has a first inner sidewall facing the first fin-type active region and a first outer sidewall aligned with the cell boundary contact portion,

the second device region includes a second fin-type active region extending in the second direction,

the second fin separation insulating portion extends along the cell boundary contact portion in the first direction at a position overlapping the cell boundary contact portion,

the second fin isolation insulation portion has a second inner sidewall and a second outer sidewall, the second inner sidewall faces the second fin-type active region, and the second outer sidewall is located in the second logic unit.

17. The integrated circuit device of claim 16, wherein

The first logic cell includes a plurality of gate structures extending in the first direction and arranged in the second direction at a first pitch,

the length of the first device region in the second direction is smaller than the length of the second device region in the second direction by the first pitch.

18. The integrated circuit device of claim 16, wherein

The first device region has a first side and a second side,

the second side is opposite the first side,

the first side is aligned with the first cell boundary defining an area of the first logic cell,

the second side is spaced apart from the cell boundary contact portion with the first fin separation insulating portion between the second side and the cell boundary contact portion, and

the second device region includes two sides of a region aligned with the first cell boundary and the cell boundary contact portion, respectively, in the second direction and defining the first logic cell.

19. The integrated circuit device of claim 16, wherein

The second logic cell includes an adjacent first device region and an adjacent second device region spaced apart from each other in the first direction,

the adjacent first device region includes a first side and a second side opposite the first side,

the first side is aligned with the cell boundary contact portion, and

the second side is spaced apart from the second cell boundary defining the second logic cell.

20. The integrated circuit device of claim 19, wherein

The first device region and the adjacent first device region are aligned with each other in a straight line in the second direction and spaced apart from each other with the first fin separation insulating portion between the first device region and the adjacent first device region, and

the second device region and the adjacent second device region are aligned with each other in a straight line in the second direction and abut each other.

Technical Field

The inventive concepts relate to Integrated Circuit (IC) devices, and more particularly, to IC devices including fin field effect transistors.

Background

Recently, as the scaling down of IC devices progresses rapidly, interest in obtaining not only a high operation speed but also an operation accuracy of the IC devices has increased. Therefore, it is required to develop an IC device having a structure capable of providing improved performance according to a channel type of a transistor and effectively utilizing a given area within a limited logic cell area.

Disclosure of Invention

The inventive concept provides an Integrated Circuit (IC) device having a structure that can provide superior performance according to each channel type in a transistor even if the area of a device region is reduced according to the scaling down of the IC device, and also having a structure in which improved performance can be provided by improving the utilization of an active region.

According to one aspect of the inventive concept, an IC device includes a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first and second device regions are arranged to be spaced apart from each other in a first direction, which is perpendicular to the second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region in the second direction is substantially equal to the width of the cell boundary in the second direction.

According to another aspect of the inventive concept, an IC device includes: a substrate including a first device region and a second device region in a logic cell defined by a cell boundary; a device isolation region in the trench between the first device region and the second device region in the substrate; a first fin separation insulating portion on the substrate; and a second fin separation insulating portion on the second device region. The first device region and the second device region are defined by a trench in the substrate and are spaced apart from each other in a first direction. The length of the first device region in the second direction is different from the length of the second device region in the second direction. The second direction is perpendicular to the first direction. The first device region includes a first fin-type active region extending in a second direction. The second device region includes a second fin-type active region extending in a second direction. The first fin separation insulation portion is between the first device region and the cell boundary. The first fin separation insulating portion extends along a cell boundary in a first direction. The first fin separation insulating portion has a first width in the second direction, and faces one end of the first fin-type active region. The second fin separation insulating portion is spaced apart from the first fin separation insulating portion, extends along the cell boundary in the first direction, and has a second width in the second direction that is smaller than the first width in the second direction. The second fin separates an end of the insulating portion facing the second fin-type active region.

According to another aspect of the inventive concept, an IC device includes a cell boundary contact portion between first and second logic cells adjacent to each other. A first cell boundary defining the first logic cell and a second cell boundary defining the second logic cell meet each other at a cell boundary contact portion. The first logic cell includes a first device region, a second device region, a first fin separation insulating portion, and a portion of a second fin separation insulating portion. The first device region and the second device region are spaced apart from each other in the first direction. The first device region includes a first fin-type active region extending in a second direction, the second direction being perpendicular to the first direction. The first fin partition insulating portion has a first inner sidewall and a first outer sidewall. The first inner sidewall faces the first fin-type active region, and the first outer sidewall is aligned with the cell boundary contact portion. The second device region includes a second fin-type active region extending in a second direction. The second fin separation insulating portion extends in the first direction along the cell boundary contact portion at a position overlapping the cell boundary contact portion. The second fin separation insulating portion has a second inner sidewall and a second outer sidewall. The second inner side wall faces the second fin-type active region. The second exterior sidewall is located within the second logic cell.

Drawings

Example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a plan layout view of an example cell block of an Integrated Circuit (IC) device according to some embodiments of the inventive concepts;

fig. 2 is a plan layout view illustrating main components of an IC device according to an embodiment of the inventive concept;

FIG. 3A is a sectional view taken along line X1-X1 'of FIG. 2, and FIG. 3B is a sectional view taken along line X2-X2' of FIG. 2; FIG. 3C is a sectional view taken along line Y1-Y1 'of FIG. 2, and FIG. 3D is a sectional view taken along line Y2-Y2' of FIG. 2;

fig. 4 is a layout diagram for explaining IC devices according to further embodiments of the inventive concepts;

fig. 5 is a plan layout view illustrating main components of an IC device according to further embodiments of the inventive concepts;

FIG. 6A is a sectional view taken along line X1-X1 'of FIG. 5, FIG. 6B is a sectional view taken along line X2-X2' of FIG. 5, FIG. 6C is a sectional view taken along line Y1-Y1 'of FIG. 5, and FIG. 6D is a sectional view taken along line Y2-Y2' of FIG. 5;

fig. 7A and 7B are cross-sectional views for explaining IC devices according to further embodiments of the inventive concepts;

fig. 8 is a cross-sectional view for explaining IC devices according to further embodiments of the inventive concepts;

fig. 9 is a layout view for explaining IC devices according to further embodiments of the inventive concepts;

fig. 10A is a plan layout view for explaining IC devices according to further embodiments of the inventive concepts;

fig. 10B is a plan layout view for explaining IC devices according to further embodiments of the inventive concepts;

fig. 11A is a plan layout view for explaining IC devices according to further embodiments of the inventive concepts;

fig. 11B is a plan layout view for explaining IC devices according to further embodiments of the inventive concepts;

fig. 12A to 19D are cross-sectional views for explaining a method of manufacturing an IC device according to an embodiment of the inventive concept, in which fig. 12A, 13A, …, and 19A are cross-sectional structures of portions corresponding to a section taken along line X1-X1 'of fig. 2 according to a process order, fig. 12B, 13B, …, and 19B are cross-sectional structures of portions corresponding to a section taken along line X2-X2' of fig. 2 according to a process order, fig. 12C, 13C, …, and 19C are cross-sectional structures of portions corresponding to a section taken along line Y1-Y1 'of fig. 2 according to a process order, and fig. 12D, 13D, …, and 19D are cross-sectional structures of portions corresponding to a section taken along line Y2-Y2' of fig. 2 according to a process order; and

fig. 20A to 20D are sectional views for explaining methods of manufacturing an IC device according to further embodiments of the inventive concepts.

Detailed Description

The inventive concept will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the inventive concept are shown. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.

Fig. 1 is a schematic plan view of an Integrated Circuit (IC) device 10 according to some embodiments of the inventive concepts.

Referring to fig. 1, a cell block 12 of an IC device 10 may include a plurality of logic cells LC including circuit patterns for constituting various circuits. The plurality of logic cells LC may be arranged in a width direction (X direction) and a height direction (Y direction) to form a matrix within the cell block 12.

The plurality of logic cells LC may include a circuit pattern having a layout designed according to a place and Route (PnR) technology to perform at least one logic function. The plurality of logic cells LC may perform various logic functions. According to some embodiments, the plurality of logic cells LC may comprise a plurality of standard cells. According to some embodiments, at least some of the plurality of logic cells LC may perform the same function as each other. According to some further embodiments, at least some of the plurality of logic cells LC may perform functions different from each other.

The plurality of logic cells LC may be various types of logic cells including a plurality of circuit elements. For example, the plurality of logic cells LC may include at least one of AND (AND), NAND (NAND), OR (OR), NOR (NOR), exclusive OR (XOR), exclusive NOR (XNOR), Inverter (INV), Adder (ADD), Buffer (BUF), Delay (DLY), Filter (FILL), multiplexer (MXT/MXIT), OR/AND/inverter (oai), AND/OR (ao), AND/OR/inverter (aoi), D flip-flop, reset flip-flop, master-slave flip-flop, latch, AND a combination thereof, but the inventive concept is not limited thereto.

In the cell block 12, at least some of the plurality of logic cells LC forming the row R1, R2, R3, R4, R5, or R6 may have the same width as each other in the width direction (X direction). The at least some of the plurality of logic cells LC forming the row R1, R2, R3, R4, R5, or R6 may have the same height as one another. However, the inventive concept is not limited to the illustration of fig. 1, and at least some of the plurality of logic cells LC forming the row R1, R2, R3, R4, R5, or R6 may have widths different from each other and heights different from each other.

An area of each of the plurality of logic cells LC included in the cell block 12 of the IC device 10 may be defined by a cell boundary CB. The cell boundary contact portion CBC may be included between two logic cells LC adjacent to each other in a width direction (X direction) or a height direction (Y direction) among the plurality of logic cells LC. In the cell boundary contact portion CBC, the respective cell boundaries CB of the two adjacent logic cells LC meet each other.

Two logic cells LC adjacent to each other in the width direction among the plurality of logic cells LC forming the row R1, R2, R3, R4, R5, or R6 may contact each other in the cell boundary contact portion CBC.

According to some embodiments, the two logic cells LC adjacent to each other among the plurality of logic cells LC forming the row R1, R2, R3, R4, R5, or R6 may perform the same function as each other. In this case, the two adjacent logic cells LC may have the same structure as each other. According to some further embodiments, the two logic cells LC adjacent to each other among the plurality of logic cells LC forming the row R1, R2, R3, R4, R5, or R6 may perform functions different from each other.

According to some embodiments, the logic cell LC selected from the plurality of logic cells LC included in the cell block 12 of the IC device 10 and the logic cell LC adjacent to the selected logic cell LC in the height direction (Y direction) may have a structure symmetrical to each other with respect to a cell boundary contact portion CBC between the two logic cells LC. For example, the reference logic cell LC _ R on the third row R3 and the lower logic cell LC _ L on the second row R2 may have a structure symmetrical to each other with respect to the cell boundary contact portion CBC between the reference logic cell LC _ R and the lower logic cell LC _ L. The reference logic cell LC _ R on the third row R3 and the higher logic cell LC _ H on the fourth row R4 may have a structure symmetrical to each other with respect to a cell boundary contact portion CBC between the reference logic cell LC _ R and the higher logic cell LC _ H.

Although fig. 1 shows the cell block 12 including six rows of R1, R2. Thus, the cell block 12 may include various numbers of rows selected according to a desired arrangement and various numbers of logic cells selected according to a desired arrangement.

Fig. 2 and 3A to 3D are diagrams for explaining an IC device 100 according to some embodiments of the inventive concept. Fig. 2 is a plan layout view showing the main components of the IC device 100, fig. 3A is a sectional view taken along line X1-X1 'of fig. 2, fig. 3B is a sectional view taken along line X2-X2' of fig. 2, fig. 3C is a sectional view taken along line Y1-Y1 'of fig. 2, and fig. 3D is a sectional view taken along line Y2-Y2' of fig. 2. The IC device 100 may configure a logic cell including a fin field effect transistor (FinFET).

Referring to fig. 2 and 3A to 3D, the IC device 100 includes a logic cell LC1 on a substrate 110. Logic cell LC1 has an area defined by cell boundary CB. The logic cell LC1 may be one of the plurality of logic cells LC constituting the cell block 12 of fig. 1.

The substrate 110 may have a main surface 110M extending from a vertical height LV1 in a horizontal direction (X-Y plane direction). The substrate 110 may include an elemental semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. The substrate 110 may include a conductive region, such as an impurity-doped well or an impurity-doped structure.

The logic cell LC1 may include a first device region RX1 and a second device region RX 2. The first device region RX1 and the second device region RX2 may be arranged to be spaced apart from each other in the height direction (Y direction) of the logic cell LC1 such that a device isolation region DTA between the first device region RX1 and the second device region RX2 is within a cell boundary CB.

In the width direction (X direction) of the logic cell LC1, the first maximum length ML1 of the first device region RX1 may be less than the X direction width BWX of the cell boundary CB, and the second maximum length ML2 of the second device region RX2 may be substantially equal to the X direction width BWX of the cell boundary CB. The cell boundary CB includes a pair of vertical boundary lines VL each extending in the height direction (Y direction) of the logic cell LC1 and parallel to each other to define the width of the logic cell LC1, and a pair of horizontal boundary lines HL each extending in the width direction (X direction) of the logic cell LC1 and parallel to each other to define the height of the logic cell LC 1.

One of a pair of opposite side faces of the first device region RX1 in the width direction (X direction) may be spaced apart from one of the vertical boundary lines VL of the cell boundary CB, and the other of the two opposite side faces may meet the other of the vertical boundary lines VL of the cell boundary CB. A pair of opposite side faces of the second device region RX2 in the width direction (X direction) may be arranged to meet the pair of vertical boundary lines VL of the cell boundary CB, respectively.

In the first device region RX1, there are a plurality of first fin-type active regions F1 protruding from the substrate 110 in the vertical direction (Z direction). In the second device region RX2, there are a plurality of second fin-type active regions F2 protruding from the substrate 110 in the vertical direction (Z direction). Between the first device region RX1 and the second device region RX2, a deep trench DT may be present in the substrate 110. The device isolation region DTA may be formed to fill the deep trench DT. The plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2 may each extend in the width direction (X direction) of the logic cell LC1 and may be parallel to each other.

On the first and second device regions RX1 and RX2, there may be device isolation layers 112 between the plurality of first fin-type active regions F1 and between the plurality of second fin-type active regions F2. The device isolation layer 112 may cover both sidewalls of each of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2. Each of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2 may protrude above the device isolation layer 112 to have a fin shape.

The first fin partition insulating portion FS1 may be interposed between the first device region RX1 and the vertical boundary line VL of the cell boundary CB. The first fin partition insulating portion FS1 may have a first width W1 in the width direction (X direction) of the logic cell LC 1. According to some embodiments, the first width W1 of the first fin partition insulating portion FS1 may correspond to a difference between a first maximum length ML1 of the first device region RX1 and a second maximum length ML2 of the second device region RX 2.

Within the cell boundary CB, the first fin partition insulating portion FS1 may face the second device region RX2 with the device isolation region DTA therebetween. According to some embodiments, the first fin separation insulating portion FS1 may be a portion of the device isolation layer 112.

The first fin-partition insulating portion FS1 may have a sidewall S1, the sidewall S1 facing one end E1 of each of the plurality of first fin-type active regions F1. In the width direction (X direction) of the logic cell LC1, one end E1 of each of the plurality of first fin-type active regions F1 may be spaced apart from the vertical boundary line VL of the cell boundary CB by a first distance D1 with the first fin separation insulating portion FS1 therebetween, the first distance D1 being substantially equal to the first width W1.

A second fin partition insulating portion FS2 extending along the vertical boundary line VL of the cell boundary CB may be disposed in the second device region RX 2. The second fin partition insulating portion FS2 may have a second width W2 in the width direction (X direction) of the logic cell LC1, which is smaller than the first width W1. The second fin-partition insulating portion FS2 may have a first sidewall S2A facing one end E2 of each of the plurality of second fin-type active regions F2. The second fin partition insulating portion FS2 may overlap the vertical boundary line VL of the cell boundary CB and extend in the height direction (Y direction) of the logic cell LC1 along the vertical boundary line VL. In the width direction (X direction) of the logic cell LC1, one end E2 of each of the plurality of second fin-type active regions F2 may be spaced apart from the vertical boundary line VL of the cell boundary CB by a second distance D2 with the second fin separation insulating portion FS2 therebetween, the second distance D2 being smaller than the first distance D1. The second distance D2 may be less than a second width W2 of the second fin separation insulation portion FS 2.

According to some embodiments, each of the first fin partition insulating portion FS1 and the second fin partition insulating portion FS2 may include a single insulating layer or a plurality of insulating layers. Although the insulating layer included in each of the first fin partition insulating portion FS1 and the second fin partition insulating portion FS2 may include a silicon oxide layer, a silicon nitride layer, a SiOCN layer, a SiCN layer, or a combination thereof, the inventive concept is not limited thereto. According to some further embodiments, at least some of the first fin partition insulating portion FS1 and the second fin partition insulating portion FS2 may include an air gap.

According to some embodiments, the device isolation layer 112, the device isolation region DTA, and the first fin partition insulating portion FS1 may include the same insulating material as each other. For example, the device isolation layer 112, the device isolation region DTA, and the first fin partition insulating portion FS1 may each include a silicon oxide layer.

The second fin partition insulating portion FS2 may include an upper insulating portion US and a lower insulating portion LS integrally connected to each other. The upper insulating portion US may extend in the Y direction over the second device region RX 2. Each of the upper insulating portion US and the lower insulating portion LS may include a silicon oxide layer, a silicon nitride layer, a SiOCN layer, a SiCN layer, or a combination thereof.

The first fin partition insulating portion FS1 and the second fin partition insulating portion FS2 may be spaced apart from each other with the device isolation region DTA therebetween, and a portion of the first fin partition insulating portion FS1 and a portion of the second fin partition insulating portion FS2 may face each other with the device isolation region DTA therebetween.

The vertical length (length in the Z direction) of the second fin partition insulating portion FS2 may be greater than the vertical length of the first fin partition insulating portion FS 1. A lowermost surface vertical height of the first fin partition insulating portion FS1 may be substantially the same as a vertical height LV1 of the main surface 110M of the substrate 110. However, the inventive concept is not limited thereto. According to some embodiments, the vertical height of the lowermost surface of the first fin partition insulating portion FS1 may be lower or higher than the vertical height LV1 of the main surface 110M of the substrate 110. The term "vertical height" as used herein refers to a length in a vertical direction (e.g., ± Z direction) with respect to the main surface 110M of the substrate 110.

A lowermost surface vertical height LV2 of the second fin partition insulating portion FS2 may be lower than a lowermost surface vertical height LV1 of the first fin partition insulating portion FS1 and may be lower than a lowermost surface vertical height of the second fin-type active region F2. However, the inventive concept is not limited thereto. For example, the lowermost surface vertical height LV2 of the second fin partition insulating portion FS2 may be equal to or higher than the lowermost surface vertical height LV1 of the first fin partition insulating portion FS 1. The lowermost surface vertical height LV2 of the second fin partition insulating portion FS2 may be equal to or higher than the lowermost surface vertical height of the second fin-type active region F2.

An uppermost surface vertical height LV3 of the first fin partition insulating portion FS1 and an uppermost surface vertical height LV4 of the second fin partition insulating portion FS2 may be different from each other. According to some embodiments, the uppermost surface vertical height LV4 of the second fin partition insulating portion FS2 may be higher than the uppermost surface vertical height LV3 of the first fin partition insulating portion FS 1. An uppermost surface vertical height LV3 of the first fin partition insulating portion FS1 may be substantially the same as an uppermost surface vertical height of the device isolation layer 112. An uppermost surface vertical height LV3 of the first fin partition insulating portion FS1 may be lower than an uppermost surface vertical height LVF of the first fin-type active region F1 and the second fin-type active region F2, and an uppermost surface vertical height LV4 of the second fin partition insulating portion FS2 may be higher than the uppermost surface vertical height LVF.

A plurality of gate structures GS may extend in the Y direction over the substrate 110 within the cell boundary CB. The plurality of gate structures GS may have the same width as each other in the X direction, and may be arranged at a regular pitch (e.g., at the first pitch P1) in the X direction. The difference between the first maximum length ML1 of the first device region RX1 and the second maximum length ML2 of the second device region RX2 may be substantially the same as the first pitch P1. An uppermost surface vertical height LV4 of the second fin partition insulating portion FS2 may be higher than an uppermost surface vertical height LVG of the plurality of gate structures GS.

Each of the plurality of gate structures GS may extend over the first device region RX1, the device isolation region DTA, and the second device region RX2 to be parallel to the vertical boundary line VL of the cell boundary CB. At least some of the gate structures GS1, GS2, GS3, and GS4 spaced apart from the vertical boundary line VL of the cell boundary CB among the plurality of gate structures GS may be normal gate structures. The plurality of gate structures GS may include dummy gate structures DG overlapping the vertical boundary lines VL of the cell boundary CB. The dummy gate structure DG may include a portion disposed on the first fin partition insulating portion FS1 so as to vertically overlap with the first fin partition insulating portion FS 1. The dummy gate structure DG may extend along the vertical boundary line VL to be aligned in a straight line with the second fin separation insulating portion FS 2. In the Y direction, a Y-direction length of the dummy gate structure DG may be smaller than a Y-direction length of each of the gate structures GS1, GS2, GS3, and GS4 included in the plurality of gate structures GS. The dummy gate structure DG may have one end DGE facing the second sidewall S2B of the second fin partition insulating portion FS 2.

A gate structure GS4 selected from the plurality of gate structures GS may extend to cover the plurality of first fin-type active regions F1 and the upper surface of the first fin separation insulating portion FS1 on the first device region RX1 and to cover the plurality of second fin-type active regions F2 on the second device region RX2 at a position spaced apart from the second fin separation insulating portion FS 2. The gate structure GS4 may be disposed to vertically overlap the first device region RX1 and the first fin partition insulating portion FS 1. The gate structure GS4 may include a portion vertically overlapping the first fin-spaced insulating portion FS1 and a portion vertically overlapping the plurality of first fin-type active regions F1. In the gate structure GS4, a vertical length (length in the Z direction) of a portion vertically overlapping the first fin-separation insulating portion FS1 may be greater than a vertical length of a portion vertically overlapping the plurality of first fin-type active regions F1. The gate structure GS4 may form a dummy gate structure on the first device region RX1 and may form a normal gate structure on the second device region RX 2. The dummy gate structure DG around the first fin partition insulating portion FS1 may have a structure similar to the gate structure GS 1.

The plurality of gate structures GS may cover an upper surface and both sidewalls of each of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2 and an upper surface of the device isolation layer 112. In the first and second device regions RX1 and RX2, a plurality of MOS transistors may be formed along the plurality of gate structures GS. Each of the plurality of MOS transistors may have a three-dimensional (3D) MOS transistor in which a channel is formed at an upper surface and two sidewalls of each of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2. According to some embodiments, the first device region RX1 may be an NMOS transistor region, and the plurality of first fin-type active regions F1 may include an N-type channel region. According to some embodiments, the second device region RX2 may be a PMOS transistor region, and the plurality of second fin-type active regions F2 may include a P-type channel region. However, the inventive concept is not limited thereto, and various modifications may be made. For example, the first device region RX1 may be a PMOS transistor region, and the second device region RX2 may be an NMOS transistor region.

The gate structures GS1, GS2, GS3, and GS4 and the dummy gate structure DG may include the same material as each other. According to some embodiments, the gate structures GS1, GS2, GS3, and GS4 and the dummy gate structure DG may include the same metal as each other and may have a stacked structure substantially the same as each other. However, the dummy gate structure DG may maintain an electrically floating state during operation of the IC device 100. Similarly, the portion of the gate structure GS4 that passes through the first device region RX1 may remain electrically floating during operation of the IC device 100.

The plurality of gate structures GS may each have a stacked structure of the gate insulating layer 132 and the gate line GL. The gate insulating layer 132 may cover a bottom surface and both sidewalls of the gate line GL. The gate insulating layer 132 may include a silicon oxide layer, a high-k dielectric layer, or a combination thereof. The high-k dielectric layer may include a material having a dielectric constant greater than that of the silicon oxide layer. The high-k dielectric layer may comprise a metal oxide or a metal oxynitride. Interface layers (not shown) may be present between the first fin-type active region F1 and the gate insulating layer 132 in the first device region RX1 and between the second fin-type active region F2 and the gate insulating layer 132 in the second device region RX 2. The interface layer may include an oxide layer, a nitride layer, or an oxynitride layer.

The plurality of gate lines GL may have a structure in which a metal nitride layer, a metal layer, a conductive cap layer, and a gap-fill metal layer are stacked in the order stated herein. The metal nitride layer and the metal layer may include at least one metal selected from Ti, Ta, W, Ru, Nb, Mo, and Hf. The gap-fill metal layer may include a W layer or an Al layer. Each of the plurality of gate lines GL may include a work function metal-containing layer. The work function metal-containing layer may include at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. According to some embodiments, the plurality of gate lines GL may each include a stacked structure of TiAlC/TiN/W, TiN/TaN/TiAlC/TiN/W, or TiN/TaN/TiN/TiAlC/TiN/W, but the inventive concept is not limited thereto.

An upper surface of each of the plurality of gate structures GS may be covered by a gate insulating cap 140. The gate insulating cap layer 140 may include a silicon nitride layer.

The plurality of first insulating spacers 120 may cover both sidewalls of each of the plurality of gate structures GS. Each of the plurality of first insulating spacers 120 may extend in a straight line shape in the Y direction together with the plurality of gate structures GS. A plurality of second insulating spacers 122 may cover both sidewalls of the second fin partition insulating portion FS 2. Each of the plurality of second insulation spacers 122 may extend in a straight line shape in the Y direction together with the second fin partition insulation portion FS 2. The plurality of first insulating spacers 120 and the plurality of second insulating spacers 122 may include a silicon nitride layer, a SiOCN layer, a SiCN layer, or a combination thereof.

A vertical length (e.g., a length in the Z-direction) of the plurality of second insulating spacers 122 may be less than a vertical length of the plurality of first insulating spacers 120. The vertical height of the uppermost surfaces of the plurality of second insulation spacers 122 may be lower than the vertical height of the uppermost surfaces of the plurality of first insulation spacers 120.

In the first and second device regions RX1 and RX2, a plurality of recesses 124R may be present in the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2. The plurality of recesses 124R may be filled with a plurality of source/drain regions 124. The plurality of source/drain regions 124 may include a semiconductor layer epitaxially grown from a surface of each of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2 included in the inner walls of the plurality of recesses 124R. According to some embodiments, the plurality of source/drain regions 124 may include a plurality of epitaxially grown SiGe layers, epitaxially grown Si layers, and/or epitaxially grown SiC layers. According to some embodiments, the plurality of source/drain regions 124 on the first device region RX1 may include an epitaxially grown Si layer or an epitaxially grown SiC layer. According to some embodiments, the plurality of source/drain regions 124 on the second device region RX2 may include a plurality of epitaxially grown SiGe layers.

The inter-gate insulating layer 128 may be in each of between the plurality of gate structures GS and between the gate structures GS and the second fin partition insulating portion FS 2. The plurality of source/drain regions 124 may be covered by an inter-gate insulating layer 128. The inter-gate insulating layer 128 may include a portion contacting an upper surface of the first fin partition insulating portion FS 1. The inter-gate insulating layer 128 may include a silicon oxide layer.

The upper insulating cap layer 150 may cover the plurality of gate insulating cap layers 140, the plurality of first insulating spacers 120, the second fin partition insulating portion FS2, and the inter-gate insulating layer 128. The upper insulating cap layer 150 may include a silicon oxide layer, a silicon nitride layer, a polysilicon layer, or a combination thereof. The interlayer insulating layer 170 may be on the upper insulating cap layer 150. The interlayer insulating layer 170 may include a silicon oxide layer, a silicon nitride layer, or a combination thereof.

Although fig. 3A to 3D illustrate the first fin partition insulating portion FS1 and the second fin partition insulating portion FS2 each having a flat bottom surface, the inventive concept is not limited thereto. According to some embodiments, a bottom surface of each of the first fin partition insulating portion FS1 and the second fin partition insulating portion FS2 may include a curved surface included in a portion of a circle or a portion of an ellipse. According to some further embodiments, a bottom surface of each of the first fin partition insulating portion FS1 and the second fin partition insulating portion FS2 may include a non-flat surface having a point sharply protruding toward the substrate 110.

The IC device 100 of fig. 2 and 3A to 3D includes a first device region RX1 and a second device region RX2 having different lengths in the width direction (X direction) of the logic cell LC1, and a first maximum length ML1 of the first device region RX1 is smaller than a second maximum length ML2 of the second device region RX 2. The first fin partition insulating portion FS1 may be interposed between the first device region RX1 and the vertical boundary line VL of the cell boundary CB, and the second fin partition insulating portion FS2 extends along the vertical boundary line VL of the cell boundary CB in the second device region RX 2.

Since the IC device 100 of fig. 2 and 3A to 3D includes the first and second fin partition insulating portions FS1 and FS2 having different structures from each other and respectively located around the cell boundary CB on the first and second device regions RX1 and RX2 of the logic cell LC1, carrier mobility may be independently improved according to the conductivity type of each of the first and second device regions RX1 and RX2, the first and second device regions RX1 and RX2 include channel regions of different conductivity types from each other, and the active region area corresponding to the first width W1 of the first fin partition insulating portion FS1 may be further utilized in the second device region RX2 within the logic cell LC 1. Accordingly, while a stable fin separation region may be provided between transistors included in IC device 100, improved performance may be provided according to the channel type of each transistor, and the availability of active area within logic cell LC1 may be improved.

Fig. 4 is a layout diagram for explaining an IC device 200 according to further embodiments of the inventive concepts. The same reference numerals and symbols in fig. 4 as those in fig. 3A to 3D denote the same elements, and thus their description will be omitted here.

Referring to fig. 4, the IC device 200 includes a logic cell LC2, and a logic cell LC2 has an area defined by a cell boundary CB. The logic cell LC2 may be one of the plurality of logic cells LC constituting the cell block 12 of fig. 1. The logic cell LC2 has almost the same configuration as the logic cell LC1 described above with reference to fig. 2 and 3A to 3D. However, the positions of the first device region RX1 and the first fin separation insulating portion FS1 in the logic cell LC2 are different from those in the logic cell LC1 of fig. 2. The configuration of the logic cell LC1 of fig. 2 and the configuration of the logic cell LC2 of fig. 4 may be symmetrical to each other about one of a pair of vertical boundary lines VL.

Fig. 5 and 6A to 6D are diagrams for explaining an IC device 300 according to further embodiments of the inventive concepts. Fig. 5 is a plan layout view showing the main components of the IC device 300, fig. 6A is a sectional view taken along line X1-X1 'of fig. 5, fig. 6B is a sectional view taken along line X2-X2' of fig. 5, fig. 6C is a sectional view taken along line Y1-Y1 'of fig. 5, and fig. 6D is a sectional view taken along line Y2-Y2' of fig. 5. The same reference numerals and symbols in fig. 5 and 6A to 6D as those in fig. 2 and 3A to 3D denote the same elements, and thus their description will be omitted here.

Referring to fig. 5 and 6A to 6D, the IC device 300 includes a logic cell LC3 on the substrate 110. Logic cell LC3 has an area defined by cell boundary CB. The logic cell LC3 may be one of the plurality of logic cells LC constituting the cell block 12 of fig. 1. The logic cell LC3 has almost the same configuration as the logic cell LC1 described above with reference to fig. 2 and 3A to 3D. However, in the logic cell LC3, the second fin partition insulating portion FS2A extending along the vertical boundary line VL of the cell boundary CB may be provided in the second device region RX 2. The second fin partition insulating portion FS2A may have a second width W2A in the width direction (X direction) of the logic cell LC3, the second width W2A being smaller than the first width W1.

The second fin partition insulating portion FS2A may overlap the vertical boundary line VL of the cell boundary CB and extend in the height direction (Y direction) of the logic cell LC3 along the vertical boundary line VL. In the width direction (X direction) of the logic cell LC3, one end E2 of each of the plurality of second fin-type active regions F2 may be spaced apart from the vertical boundary line VL of the cell boundary CB by a second distance D2 smaller than the first width W1 with the second fin separation insulating portion FS2A therebetween. The second distance D2 may be less than the second width W2A of the second fin separation insulation portion FS 2A.

The second fin separation insulation portion FS2A may extend parallel to the plurality of gate structures GS. The plurality of gate structures GS may include dummy gate structures DGA overlapping the vertical boundary lines VL of the cell boundary CB. In the Y direction, the length of the dummy gate structure DGA is substantially the same as the length of each of the gate structures GS1, GS2, GS3, and GS4 included in the plurality of gate structures GS. The dummy gate structure DGA may include a portion disposed on the first fin partition insulating portion FS1 so as to vertically overlap the first fin partition insulating portion FS 1. The dummy gate structure DGA may extend along the vertical boundary line VL to be aligned in a straight line with the second fin separation insulating portion FS 2A. The detailed configuration of the dummy gate structure DGA is almost the same as that of the dummy gate structure DG described above with reference to fig. 2 and 3A to 3D.

An uppermost surface vertical height LV5 of the second fin partition insulating portion FS2A may be higher than uppermost surface vertical heights LVF of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2.

The second fin partition insulating portion FS2A may include a lower insulating pattern LSA and an upper insulating pattern USA. The lower insulation pattern LSA may have a first sidewall S3A and a second sidewall S3B, the first sidewall S3A facing one end E2 of each of the plurality of second fin-type active areas F2, the second sidewall S3B facing the dummy gate structure DGA. The upper insulation pattern USA may have an upper surface at a height higher than that of each of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2. According to some embodiments, the device isolation layer 112 and the lower insulation pattern LSA may be integrally formed with each other. In the width direction (X direction) of the logic unit LC3, the width of the upper insulation pattern USA may be greater than the width of the lower insulation pattern LSA. Although the upper insulation pattern USA has a flat upper surface in fig. 6B and 6C, the inventive concept is not limited thereto. According to some embodiments, the upper surface of the upper insulation pattern USA may have a rounded profile protruding upward.

Since the uppermost surface vertical height LV5 of the second fin-separation insulating portion FS2A is higher than the uppermost surface vertical height LVF of the second fin-type active region F2 and the upper surface of the dummy gate structure DGA extends flatly over the uppermost surface vertical heights LVG of the plurality of gate structures GS, the portion of the dummy gate structure DGA located on the second fin-separation insulating portion FS2A may have a smaller thickness than other portions of the dummy gate structure DGA.

According to some embodiments, the lower insulation pattern LSA and the upper insulation pattern USA included in the second fin partition insulation portion FS2A may be integrally connected to each other, or may be formed independently of each other but may contact each other. Each of the lower insulation pattern LSA and the upper insulation pattern USA included in the second fin partition insulation portion FS2A may include a single insulation layer or a plurality of insulation layers. For example, each of the upper insulation pattern USA and the lower insulation pattern LSA may include a silicon oxide layer, a silicon nitride layer, an SiOCN layer, a SiCN layer, or a combination thereof.

Although the second fin partition insulating portion FS2A has a flat lower surface in fig. 6B and 6C, the inventive concept is not limited thereto. According to some embodiments, the lower surface of the second fin partition insulating portion FS2A may include a curved surface included in a portion of a circle or a portion of an ellipse. According to some further embodiments, the lower surface of the second fin partition insulating portion FS2A may include a non-flat surface having a point sharply protruding toward the substrate 110.

Since the IC device 300 shown in fig. 5 and 6A to 6D includes the first and second fin partition insulating portions FS1 and FS2A (the first and second fin partition insulating portions FS1 and FS2 have different structures from each other around the cell boundary CB in the first and second device regions RX1 and RX2, respectively, of the logic cell LC 3), carrier mobility may be independently improved according to the conductivity type of each of the first and second device regions RX1 and RX2, the first and second device regions RX1 and RX2 include channel regions of different conductivity types from each other, and the active region area corresponding to the first width W1 of the first fin partition insulating portion FS1 may be further utilized in the second device region RX2 within the logic cell LC 3. Accordingly, while a stable fin separation region may be provided between transistors included in IC device 300, improved performance may be provided according to the channel type of each transistor, and the availability of active area within logic cell LC3 may be improved.

Fig. 7A and 7B are cross-sectional views for explaining an IC device 300A according to further embodiments of the inventive concepts. The IC device 300A of fig. 7A and 7B may have a planar layout as shown in fig. 5. Fig. 7A shows a sectional structure corresponding to a section taken along line X2-X2 'of fig. 5, and fig. 7B shows a sectional structure corresponding to a section taken along line Y1-Y1' of fig. 5. The same reference numerals and symbols of fig. 7A and 7B as those of fig. 2 to 6D denote the same elements, and thus their description will be omitted here.

Referring to fig. 7A and 7B, the IC device 300A includes a logic cell LC 3X. Logic cell LC3X may be one of the plurality of logic cells LC that make up cell block 12 of fig. 1. The logic cell LC3X has almost the same configuration as the logic cell LC3 described above with reference to fig. 6A to 6D. However, the logic cell LC3X includes the second fin partition insulating portion FS2B instead of the second fin partition insulating portion FS 2A. The second fin partition insulating portion FS2B extends in the second device region RX2 along the vertical boundary line VL of the cell boundary CB. The second fin partition insulating portion FS2B has almost the same configuration as the second fin partition insulating portion FS2A described above with reference to fig. 6A to 6D. However, an uppermost surface vertical height LV6 of the second fin partition insulating portion FS2B is lower than uppermost surface vertical heights LVF of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2. According to some embodiments, the uppermost surface vertical height LV6 of the second fin partition insulating portion FS2B may be the same as or similar to the uppermost surface vertical height LV3 of the first fin partition insulating portion FS 1. The second fin partition insulating portion FS2B may include a silicon oxide layer, a silicon nitride layer, a SiOCN layer, a SiCN layer, or a combination thereof.

The plurality of gate structures GS may include dummy gate structures DGB overlapping the vertical boundary lines VL of the cell boundary CB. The dummy gate structure DGB may include a portion disposed on the first fin partition insulating portion FS1 so as to vertically overlap the first fin partition insulating portion FS1 and a portion disposed on the second fin partition insulating portion FS2B so as to vertically overlap the second fin partition insulating portion FS 2B. A vertical direction (Z-direction) height of a portion of the dummy gate structure DGB disposed on the first fin partition insulating portion FS1 may be substantially equal to a vertical direction height of a portion of the dummy gate structure DGB disposed on the second fin partition insulating portion FS 2B. The detailed configuration of the dummy gate structure DGB is almost the same as that of the dummy gate structure DG described above with reference to fig. 2 and 3A to 3D.

Fig. 8 is a cross-sectional view for explaining an IC device 300B according to further embodiments of the inventive concepts. The IC device 300B of fig. 8 may have a planar layout as shown in fig. 5. Fig. 8 illustrates a sectional structure corresponding to a section taken along line X2-X2' of fig. 5. The same reference numerals and symbols in fig. 8 as those in fig. 2 to 7B denote the same elements, and thus their description will be omitted here.

Referring to fig. 8, the IC device 300B includes a logic cell LC 3Y. Logic cell LC3Y may be one of the plurality of logic cells LC that make up cell block 12 of fig. 1. The logic cell LC3Y has almost the same configuration as the logic cell LC3 described above with reference to fig. 6A to 6D. However, the logic cell LC3Y includes the second fin partition insulating portion FS2C instead of the second fin partition insulating portion FS 2A. The second fin partition insulating portion FS2C extends in the second device region RX2 along the vertical boundary line VL of the cell boundary CB. The second fin partition insulating portion FS2C has almost the same configuration as the second fin partition insulating portion FS2A described above with reference to fig. 6A to 6D. However, the uppermost surface vertical height LV7 of the second fin separation insulating portion FS2C is lower than the uppermost surface vertical heights LVF of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2, and is higher than the uppermost surface vertical height LV3 of the first fin separation insulating portion FS1 (see fig. 6A). The second fin partition insulating portion FS2C may include a silicon oxide layer, a silicon nitride layer, a SiOCN layer, a SiCN layer, or a combination thereof.

The plurality of gate structures GS may include dummy gate structures DGC overlapping the vertical boundary lines VL of the cell boundary CB. The dummy gate structure DGC may include a portion disposed on the first fin partition insulating portion FS1 so as to vertically overlap the first fin partition insulating portion FS1 and a portion disposed on the second fin partition insulating portion FS2C so as to vertically overlap the second fin partition insulating portion FS 2C. A vertical direction (Z-direction) height of a portion of the dummy gate structure DGC disposed on the second fin partition insulating portion FS2C may be less than a vertical direction height of a portion of the dummy gate structure DGC disposed on the first fin partition insulating portion FS 1. The detailed configuration of the dummy gate structure DGC is almost the same as that of the dummy gate structure DG described above with reference to fig. 2 and 3A to 3D.

Since the IC device 300A shown in fig. 7A and 7B includes the first fin separation insulating portion FS1 and the second fin separation insulating portion FS2B and the IC device 300B shown in fig. 8 includes the first fin separation insulating portion FS1 and the second fin separation insulating portion FS2C (the first fin separation insulating portion FS1 and the second fin separation insulating portion FS2B (or FS2C) have different structures from each other around the cell boundary CB in the first device region RX1 and the second device region RX2 of the logic cell LC3X (or LC 3Y)), carrier mobility may be independently improved according to the conductivity type of each of the channel regions in the first and second device regions RX1 and RX2, the first and second device regions RX1 and RX2 include channel regions of different conductivity types from each other, and an active area corresponding to the first width W1 of the first fin partition insulating portion FS1 may be further utilized in the second device region RX2 of each of the logic cells LC3X and LC 3Y. Accordingly, while a stable fin separation region may be provided between the transistors included in the IC devices 300A and 300B, improved performance may be provided according to the channel type of each transistor, and the availability of active regions within each of the logic cells LC3X and LC3Y may be improved.

Fig. 9 is a layout diagram for explaining an IC device 400 according to further embodiments of the inventive concepts. The same reference numerals and symbols in fig. 9 as those in fig. 5 and 6A to 6D denote the same elements, and thus their description will be omitted here.

Referring to fig. 9, the IC device 400 includes a logic cell LC4, and a logic cell LC4 has an area defined by a cell boundary CB. The logic cell LC4 may be one of the plurality of logic cells LC constituting the cell block 12 of fig. 1. The logic cell LC4 has almost the same configuration as the logic cell LC3 described above with reference to fig. 5 and 6A to 6D. However, the positions of the first device region RX1 and the first fin separation insulating portion FS1 in the logic cell LC4 are different from those in the logic cell LC3 of fig. 5. The configuration of the logic cell LC3 of fig. 5 and the configuration of the logic cell LC4 of fig. 9 may be symmetrical to each other about one of the pair of vertical boundary lines VL.

Fig. 10A is a plan layout view for explaining an IC device 500 according to further embodiments of the inventive concepts. The same reference numerals and symbols in fig. 10A as those in fig. 1 to 3D denote the same elements, and thus their description will be omitted here.

Referring to fig. 10A, the IC device 500 includes a first logic cell LC1A and a second logic cell LC1B, the first logic cell LC1A and the second logic cell LC1B being arranged adjacent to each other in the width direction (X direction) with a cell boundary contact portion CBC therebetween. The IC device 500 may constitute the logic cell block 12 of fig. 1.

The first cell boundary CBA defining the area of the first logic cell LC1A and the second cell boundary CBB defining the area of the second logic cell LC1B may meet each other at the cell boundary contact portion CBC and may share the cell boundary contact portion CBC. Each of the first logic cell LC1A and the second logic cell LC1B may have substantially the same configuration as the logic cell LC1 described above with reference to fig. 2 and 3A through 3D.

The first fin partition insulating portion FS1 located within the first logic cell LC1A may have a first inner sidewall IW1 and a first outer sidewall OW1, the first inner sidewall IW1 facing the plurality of first fin-type active regions F1 formed in the first device region RX1 of the first logic cell LC1A, the first outer sidewall OW1 being aligned with the cell boundary contact portion CBC. The second fin partition insulating portion FS2 may overlap the cell boundary contact portion CBC and may extend along the cell boundary contact portion CBC in the Y direction. The second fin partition insulating portion FS2 may have a second inner sidewall IW2 and a second outer sidewall OW2, the second inner sidewall IW2 facing the plurality of second fin-type active regions F2 formed in the second device region RX2 of the first logic cell LC1A, the second outer sidewall OW2 being located within the second logic cell LC 1B.

Within the first logic cell LC1A, the first device region RX1 may include a first side SX1A and a second side SX1B opposite to each other in a width direction (X direction). The first side SX1A of the first device region RX1 is aligned with the first cell boundary CBA, and the second side SX1B of the first device region RX1 is spaced apart from the cell boundary contact portion CBC with the first fin separation insulating portion FS1 therebetween. Within the first logic cell LC1A, the second device region RX2 may include a first side SX2A and a second side SX2B opposite to each other in a width direction (X direction). The first side SX2A of the second device region RX2 may be aligned with the first cell boundary CBA, and the second side SX2B may be aligned with the cell boundary contact portion CBC.

The second logic cell LC1B is adjacent to the first logic cell LC1A in the width direction (X direction) with a cell boundary contact portion CBC, and has almost the same configuration as the first logic cell LC 1A. The first and second device regions RX1 and RX2 of the second logic cell LC1B may be referred to as adjacent first and second device regions RX1 and RX 2. One of a pair of opposite side faces of the adjacent first device region RX1 in the width direction (X direction) is aligned with the cell boundary contact portion CBC, and the other side face is spaced apart from the second cell boundary CBB.

The first device region RX1 of the first logic cell LC1A and the first device region RX1 of the second logic cell LC1B are aligned in a straight line in the X direction and spaced apart from each other with the first fin partition insulating portion FS1 therebetween. The second device region RX2 of the first logic cell LC1A and the adjacent second device region RX2 of the second logic cell LC1B are aligned in a line in the X direction and abut each other.

Fig. 10B is a plan layout view for explaining an IC device 600 according to further embodiments of the inventive concepts. The same reference numerals and symbols in fig. 10B as those in fig. 1 to 10A denote the same elements, and thus their description will be omitted here.

Referring to fig. 10B, the IC device 600 includes a first logic cell LC2A and a second logic cell LC2B, the first logic cell LC2A and the second logic cell LC2B being arranged adjacent to each other in the width direction (X direction) with a cell boundary contact portion CBC therebetween. The IC device 600 may constitute the logic cell block 12 of fig. 1.

Each of the first logic cell LC2A and the second logic cell LC2B may have substantially the same configuration as the logic cell LC2 described above with reference to fig. 4, and the IC device 600 may have substantially the same configuration as the IC device 500 of fig. 10A. However, in the IC device 600, the first side SX1A of the first device region RX1 located in the first logic cell LC2A may face the first fin partition insulating portion FS1, and the second side SX1B of the first device region RX1 may be aligned with the cell boundary contact portion CBC. The first fin partition insulating portion FS1 may have a first inner sidewall IW1 and a first outer sidewall OW1, the first inner sidewall IW1 facing the plurality of first fin-type active regions F1 formed in the first device region RX1 of the first logic cell LC1A, the first outer sidewall OW1 being aligned with the first cell boundary CBA. The first side SX1A of the first device region RX1 may be spaced apart from the first cell boundary CBA with the first fin separation insulating portion FS1 therebetween.

The second logic cell LC2B is adjacent to the first logic cell LC2A in the width direction (X direction) with a cell boundary contact portion CBC, and has almost the same configuration as the first logic cell LC 2A. The first and second device regions RX1 and RX2 of the second logic cell LC2B may be referred to as adjacent first and second device regions RX1 and RX 2.

One of a pair of opposite side surfaces of the first fin partition insulating portion FS1 in the width direction (X direction) of the second logic cell LC2B may be aligned with the cell boundary contact portion CBC, and the other side surface may abut the adjacent first device region RX 1. One of a pair of opposite side surfaces of the adjacent first device region RX1 in the width direction (X direction) of the second logic cell LC2B is spaced apart from the cell boundary contact portion CBC with the first fin partition insulating portion FS1 therebetween, and the other side surface is aligned with the second cell boundary CBB.

Fig. 11A is a plan layout view for explaining an IC device 700 according to further embodiments of the inventive concepts. The same reference numerals and symbols in fig. 11A as those in fig. 1 to 10B denote the same elements, and thus their description will be omitted here.

Referring to fig. 11A, the IC device 700 includes a first logic cell LC3A and a second logic cell LC3B, the first logic cell LC3A and the second logic cell LC3B being arranged adjacent to each other in the width direction (X direction) with a cell boundary contact portion CBC therebetween. The IC device 700 may constitute the logic cell block 12 of fig. 1.

The first cell boundary CBA defining the area of the first logic cell LC3A and the second cell boundary CBB defining the area of the second logic cell LC3B may meet each other at the cell boundary contact portion CBC and may share the cell boundary contact portion CBC. Each of the first logic cell LC3A and the second logic cell LC3B may have substantially the same configuration as the logic cell LC3 described above with reference to fig. 5 and 6A through 6D.

The first fin partition insulating portion FS1 located within the first logic cell LC3A may have a first inner sidewall IW1 and a first outer sidewall OW1, the first inner sidewall IW1 facing the plurality of first fin-type active regions F1 formed in the first device region RX1 of the first logic cell LC3A, the first outer sidewall OW1 being aligned with the cell boundary contact portion CBC. The second fin partition insulating portion FS2 may overlap the cell boundary contact portion CBC and may extend along the cell boundary contact portion CBC in the Y direction. The second fin partition insulating portion FS2 may have a second inner sidewall IW2 and a second outer sidewall OW2, the second inner sidewall IW2 facing the plurality of second fin-type active regions F2 formed in the second device region RX2 of the first logic cell LC3A, the second outer sidewall OW2 being located within the second logic cell LC 3B.

In the first logic cell LC3A, the first side SX1A of the first device region RX1 is aligned with the first cell boundary CBA, and the second side SX1B of the first device region RX1 is spaced apart from the cell boundary contact portion CBC with the first fin partition insulating portion FS1 therebetween. In the first logic cell LC3A, the first side SX2A of the second device region RX2 may be aligned with the first cell boundary CBA, and the second side SX2B may be aligned with the cell boundary contact portion CBC.

The second logic cell LC3B is adjacent to the first logic cell LC3A in the width direction (X direction) with a cell boundary contact portion CBC, and has almost the same configuration as the first logic cell LC 3A. The first and second device regions RX1 and RX2 of the second logic cell LC3B may be referred to as adjacent first and second device regions RX1 and RX 2. One of a pair of opposite side faces of the adjacent first device region RX1 in the width direction (X direction) is aligned with the cell boundary contact portion CBC, and the other side face is spaced apart from the second cell boundary CBB.

Fig. 11B is a plan layout view for explaining an IC device 800 according to further embodiments of the inventive concepts. The same reference numerals and symbols in fig. 11B as those in fig. 1 to 11A denote the same elements, and thus their description will be omitted here.

Referring to fig. 11B, the IC device 800 includes a first logic cell LC4A and a second logic cell LC4B, the first logic cell LC4A and the second logic cell LC4B being arranged adjacent to each other in the width direction (X direction) with a cell boundary contact portion CBC therebetween. The IC device 800 may constitute the logic cell block 12 of fig. 1.

Each of the first logic cell LC4A and the second logic cell LC4B may have substantially the same configuration as the logic cell LC4 described above with reference to fig. 9, and the IC device 800 may have substantially the same configuration as the IC device 700 of fig. 11A. However, in the IC device 800, the first side SX1A of the first device region RX1 located in the first logic cell LC4A may face the first fin partition insulating portion FS1, and the second side SX1B of the first device region RX1 located in the first logic cell LC4A may be aligned with the cell boundary contact portion CBC. The first fin partition insulating portion FS1 may have a first inner sidewall IW1 and a first outer sidewall OW1, the first inner sidewall IW1 facing the plurality of first fin-type active regions F1 formed in the first device region RX1 of the first logic cell LC4A, the first outer sidewall OW1 being aligned with the first cell boundary CBA. The first side SX1A of the first device region RX1 may be spaced apart from the first cell boundary CBA with the first fin separation insulating portion FS1 therebetween.

The second logic cell LC4B is adjacent to the first logic cell LC4A in the width direction (X direction) with a cell boundary contact portion CBC, and has almost the same configuration as the first logic cell LC 4A. The first and second device regions RX1 and RX2 of the second logic cell LC4B may be referred to as adjacent first and second device regions RX1 and RX 2.

One of a pair of opposite side surfaces of the first fin partition insulating portion FS1 in the width direction (X direction) of the second logic cell LC4B may be aligned with the cell boundary contact portion CBC, and the other side surface may abut the adjacent first device region RX 1. One of a pair of opposite side surfaces of the adjacent first device region RX1 in the width direction (X direction) of the second logic cell LC4B is spaced apart from the cell boundary contact portion CBC with the first fin partition insulating portion FS1 therebetween, and the other side surface is aligned with the second cell boundary CBB.

In an IC device including a plurality of logic cells adjacent to each other (like the IC devices 500, 600, 700, and 800 described above with reference to fig. 10A to 11B), even when the area of the logic cells is reduced due to scaling down, the fin separation insulating portions formed around the cell boundary contact portions CBC at which the logic cells meet each other adopt structures different from each other according to the respective channel types of transistors included in the IC device. Accordingly, while improved performance may be provided according to the channel type of each transistor in the logic cell, a stable fin separation region may be provided between the transistors. Also, the availability of active areas within each of the plurality of adjacent logic cells may be improved, and thus an IC device capable of providing improved performance may be obtained.

Fig. 12A to 19D are sectional views for explaining a method of manufacturing an IC device according to an embodiment of the inventive concept. More specifically, fig. 12A, 13A, …, and 19A are sectional structures according to process order of portions corresponding to a section taken along line X1-X1 'of fig. 2, fig. 12B, 13B, …, and 19B are sectional structures according to process order of portions corresponding to a section taken along line X2-X2' of fig. 2, fig. 12C, 13C, …, and 19C are sectional structures according to process order of portions corresponding to a section taken along line Y1-Y1 'of fig. 2, and fig. 12D, 13D, …, and 19D are sectional structures according to process order of portions corresponding to a section taken along line Y2-Y2' of fig. 2. A method of manufacturing the IC device 100 of fig. 2 and 3A to 3D will now be described with reference to fig. 12A to 19D. The same reference numerals and symbols in fig. 12A to 19D as those in fig. 2 and 3A to 3D denote the same elements, and thus their description will be omitted here.

Referring to fig. 12A to 12D, a plurality of first fin-type active regions F1 and a plurality of second fin-type active regions F2 are formed by etching some regions of the substrate 110 in the first device region RX1 and the second device region RX2, respectively, and device isolation layers 112 covering both sidewalls of a lower portion of each of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2 are formed.

The deep trench DT defining the first and second device regions RX1 and RX2 may be formed by etching a portion of the device isolation layer 112 and a portion of the substrate 110, and the device isolation region DTA may be formed to fill the deep trench DT. Since the plurality of first fin-type active regions F1 are formed in the first device region RX1, the first fin separation space SS1 may be provided on the main surface 110M of the substrate 110. A portion of the device isolation layer 112 filling the first fin partition space SS1 may be included in the first fin partition insulating portion FS 1.

Referring to fig. 13A to 13D, a plurality of dummy gate structures DGS each extending in the Y direction to be parallel to each other are formed over the first fin separation insulating portion FS1, the device isolation layer 112, the device isolation region DTA, and the plurality of first and second fin-type active regions F1 and F2. Each of the plurality of dummy gate structures DGS may include a dummy gate insulating layer D12, a dummy gate line D14 and a dummy gate insulating cap layer D16 stacked on the plurality of first fin-shaped active regions F1 and the plurality of second fin-shaped active regions F2 in the order set forth. The dummy gate insulating layer D12 may include silicon oxide. The dummy gate line D14 may include polysilicon. The dummy gate insulating cap layer D16 may include silicon nitride. Some of the plurality of dummy gate structures DGS may cover the first fin separation insulating portion FS 1. The first insulation spacers 120 may be formed on both sidewalls of the dummy gate structure DGS.

The plurality of recesses 124R may be formed by partially etching the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2 at both sides of the dummy gate structure DGS, and the plurality of source/drain regions 124 may be formed by forming a semiconductor layer from the inner walls of the plurality of recesses 124R by an epitaxial growth process. According to some embodiments, the first device region RX1 may be an NMOS transistor region and the second device region RX2 may be a PMOS transistor region. In this case, the plurality of source/drain regions 124 on the first device region RX1 may include an epitaxially grown Si layer or an epitaxially grown SiC layer, and the plurality of source/drain regions 124 on the second device region RX2 may include a plurality of epitaxially grown SiGe layers.

An inter-gate insulating layer 128 covering the first fin partition insulating portion FS1, the device isolation layer 112, and the plurality of source/drain regions 124 may be formed between the plurality of dummy gate structures DGS.

Referring to fig. 14A to 14D, the dummy gate insulating cap layer D16 and the insulating layer therearound are removed from the product of fig. 13A to 13D by Chemical Mechanical Polishing (CMP), thereby exposing the dummy gate line D14 and reducing the height of the inter-gate insulating layer 128 and the plurality of first insulating spacers 120.

Referring to fig. 15A to 15D, a mask pattern M1 having an opening OP1 is formed on the product of fig. 14A to 14D. The mask pattern M1 may include silicon nitride, silicon oxide, or a combination thereof. A portion of the dummy gate line D14 corresponding to the second fin partition insulating portion FS2 (refer to fig. 2) on the second device region RX2 may be exposed through the opening OP1 of the mask pattern M1.

The dummy gate line D14 exposed through the opening OP1 of the mask pattern M1 is selectively removed by using the mask pattern M1 as an etching mask, and thus the exposed dummy gate insulating layer D12 is removed. Next, the second fin separation space SS2 is formed by etching portions of the plurality of second fin-type active regions F2 exposed by the opening OP1 on the second device region RX 2.

When the dummy gate line D14, the dummy gate insulating layer D12, and the plurality of second fin-type active regions F2 are being etched to form the second fin-separating space SS2, the first insulating spacers 120, which are exposed to the etching atmosphere together through the opening OP1, may also be partially consumed, and thus, the plurality of second insulating spacers 122 may be formed as a result of reducing the height of the first insulating spacers 120.

Referring to fig. 16A to 16D, an isolation insulating layer (not shown) fills the second fin isolation space SS2 formed by depositing an insulating material on the product of fig. 15A to 15D, and then the mask pattern M1 and unnecessary portions of the isolation insulating layer are removed until the upper surface of the inter-gate insulating layer 128 is exposed. As a result, the second fin partition insulating portion FS2 may be obtained, the second fin partition insulating portion FS2 having a portion of the isolation insulating layer filling the second fin partition space SS 2. The second fin partition insulating portion FS2 may include an upper insulating portion US and a lower insulating portion LS integrally connected to each other.

Referring to fig. 17A to 17D, a plurality of gate structure spaces GA are prepared on the first and second device regions RX1 and RX2 by removing the plurality of dummy gate lines D14 and the plurality of dummy gate insulating layers D12 under the plurality of dummy gate lines D14 from the product of fig. 16A to 16D.

Referring to fig. 18A to 18D, a gate insulating layer 132 and a gate line GL filling a portion of each of the plurality of gate structure spaces GA are formed on the resultant of fig. 17A to 17D. In the gate structure space GA, the cap space CS may remain on the gate line GL.

According to some embodiments, an interfacial layer (not shown) may be formed on a surface of each of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2 exposed through the plurality of gate structure spaces GA before forming the gate insulating layer 132. The interfacial layer may be obtained by oxidizing a portion of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2.

Referring to fig. 19A to 19D, the plurality of gate insulating capping layers 140 filling the plurality of cap spaces CS are formed on the product of fig. 18A to 18D.

A cap insulating layer thick enough to fill each of the plurality of cap spaces CS may be formed over the substrate 110 to form each of the gate insulating capping layers 140, and then an unnecessary portion of the cap insulating layer may be removed to expose an upper surface of each of the inter-gate insulating layer 128 and the second fin partition insulating portion FS 2.

Next, an upper insulating cap layer 150 and an interlayer insulating layer 170 may be formed on the resultant of fig. 19A to 19D, thereby manufacturing the IC device 100 shown in fig. 2 and 3A to 3D.

Fig. 20A to 20D are sectional views for explaining methods of manufacturing an IC device according to further embodiments of the inventive concepts. Specifically, fig. 20A to 20D are sectional structures of portions corresponding to the sections taken along the line X2-X2' of fig. 5 in the process order. A method of manufacturing the IC device 300 of fig. 5 and 6A to 6D will now be described with reference to fig. 20A to 20D. The same reference numerals and symbols in fig. 20A to 20D as those in fig. 5 and 6A to 6D denote the same elements, and thus their description will be omitted here.

Referring to fig. 20A, similar to the method described above with reference to fig. 12A through 12D, the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2 are formed by etching certain regions of the substrate 110 in the first device region RX1 and the second device region RX2, respectively, and the fin isolation trench FST is formed by partially etching each of the plurality of second fin-type active regions F2 on the second device region RX 2.

Referring to fig. 20B, an isolation insulating layer 112A is formed to fill the fin isolation trench FST. The isolation insulating layer 112A may be an insulating layer for forming the device isolation layer 112 described above with reference to fig. 12A to 12D. The isolation insulating layer 112A may be formed to fill spaces between the plurality of first fin-type active regions F1 on the first device region RX1 and between the plurality of second fin-type active regions F2 on the second device region RX2 (see fig. 5 and 6A to 6D).

Referring to fig. 20C, a mask pattern M2 having an opening OP2 is formed on the product of fig. 20B, the opening OP2 partially exposing the isolation insulating layer 112A and the plurality of second fin-type active regions F2 around the isolation insulating layer 112A. The mask pattern M2 may be formed to cover the plurality of first fin-type active regions F1, the plurality of second fin-type active regions F2, and an isolation insulating layer 112A filling spaces between the plurality of first fin-type active regions F1 on the first device region RX1 and between the plurality of second fin-type active regions F2 on the second device region RX2 (see fig. 5 and 6A to 6D). The mask pattern M2 may include a material having an etch selectivity with respect to the isolation insulating layer 112A. For example, the mask pattern M2 may include a nitride layer, a spin on hard mask (SOH) layer, or a combination thereof.

The recess region RR is formed by partially etching the isolation insulating layer 112A and the plurality of second fin-type active regions F2 around the isolation insulating layer 112A to a certain thickness using the mask pattern M2 as an etch mask. After the formation of the recess region RR, a portion of the isolation insulation layer 112A remaining in the fin isolation trench FST may be included in the lower insulation pattern LSA.

An upper insulating layer 112B is formed, and the upper insulating layer 112B fills the openings OP2 of the recess regions RR and the mask pattern M2. The upper insulating layer 112B may include the same material as that included in the isolation insulating layer 112A or a material different from that included in the isolation insulating layer 112A.

Referring to fig. 20D, the mask pattern M2 is removed from the product of fig. 20C, thereby exposing the plurality of first fin-type active regions F1, the plurality of second fin-type active regions F2, and an isolation insulating layer 112A (not shown), the isolation insulating layer 112A filling spaces between the plurality of first fin-type active regions F1 on the first device region RX1 and between the plurality of second fin-type active regions F2 on the second device region RX2 (see fig. 5 and 6A to 6D). Thereafter, the device isolation layer 112 of fig. 6D covering both sidewalls of the lower portion of each of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2 is formed by etching each of the isolation insulating layer 112A and the upper insulating layer 112B exposed over the substrate 110 from the upper surface thereof to a certain thickness such that respective upper portions of the plurality of first fin-type active regions F1 and the plurality of second fin-type active regions F2 are exposed, and at the same time, an upper insulating pattern USA including a remaining portion of the upper insulating layer 112B is formed. The lower insulation pattern LSA and the upper insulation pattern USA may be included in the second fin partition insulation portion FS 2A. A portion of the device isolation layer 112 may be included in the first fin partition insulating portion FS1 of fig. 6A and 6C.

Then, processes similar to those described above with reference to fig. 13A to 19D may be performed, and thus the IC device 300 of fig. 5 and 6A to 6D may be manufactured.

The IC device 300A of fig. 7A and 7B and the IC device 300B of fig. 8 may be formed using a method similar to that described above with reference to fig. 20A through 20D. However, after the fin isolation trench is formed on the substrate through a process similar to the process of forming the fin isolation trench FST with reference to fig. 20A, the second fin partition insulating portion FS2B or the second fin partition insulating portion FS2C may be formed within the fin isolation trench in a method similar to the process of forming the isolation insulating layer 112A with reference to fig. 20B. Processes similar to those described above with reference to fig. 13A to 19D may be performed, and thus the IC device 300 of fig. 5 and 6A to 6D may be manufactured. Although example methods of manufacturing some IC devices according to the inventive concepts have been described with reference to fig. 12A through 20D, other IC devices having various structures may be implemented in various methods corresponding to modifications made to the example methods described above without departing from the spirit of the inventive concepts.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

This application claims the benefit of korean patent application No. 10-2018-0098759, filed in the korean intellectual property office at 23.8.2018, the disclosure of which is hereby incorporated by reference in its entirety.