阅读说明：本技术 一种半导体结构及其制作方法 (Semiconductor structure and manufacturing method thereof ) 是由 吴玉雷 吴保磊 王晓光 平尔萱 于 2020-04-16 设计创作，主要内容包括：本发明实施例提供了一种半导体结构及其制作方法。其中半导体结构的制作方法包括：提供衬底；在所述衬底上形成第一屏蔽层；形成贯穿所述第一屏蔽层的第一电极；在所述第一电极上形成存储结构；在所述存储结构的顶部和侧壁形成第二屏蔽层,所述第一屏蔽层与所述第二屏蔽层共同构成屏蔽层；形成贯穿所述屏蔽层且与所述存储结构电连接的第二电极。本发明中,通过先形成第一屏蔽层,然后再依次形成第一电极、存储结构和第二屏蔽层,所述第一屏蔽层和所述第二屏蔽层形成包覆所述存储结构的屏蔽层,可更好的屏蔽外部电磁场对所述存储结构的干扰,确保信息能够被正确存储以及读写。(The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming a first shielding layer on the substrate; forming a first electrode through the first shielding layer; forming a storage structure on the first electrode; forming a second shielding layer on the top and the side wall of the storage structure, wherein the first shielding layer and the second shielding layer jointly form a shielding layer; a second electrode is formed through the shielding layer and electrically connected to the memory structure. According to the invention, the first shielding layer is formed firstly, and then the first electrode, the storage structure and the second shielding layer are sequentially formed, wherein the first shielding layer and the second shielding layer form the shielding layer for coating the storage structure, so that the interference of an external electromagnetic field on the storage structure can be better shielded, and the information can be ensured to be correctly stored and read and written.)

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate;

forming a first shielding layer on the substrate;

forming a first electrode through the first shielding layer;

forming a storage structure on the first electrode;

forming a second shielding layer on the top and the side wall of the storage structure, wherein the first shielding layer and the second shielding layer jointly form a shielding layer;

a second electrode is formed through the shielding layer and electrically connected to the memory structure.

2. The method of claim 1, wherein the memory structure comprises a magnetic layer stack structure.

3. The method of fabricating a semiconductor structure according to claim 2, wherein the step of forming a first electrode through the first shielding layer comprises:

forming a first dielectric layer on the first shielding layer;

forming a first opening in the first shielding layer and the first dielectric layer;

forming the first electrode in the first opening.

4. The method of fabricating a semiconductor structure according to claim 3, wherein before forming the second shielding layer on the top and sidewalls of the memory structure, further comprising:

and forming a second dielectric layer covering the top and the side wall of the magnetic layer stacking structure, wherein the first dielectric layer and the second dielectric layer jointly form an isolation layer.

5. The method of claim 4, wherein a material of the first shield layer and the second shield layer comprises a conductive material and/or a permeable material.

6. The method of fabricating a semiconductor structure of claim 5, comprising:

the first shielding layer and the second shielding layer are made of different materials;

removing the first shielding layer except the part below the second shielding layer on the side wall of the magnetic layer stacking structure by utilizing a self-aligned etching process;

the first and second shield layers remaining below the second shield layer on the magnetic layer stack structure sidewalls form the shield layer.

7. The method of claim 6, wherein a bottom of the shielding layer is lower than a bottom of the magnetic layer stack.

8. The method of fabricating a semiconductor structure according to claim 4,

the top of the magnetic layer stack structure is arc-shaped.

9. The method of claim 4, wherein a lateral dimension of the magnetic layer stack is greater than a lateral dimension of the first electrode.

10. The method of claim 8, wherein the step of forming a second electrode through the mask layer and electrically connected to the memory structure comprises:

forming a third dielectric layer on the substrate and the shielding layer;

removing a portion of the shielding layer over the magnetic layer stack structure using a grinding process to expose a top of the magnetic layer stack structure;

forming a fourth dielectric layer on the top of the magnetic layer stacking structure;

forming a second opening in the fourth dielectric layer to expose the top of the magnetic layer stack structure;

and forming the second electrode in the second opening.

11. A semiconductor structure, comprising:

a substrate;

a first electrode located within the substrate;

a storage structure on the first electrode;

a shielding layer covering the top and the side walls of the storage structure, wherein the bottom of the shielding layer is lower than the bottom of the storage structure; and

and the second electrode penetrates through the shielding layer on the top of the storage structure and is electrically connected with the storage structure.

12. The semiconductor structure of claim 11, in which the memory structure comprises a magnetic layer stack structure.

13. The semiconductor structure of claim 12, wherein the magnetic layer stack structure comprises a fixed layer, a spacer layer, and a free layer.

14. The semiconductor structure of claim 13, wherein the material of the pinned layer and the free layer comprises Co, Fe, B, Ta, or Ru; the material of the spacing layer comprises Mg or O.

15. The semiconductor structure of claim 12, wherein a top of the magnetic layer stack is curved.

16. The semiconductor structure of claim 12, further comprising:

an isolation layer coated on the magnetic laminated structure;

the isolation layer comprises a first dielectric layer and a second dielectric layer;

the first dielectric layer is positioned between the shielding layer and the first electrode;

the second dielectric layer is located between the shielding layer and the magnetic laminated structure.

17. The semiconductor structure of claim 16, wherein a lateral dimension of the magnetic layer stack is greater than a lateral dimension of the first electrode.

18. The semiconductor structure of claim 17, wherein the shielding layer comprises a first shielding layer and a second shielding layer;

the first shielding layer is positioned between the first medium layer and the substrate, wherein one end part of the first shielding layer is positioned in a projection area of the magnetic layer stacking structure on the substrate;

the second shielding layer is located on the outer surface of the side wall of the first dielectric layer and the outer surface of the second dielectric layer.

19. The semiconductor structure of claim 18, in which a material of the first shield layer and the second shield layer comprises an electrically conductive material and/or a magnetically permeable material; the first shielding layer and the second shielding layer are made of different materials.

20. The semiconductor structure of claim 16, wherein a bottom of the second electrode is on a same level as a top surface of the magnetic layer stack, a top surface of the shield layer, and a top surface of the isolation layer.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.

Background

A Spin Transfer Torque (STT) Magnetic memory (MRAM) is a memory in which information is written by a spin current, and a core of a memory cell of the MRAM is a MTJ (Magnetic Tunnel Junction) including a Magnetic layer stack structure including a free layer, a spacer layer, and a pinned layer stacked from top to bottom, a first electrode on top of the free layer, and a second electrode on bottom of the pinned layer.

However, STT-MRAM is susceptible to interference from external electromagnetic fields, and current chip-level shielding is insufficient to completely shield against external electromagnetic fields.

Disclosure of Invention

The invention provides a semiconductor structure and a manufacturing method thereof, which are used for shielding interference of an external electromagnetic field.

The embodiment of the invention provides a manufacturing method of a semiconductor structure, which comprises the following steps:

providing a substrate;

forming a first shielding layer on the substrate;

forming a first electrode through the first shielding layer;

forming a storage structure on the first electrode;

forming a second shielding layer on the top and the side wall of the storage structure, wherein the first shielding layer and the second shielding layer jointly form a shielding layer;

a second electrode is formed through the shielding layer and electrically connected to the memory structure.

Optionally, the memory structure comprises a magnetic layer stack structure.

Optionally, the step of forming a first electrode penetrating through the first shielding layer includes:

forming a first dielectric layer on the first shielding layer;

forming a first opening in the first shielding layer and the first dielectric layer;

forming the first electrode in the first opening.

Optionally, before forming the second shielding layer on the top and the sidewall of the memory structure, the method further includes:

and forming a second dielectric layer covering the top and the side wall of the magnetic layer stacking structure, wherein the first dielectric layer and the second dielectric layer jointly form an isolation layer.

Optionally, the material of the first shielding layer and the second shielding layer includes an electrically conductive material and/or a magnetically permeable material.

Optionally, the method includes:

the first shielding layer and the second shielding layer are made of different materials;

removing the first shielding layer except the part below the second shielding layer on the side wall of the magnetic layer stacking structure by utilizing a self-aligned etching process;

the first and second shield layers remaining below the second shield layer on the magnetic layer stack structure sidewalls form the shield layer.

Optionally, the bottom of the shielding layer is lower than the bottom of the magnetic layer stack structure.

Optionally, the top of the magnetic layer stack structure is arc-shaped.

Optionally, a lateral dimension of the magnetic layer stack is larger than a lateral dimension of the first electrode.

Optionally, the step of forming a second electrode penetrating through the shielding layer and electrically connected to the storage structure includes:

forming a third dielectric layer on the substrate and the shielding layer;

removing a portion of the shielding layer over the magnetic layer stack structure using a grinding process to expose a top of the magnetic layer stack structure;

forming a fourth dielectric layer on the top of the magnetic layer stacking structure;

forming a second opening in the fourth dielectric layer to expose the top of the magnetic layer stack structure;

and forming the second electrode in the second opening.

An embodiment of the present invention further provides a semiconductor structure, including:

a substrate;

a first electrode located within the substrate;

a storage structure on the first electrode;

a shielding layer covering the top and the side walls of the storage structure, wherein the bottom of the shielding layer is lower than the bottom of the storage structure; and

and the second electrode penetrates through the shielding layer on the top of the storage structure and is electrically connected with the storage structure.

Optionally, the memory structure comprises a magnetic layer stack structure.

Optionally, the magnetic layer stack structure includes a fixed layer, a spacer layer, and a free layer.

Optionally, the material of the fixed layer and the free layer includes Co, Fe, B, Ta, or Ru; the material of the spacing layer comprises Mg or O.

Optionally, the top of the magnetic layer stack structure is arc-shaped.

Optionally, the method further includes:

an isolation layer coated on the magnetic laminated structure;

the isolation layer comprises a first dielectric layer and a second dielectric layer;

the first dielectric layer is positioned between the shielding layer and the first electrode;

the second dielectric layer is located between the shielding layer and the magnetic laminated structure.

Optionally, a lateral dimension of the magnetic layer stack is larger than a lateral dimension of the first electrode.

Optionally, the shielding layer includes a first shielding layer and a second shielding layer;

the first shielding layer is positioned between the first medium layer and the substrate, wherein one end part of the first shielding layer is positioned in a projection area of the magnetic layer stacking structure on the substrate;

the second shielding layer is located on the outer surface of the side wall of the first dielectric layer and the outer surface of the second dielectric layer.

Optionally, the material of the first shielding layer and the second shielding layer includes an electrically conductive material and/or a magnetically permeable material; the first shielding layer and the second shielding layer are made of different materials.

Optionally, the bottom of the second electrode is on the same level with the top surface of the magnetic layer stack structure, the top surface of the shielding layer, and the top surface of the isolation layer.

In summary, embodiments of the present invention provide a semiconductor structure and a method for fabricating the same. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming a first shielding layer on the substrate; forming a first electrode through the first shielding layer; forming a storage structure on the first electrode; forming a second shielding layer on the top and the side wall of the storage structure, wherein the first shielding layer and the second shielding layer jointly form a shielding layer; a second electrode is formed through the shielding layer and electrically connected to the memory structure. According to the invention, the first shielding layer is formed firstly, and then the first electrode, the storage structure and the second shielding layer are sequentially formed, wherein the first shielding layer and the second shielding layer form the shielding layer for coating the storage structure, so that the interference of an external electromagnetic field on the storage structure can be better shielded, and the information can be ensured to be correctly stored and read and written.

Drawings

Fig. 1 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;

FIGS. 2-11 are schematic structural diagrams illustrating a process for forming a semiconductor structure according to an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of a semiconductor structure according to another embodiment of the present invention;

fig. 14 is a schematic structural diagram of a semiconductor structure according to yet another embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as broadly as the present invention is capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Referring to fig. 1, an embodiment of the invention provides a method for manufacturing a semiconductor structure, including:

step S110, providing a substrate 100;

step S120 of forming a first shielding layer 200a on the substrate 100;

step S130, forming a first electrode 400 penetrating the first shielding layer 200 a;

step S140, forming a memory structure 500 on the first electrode 400;

step S150, forming a second shielding layer 200b on the top and the sidewall of the memory structure 500, where the first shielding layer 200a and the second shielding layer 200b together form a shielding layer 200;

step S160, forming a second electrode 600 penetrating the shielding layer 200 and electrically connected to the memory structure 500.

In the invention, the first shielding layer 200a is formed first, then the first electrode 400, the storage structure 500 and the second shielding layer 200b are formed in sequence, and the first shielding layer 200a and the second shielding layer 200b form the shielding layer 200 covering the storage structure 500, so that the interference of an external electromagnetic field on the storage structure can be better shielded, and the information can be ensured to be correctly stored and read and written.

In order to describe the technical solution more clearly, each manufacturing process is described in detail below according to the manufacturing flow.

In this embodiment, step S110 is performed to provide a substrate 100. The substrate 100 may be a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate, but not limited thereto, and any substrate known to those skilled in the art for supporting components of a semiconductor integrated circuit may be used. The substrate 100 may contain device structures such as semiconductor transistors and plugs connecting the semiconductor transistors.

Referring to fig. 2, step S120 is performed to form a first shielding layer 200a on the substrate 100.

A shield material is deposited on the substrate 100 through a deposition process to form a first shield layer 200a covering a surface of the substrate 100. In this embodiment, the deposition process includes Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like. The shielding material can be a material with good conductivity, such as silver, copper, gold and the like, and can play a good shielding role on an electric field; the shielding material may also be a material with good magnetic permeability, such as alloys including iron (Fe), cobalt (Co), and nickel (Ni), e.g., cofe, ferronickel, and nickel-cobalt-iron, other alloys with higher magnetic permeability such as various combinations of NiFe and Co, doped amorphous ferromagnetic alloys, and the like. It should be noted that the material with good conductivity may also play a certain role in shielding a magnetic field, and the material with good magnetic permeability may also play a certain role in shielding an electric field.

Optionally, referring to fig. 3, a first dielectric layer 300a is further formed on the first shielding layer 200 a. Specifically, a dielectric material, such as silicon nitride, silicon oxide, or silicon oxynitride, is deposited on the first shielding layer 200a by a deposition process to form a first dielectric layer 300a covering the first shielding layer 200 a. The first dielectric layer 300a may serve as a hard mask for patterning the first shielding layer 200a and also as a portion of an isolation layer between the first shielding layer 200a and a subsequently formed memory structure.

Referring to fig. 4, step S130 is performed to form a first electrode 400 penetrating through the first shielding layer 200 a. Specifically, a first opening (not shown in the figure) is formed in the first shielding layer 200a and the first dielectric layer 300a by using photolithography and etching processes; forming a first electrode layer in the first opening, wherein the first electrode layer fills the trench and covers the first dielectric layer 300a, and specifically, the first electrode layer is formed by utilizing physical vapor deposition, chemical vapor deposition or electroplating and other processes, and is a conductive material layer, such as a metal material layer with good conductivity, such as Al, W, Cu and the like; the first electrode layer covering the upper surface of the first dielectric layer 300a is removed to form the first electrode 400 in the first opening. Specifically, the first electrode layer covering the upper surface of the first dielectric layer 300a may be removed by using a back etching or chemical mechanical polishing process to form the first electrode 400.

Optionally, the top of the first electrode 400 is flush with the top of the first dielectric layer 300 a. It is understood that the top of the first electrode 400 is flush with the top of the first dielectric layer 300a, such that the bottom of the first shielding layer 200a is lower than the bottom of the subsequently formed memory structure, increasing the shielding margin.

Referring to fig. 5a and 5b, step S140 is performed to form a memory structure 500 on the first electrode 400.

Optionally, the memory structure 500 is a magnetic layer stack structure. Forming the magnetic layer stack structure specifically includes: as shown in fig. 5a, a first magnetic layer 530a, a spacer material layer 520a, and a second magnetic layer 510a are sequentially deposited on the substrate 100 on which the first electrode 400 is formed; then, as shown in fig. 5b, the first magnetic layer 530a, the spacer material layer 520a, and the second magnetic layer 510a are patterned using photolithography and etching processes to form a magnetic layer stack structure including the pinned layer 530, the spacer layer 520, and the free layer 510. Specifically, the first magnetic layer 530a and the second magnetic layer 510a are made of Co, Fe, B, Ta or Ru; the material of the spacer material layer 520a includes Mg or O. For example, the fixed layer 530 may be CoFeB, the spacer layer 520 may be a MgO layer, and the free layer 510 may be CoFeB.

Optionally, the number of the storage structures 500 and the number of the first electrodes 400 are multiple, and the first electrodes 400 are arranged in one-to-one correspondence with the storage structures 500; the first electrodes 400 are spaced apart on the substrate 100. The memory structures 500 have spaces between them.

Optionally, the top of the magnetic layer stack structure is arc-shaped. Specifically, the first magnetic layer 530a, the spacer material layer 520a and the second magnetic layer 510a are etched by an Ion Beam Etching (IBE) process to form the magnetic layer stack structure, and the top of the free layer 510 of the magnetic layer stack structure is arc-shaped, so that the distance between the tops of adjacent magnetic layer stack structures can be increased, the contact risk of the tops of adjacent magnetic layer stack structures can be reduced, and the product yield can be increased; and simultaneously, the filling of a subsequent third dielectric layer in the interval between the adjacent magnetic layer stacking structures is facilitated.

Referring to fig. 8, step S150 is performed to form a second shielding layer 200b on the top and the sidewall of the memory structure, and the first shielding layer 200a and the second shielding layer 200b together form a shielding layer 200. The method specifically comprises the following steps: a shield material is deposited on the memory structure by a deposition process to form a second shield layer 200b covering the top and sidewalls of the memory structure. The second shielding layer 200b is connected to the first shielding layer 200a to form the shielding layer 200 covering the memory structure 500. The deposition process includes Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like. The shielding material can be a material with good conductivity, such as silver, copper, gold and the like, and can play a good shielding role on an electric field; the shielding material may also be a material with good magnetic permeability, such as alloys including iron (Fe), cobalt (Co), and nickel (Ni), e.g., cofe, ferronickel, and nickel-cobalt-iron, other alloys with higher magnetic permeability such as various combinations of NiFe and Co, doped amorphous ferromagnetic alloys, and the like. It should be noted that the material with good conductivity may also play a certain role in shielding a magnetic field, and the material with good magnetic permeability may also play a certain role in shielding an electric field.

Optionally, the first shielding layer 200a and the second shielding layer 200b are made of different materials. For example, the first shielding layer 200a and the second shielding layer 200b are both made of materials with good magnetic permeability, but the first shielding layer 200a and the second shielding layer 200b are made of different materials, for example, the first shielding layer 200a is cobalt iron, and the second shielding layer 200b is nickel iron; or the first shielding layer 200a and the second shielding layer 200b are both made of materials with good conductivity, but the first shielding layer 200a and the second shielding layer 200b are made of different materials, for example, the first shielding layer 200a is made of silver, and the second shielding layer 200b is made of copper; alternatively, the first shielding layer 200a is made of a material with good conductivity, such as copper, and the second shielding layer 200b is made of a material with good magnetic permeability, such as nickel-iron. As shown in fig. 9, the first shielding layer 200a and the second shielding layer 200b have an etching selectivity, and the first shielding layer 200a on the sidewall of the magnetic layer stack structure except under the second shielding layer 200b is removed by self-aligned etching using the etching selectivity; the first shield layer 200a and the second shield layer 200b remaining under the second shield layer 200b on the sidewalls of the magnetic layer stack structure form the shield layer 200. The method can reduce the process steps and save the cost; meanwhile, by utilizing self-aligned etching, the overlay error generated by the photoetching process can be prevented, and the product yield is improved.

Optionally, referring to fig. 6 and fig. 7, before forming the second shielding layer on the top and the sidewalls of the memory structure, the method further includes: and forming a second dielectric layer 300b covering the top and the side wall of the magnetic layer stack structure, wherein the first dielectric layer 300a and the second dielectric layer 300b jointly form an isolation layer 300. The method specifically comprises the following steps: and depositing an isolation material, such as silicon oxide, silicon nitride or silicon oxynitride, by using a deposition process to form a second dielectric layer 300b covering the first dielectric layer 300a and the top and the side walls of the magnetic layer stack structure, and then removing the second dielectric layer 300b on the upper surface of the first dielectric layer 300a by using an etching process to form a second dielectric layer 300b only covering the top and the side walls of the magnetic layer stack structure. In this embodiment, referring to fig. 7, the first dielectric layer 300a and the second dielectric layer 300b are made of the same material, so that the first dielectric layer 300a and the second dielectric layer 300b between adjacent magnetic layer stack structures can be removed by one etching process, and the first dielectric layer 300a and the second dielectric layer 300b on the top and the sidewall of the magnetic layer stack structure are remained. The first dielectric layer 300a and the second dielectric layer 300b together form an isolation layer 300. The spacer layer may release stress of the shielding layer 200 and isolate the shielding layer 200 and the magnetic layer stack structure.

Optionally, a lateral dimension of the magnetic layer stack is larger than a lateral dimension of the first electrode. Specifically, as shown in fig. 13, the dimension of the magnetic layer stack structure in the direction along the surface of the substrate 100 is greater than the dimension of the first electrode 400 in the direction along the surface of the substrate 100, so that a part of the shielding layer 200 is also formed between the substrate 100 and the magnetic layer stack structure, and the formed shielding layer 200 also plays a certain shielding role at the bottom of the magnetic layer stack structure, thereby enhancing the shielding effect.

Referring to fig. 10 and 12, step S160 is performed to form a second electrode 600 penetrating through the shielding layer 200 and electrically connected to the memory structure. The method specifically comprises the following steps: forming a third dielectric layer 700 on the substrate 100 and the storage structure; forming a third opening 900 in the third dielectric layer 700 by photolithography and etching processes to expose a top portion of the storage structure 500; finally, the third opening 900 is filled with a conductive material, and the conductive material on the surface of the third dielectric layer 700 is removed by a back etching or mechanochemical grinding process to form the second electrode 600. The second electrode layer may be a metal material layer having good conductivity such as Al, W, Cu, or the like.

Alternatively, as shown in fig. 11 and 14, forming a second electrode penetrating through the shielding layer and electrically connected to the storage structure includes: the storage structure is a magnetic layer stack structure; the top of the magnetic layer stacking structure is arc-shaped; forming a third dielectric layer 700 on the substrate and the magnetic layer stack structure; removing a portion of the shielding layer over the magnetic layer stack structure using a grinding process to expose a top of the magnetic layer stack structure; forming a fourth dielectric layer 800 on top of the magnetic layer stack structure; forming a second opening (not shown) in the fourth dielectric layer 800 to expose the top of the magnetic layer stack; the second electrode 600 is formed in the second opening. The manufacturing process can be simplified by removing part of the shielding layer above the magnetic layer stacking structure by using a grinding process to expose the top of the magnetic layer stacking structure, and meanwhile, when the second opening is formed subsequently, the shielding layer and the isolation layer do not need to be etched, so that the damage to the magnetic layer stacking structure can be reduced; the arc-shaped top structure can prevent the isolating layer and the shielding layer outside the non-exposed area of the magnetic layer stacked structure from being removed when the top of the magnetic layer stacked structure is exposed by using a grinding process, so that the shielding effect is enhanced. In the present embodiment, the bottom of the second electrode 600 is on the same level with the top surface of the magnetic layer stack structure, the top surface of the shielding layer 200, and the top surface of the isolation layer 300.

Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor structure, please refer to fig. 12, where the semiconductor structure includes: a substrate 100, a first electrode 400, a memory structure 500, a shield layer 200, and a second electrode 600. Wherein a first electrode 400 is located within the substrate 100; a memory structure 500 is located on the first electrode 400; the shielding layer 200 covers the top and the side walls of the memory structure 500, and the bottom of the shielding layer 200 is lower than the bottom of the memory structure 500; a second electrode 600 penetrating the shielding layer 200 on the top of the memory structure 500 and electrically connected to the memory structure 500.

In the invention, the shielding layer 200 covers the storage structure 500, so that the interference of an external electromagnetic field to the storage structure 500 can be better shielded, and the information can be correctly stored and read and written. The substrate 100 may be a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate, but not limited thereto. The substrate 100 may contain device structures such as semiconductor transistors and plugs connecting the semiconductor transistors.

Optionally, the number of the storage structures 500, the number of the first electrodes 400, and the number of the second electrodes 600 are all multiple, the first electrodes 400 and the second electrodes 600 are arranged in one-to-one correspondence with the storage structures 500, and intervals exist between the storage structures 500; the semiconductor structure further includes a third dielectric layer 700, where the third dielectric layer 700 is located on the substrate 100, fills the space between the memory structures 500, and is used to isolate two adjacent second electrodes 600 and two adjacent shielding layers 200. In this embodiment, the third dielectric layer 700 may be formed of a dielectric material such as silicon nitride, silicon oxide, or silicon oxynitride.

Optionally, the memory structure 500 is a magnetic layer stack structure. The magnetic layer stack structure includes at least a free layer 510, a spacer layer 520, and a fixed layer 530 stacked from top to bottom. Specifically, the material of the free layer 510 and the fixed layer 530 includes Co, Fe, B, Ta, or Ru; the material of the spacing layer comprises Mg or O. For example, the fixed layer 530 may be CoFeB, the spacer layer is a MgO layer, and the free layer 510 is CoFeB.

Optionally, the magnetic material further comprises an isolation layer 300, and the isolation layer 300 is coated on the magnetic laminated structure. Specifically, the isolation layer 300 includes a first dielectric layer 300a and a second dielectric layer 300 b; the first dielectric layer 300a is located between the shielding layer 200 and the first electrode 400; the second dielectric layer 300b is located between the shield layer 200 and the magnetic stack structure.

Optionally, the top of the magnetic layer stack structure is arc-shaped. As shown in fig. 12, the top of the magnetic layer stack structure is arc-shaped, and the top of the isolation layer 300 and the shielding layer 200 coated thereon are also arc-shaped. Specifically, the arc is an arc protruding outwards, and the top of the free layer 510 of the magnetic layer stacked structure is arc-shaped, so that the distance between the tops of adjacent magnetic layer stacked structures can be increased, the contact risk between the tops of adjacent magnetic layer stacked structures can be reduced, and the product yield can be increased; while also facilitating the filling of the third dielectric layer 700 in the spaces between adjacent magnetic layer stacks. In addition, as shown in fig. 14, the arc-shaped top structure may prevent the isolation layer 200 and the shielding layer 300 outside the unexposed region of the magnetic layer stack structure from being removed when the top of the magnetic layer stack structure is exposed by a grinding process, thereby enhancing the shielding effect.

Optionally, a lateral dimension of the magnetic layer stack is larger than a lateral dimension of the first electrode. As shown in fig. 13, the dimension of the magnetic layer stack structure in the direction along the surface of the substrate 100 is larger than the dimension of the first electrode 400 along the surface of the substrate 100, so that a part of the shielding layer 200 is also formed between the substrate 100 and the magnetic layer stack structure, i.e. a part of the shielding layer 200 is also formed at the bottom of the magnetic layer stack structure, and the shielding layer 200 also plays a certain role in shielding at the bottom of the magnetic layer stack structure, thereby enhancing the shielding effect.

Optionally, as shown in fig. 13, the shielding layer 200 includes a first shielding layer 200a and a second shielding layer 200 b; the first shielding layer 200a is located between the first dielectric layer 300a and the substrate 100, and one end of the first shielding layer 200a is located in a projection area of the magnetic layer stack structure on the substrate 100; the second shielding layer 200b is located on the outer surface of the sidewall of the first dielectric layer 300a and the outer surface of the second dielectric layer 300 b. The ends of the first shielding layer 200a and the second shielding layer 200b are connected to form the shielding layer 200 covering the top, the sidewall and a part of the bottom of the magnetic layer stack.

Optionally, the first shielding layer 200a and the second shielding layer 200b may be made of a material with good conductivity, such as silver, copper, gold, etc., which may have a good shielding effect on an electric field; the material of the first and second shield layers 200a and 200b may also be a material with good magnetic permeability, such as an alloy including iron (Fe), cobalt (Co) and nickel (Ni), such as cofe, ferronickel and nickel-cobalt-iron, other alloys with higher magnetic permeability such as NiFe and Co in various combinations, a doped amorphous ferromagnetic alloy, and the like. It should be noted that the material with good conductivity may also play a certain role in shielding a magnetic field, and the material with good magnetic permeability may also play a certain role in shielding an electric field.

Optionally, the first shielding layer 200a and the second shielding layer 200b are made of different materials. For example, the first shielding layer 200a and the second shielding layer 200b are both made of materials with good magnetic permeability, but the first shielding layer 200a and the second shielding layer 200b are made of different materials, for example, the first shielding layer 200a is cobalt iron, and the second shielding layer 200b is nickel iron; or the first shielding layer 200a and the second shielding layer 200b are both made of materials with good conductivity, but the first shielding layer 200a and the second shielding layer 200b are made of different materials, for example, the first shielding layer 200a is made of silver, and the second shielding layer 200b is made of copper; alternatively, the first shielding layer 200a is made of a material with good conductivity, such as copper, and the second shielding layer 200b is made of a material with good magnetic permeability, such as nickel-iron. As shown in fig. 9, the first shielding layer 200a and the second shielding layer 200b have an etching selectivity, and the first shielding layer 200a outside the sidewall of the first electrode 400 is removed by self-aligned etching using the etching selectivity; the first shielding layer 200a and the second shielding layer 200b remaining on the sidewalls of the first electrode 400 form the shielding layer 200. The method can reduce the process steps and save the cost; meanwhile, by utilizing self-aligned etching, the overlay error generated by the photoetching process can be prevented, and the product yield is improved.

Alternatively, as shown in fig. 14, the bottom of the second electrode 600 is on the same level with the top surface of the magnetic layer stack structure, the top surface of the shielding layer 200, and the top surface of the isolation layer 300. Specifically, as shown in fig. 11 and 14, the memory structure 500 is a magnetic layer stack structure; the top of the magnetic layer stacking structure is arc-shaped; forming a third dielectric layer 700 on the substrate 100 and the magnetic layer stack structure; removing a portion of the shielding layer 200 above the magnetic layer stack structure using a grinding process to expose a top portion of the magnetic layer stack structure; forming a fourth dielectric layer 800 on top of the magnetic layer stack structure; forming a second opening (not shown) in the fourth dielectric layer 800 to expose the top of the magnetic layer stack; the second electrode 600 is formed in the second opening. Removing part of the shielding layer 200 above the magnetic layer stack structure by using a grinding process to expose the top of the magnetic layer stack structure can simplify the manufacturing process, and simultaneously, when the second opening is formed subsequently, the shielding layer and the isolation layer do not need to be etched, so that the damage to the magnetic layer stack structure can be reduced; the arc-shaped top structure can prevent the isolation layer 300 and the shielding layer 200 outside the non-exposed region of the magnetic layer stack structure from being removed when the top of the magnetic layer stack structure is exposed by using a grinding process, thereby enhancing the shielding effect. In the present embodiment, the bottom of the second electrode 600 is on the same level with the top surface of the magnetic layer stack structure, the top surface of the shielding layer 200, and the top surface of the isolation layer 300.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.