N-time driving two-input NAND gate standard unit and layout thereof
阅读说明：本技术 n倍驱动两输入与非门标准单元及其版图 (N-time driving two-input NAND gate standard unit and layout thereof ) 是由 虞蓓蕾 高唯欢 胡晓明 于 2019-11-19 设计创作，主要内容包括：本发明涉及n倍驱动两输入与非门标准单元及其版图,涉及半导体集成电路设计,通过由两输入与门和n倍驱动反相器共同构成n倍驱动两输入与非门,其中n为大于等于2的偶数,其中n倍驱动反相器中的PMOS与NMOS晶体管的使用个数随驱动倍数增加,而两输入与门中的PMOS与NMOS晶体管的使用个数不变,因此减少了PMOS与NMOS晶体管的使用个数,从而减小n倍驱动两输入与非门单元的版图面积,并且节省晶体管个数与驱动倍数成正比,所以减小的面积与驱动倍数成正比。(The invention relates to an n-time driving two-input NAND gate standard unit and a layout thereof, relating to the design of a semiconductor integrated circuit, wherein the n-time driving two-input NAND gate is formed by two-input AND gates and an n-time driving inverter together, wherein n is an even number which is more than or equal to 2, the using number of PMOS and NMOS transistors in the n-time driving inverter is increased along with the driving multiple, and the using number of the PMOS and NMOS transistors in the two-input AND gates is unchanged, thereby reducing the using number of the PMOS and NMOS transistors, further reducing the layout area of the n-time driving two-input NAND gate unit, saving the number of the transistors which is in direct proportion to the driving multiple, and reducing the area which is in direct proportion to the driving multiple.)
1. An n-fold driving two-input NAND standard cell, comprising:
a two-input and gate for receiving a first input signal a1 and a second input signal a2, and outputting an intermediate output signal Sinter after performing and operation on the first input signal a1 and the second input signal a 2; and
and the n-time driving inverter receives the intermediate output signal Sinter and is used for outputting a final output signal Sf after performing an inversion operation on the intermediate output signal Sinter, wherein n is an even number which is more than or equal to 2.
2. The n-fold driven two-input nand gate standard cell of claim 1, wherein the two-input and gate comprises a first PMOS transistor PMOS1 and a first NMOS transistor NMOS 1.
3. The n-fold driving two-input nand gate standard cell of claim 2, wherein the source of the first PMOS transistor PMOS1 is grounded VSS, the gate of the first PMOS transistor PMOS1 is connected to the gate of the first NMOS transistor NMOS1 to form a first input terminal of the two-input and gate for receiving the first input signal a1, the drain of the first PMOS transistor PMOS1 is connected to the drain of the first NMOS transistor NMOS1 to form an output terminal of the two-input and gate for outputting the intermediate output signal Sinter, and the source of the first NMOS transistor NMOS1 forms a second input terminal of the two-input and gate for receiving the second input signal a 2.
4. The n-fold driven two-input nand gate standard cell of claim 1, wherein the two-input and gate comprises only the first PMOS transistor PMOS1 and the first NMOS transistor NMOS 1.
5. The n-fold driving two-input nand gate standard cell of claim 4, wherein the source of the first PMOS transistor PMOS1 is grounded VSS, the gate of the first PMOS transistor PMOS1 is connected to the gate of the first NMOS transistor NMOS1 to form a first input terminal of the two-input and gate for receiving the first input signal a1, the drain of the first PMOS transistor PMOS1 is connected to the drain of the first NMOS transistor NMOS1 to form an output terminal of the two-input and gate for outputting the intermediate output signal Sinter, and the source of the first NMOS transistor NMOS1 forms a second input terminal of the two-input and gate for receiving the second input signal a 2.
6. The n-fold driven two-input NAND standard cell as defined in any one of claims 3 or 5, wherein when the first input signal A1 is 0 and the second input signal A2 is 0, the first PMOS transistor PMOS1 is turned on, the first NMOS transistor NMOS1 is turned off, and the intermediate output signal Sinter is equal to the ground voltage VSS and equal to 0; when the first input signal a1 is 0 and the second input signal a2 is 1, the first PMOS transistor PMOS1 is turned on, the first NMOS transistor NMOS1 is turned off, and the intermediate output signal Sinter is equal to the ground voltage VSS and equal to 0; when the first input signal a1 is 1 and the second input signal a2 is 0, the first PMOS transistor PMOS1 is turned off, the first NMOS transistor NMOS1 is turned on, and the intermediate output signal Sinter is equal to the second input signal a2 and is equal to 0; when the first input signal a1 is 1 and the second input signal a2 is 1, the first PMOS transistor PMOS1 is turned off, the first NMOS transistor NMOS1 is turned on, and the intermediate output signal Sinter is equal to the second input signal a2 and is equal to 1.
7. The n-times driven two-input nand gate standard cell of claim 1, wherein the n-times driven inverter comprises a second PMOS transistor cell PMOS2 and a second NMOS transistor cell NMOS 2.
8. The n-fold driven two-input nand gate standard cell of claim 7, wherein the source of the second PMOS transistor unit PMOS2 is connected to the voltage terminal VDD, the drain of the second PMOS transistor unit PMOS2 is connected to the drain of the second NMOS transistor unit NMOS2 and forms the output terminal X of the n-fold driven two-input nand gate standard cell for outputting the final output signal Sf, the source of the second NMOS transistor unit NMOS2 is connected to the ground VSS, and the gate of the second NMOS transistor unit NMOS2 is connected to the gate of the second PMOS transistor unit PMOS2 and forms the input terminal of the n-fold driven inverter for receiving the intermediate output signal Sinter output from the two-input and gate.
9. The n-times driven two-input nand gate standard cell of claim 1, wherein the n-times driven inverter comprises only the second PMOS transistor cell PMOS2 and the second NMOS transistor cell NMOS 2.
10. The n-fold driven two-input nand gate standard cell of claim 9, wherein the source of the second PMOS transistor unit PMOS2 is connected to the voltage terminal VDD, the drain of the second PMOS transistor unit PMOS2 is connected to the drain of the second NMOS transistor unit NMOS2 and forms the output terminal X of the n-fold driven two-input nand gate standard cell for outputting the final output signal Sf, the source of the second NMOS transistor unit NMOS2 is connected to the ground VSS, and the gate of the second NMOS transistor unit NMOS2 is connected to the gate of the second PMOS transistor unit PMOS2 and forms the input terminal of the n-fold driven inverter for receiving the intermediate output signal Sinter output from the two-input and gate.
11. The n-fold driving two-input nand gate standard cell of any one of claims 7 or 9, wherein the second PMOS transistor unit PMOS2 comprises n PMOS transistors connected in parallel, and the second NMOS transistor unit NMOS2 comprises n NMOS transistors connected in parallel, where n is a driving multiple of the inverter and is an even number equal to or greater than 2.
12. The n-fold driven two-input nand gate standard cell of any one of claims 8 or 10, wherein when the intermediate output signal Sinter is 0, the second PMOS transistor unit PMOS2 is turned on, the second NMOS transistor unit NMOS2 is turned off, and the final output signal Sf is equal to the voltage terminal VDD and is equal to 1; when the intermediate output signal Sinter is 1, the second PMOS transistor unit PMOS2 is turned off, the second NMOS transistor unit NMOS2 is turned on, and the intermediate output signal Sinter is equal to the ground voltage VSS and equal to 0.
13. The n-fold driving nand gate standard cell as claimed in claim 1, wherein the n-fold driving nand gate standard cell uses transistors m being 2+2n, where n is a driving multiple of the two-input nand gate standard cell and is an even number greater than or equal to 2.
14. A layout of an n-time driving two-input NAND standard cell, the n-time driving two-input NAND standard cell comprises a two-input AND gate formed by a first PMOS transistor PMOS1 and a first NMOS transistor NMOS1, and an n-time driving inverter formed by a second PMOS transistor PMOS2 and a second NMOS transistor NMOS2, wherein the second PMOS transistor PMOS2 comprises n PMOS transistors which are connected in parallel, the second NMOS transistor NMOS2 comprises n NMOS transistors which are connected in parallel, wherein n is the driving multiple of the inverter and is an even number more than or equal to 2, the layout is characterized by comprising:
a first active region in which a first PMOS transistor PMOS1 is formed;
a second active region in which a first NMOS transistor NMOS1 is formed;
a third active region in which a second PMOS transistor cell PMOS2 is formed;
a fourth active region in which a second NMOS transistor cell NMOS2 is formed;
the gate structures of the first polysilicon, the first PMOS transistor PMOS1, and the first NMOS transistor NMOS1 are formed of the first polysilicon; and
the second polysilicon, the gate structures of the PMOS transistors of the n PMOS transistors in the second PMOS transistor unit PMOS2 and the NMOS transistors of the n NMOS transistors in the second NMOS transistor unit NMOS2 are formed by the second polysilicon.
15. The layout of the n-fold driving two-input nand gate standard cell as claimed in claim 14, wherein the first active region and the third active region are located in a row, the second active region and the fourth active region are located in a row, the first active region and the second active region are located in a column, and the third active region and the fourth active region are located in a column.
16. The layout of an n-fold driven two-input nand gate standard cell as claimed in claim 14, wherein the second polysilicon includes n vertical sides and a lateral side, the lateral side connecting the n vertical sides together to form the second polysilicon.
17. The layout of an n-times driven two-input nand standard cell of claim 16, wherein the gate structures of one of the n PMOS transistors in the second PMOS transistor unit PMOS2 and one of the n NMOS transistors in the second NMOS transistor unit NMOS2 are formed by one of n vertical sides.
18. The layout of an n-times driving two-input nand standard cell as claimed in claim 17, wherein the gate structures of one of the n PMOS transistors in the second PMOS transistor unit PMOS2 and one of the n NMOS transistors in the second NMOS transistor unit NMOS2 constitute a group of gate structures, the gate structures of the n PMOS transistors in the second PMOS transistor unit PMOS2 and the n NMOS transistors in the second NMOS transistor unit NMOS2 constitute n groups of gate structures, and each of the n groups of gate structures is formed by a corresponding one of the n vertical sides, respectively.
19. The layout of an n-fold driven two-input nand gate standard cell as claimed in claim 18, wherein the lateral edge is located in a spacing region between the third active region and the fourth active region.
20. The layout of an n-fold driven two-input nand gate standard cell as claimed in claim 16, wherein the n vertical edges are parallel to each other and to the first polysilicon.
21. The layout of an n-fold driven two-input NAND standard cell as claimed in any one of claims 14 to 20, wherein a first contact hole is formed in the first polysilicon, the first contact hole forming a common terminal between the gate of the first PMOS transistor PMOS1 and the gate of the first NMOS transistor NMOS1, forming a first input terminal of the n-fold driven two-input NAND standard cell for receiving the first input signal A1, a second contact hole is formed in the second active region, the second contact hole forming a source of the first NMOS transistor NMOS1, forming a second input terminal of the n-fold driven two-input NAND standard cell for receiving the second input signal A2, a third contact hole is formed in the first active region, the third contact hole forming a source of the first PMOS transistor 1, the third contact hole being connected to a ground terminal through a first metal wire, a fourth contact hole is formed in the first active region, a drain terminal of the first PMOS transistor PMOS1 is formed, a fifth contact hole is formed on the second active region, a drain terminal of the first NMOS transistor NMOS1 is formed, a fourth contact hole and a connection fifth contact hole are connected together by a second metal wire to form output terminals of the two-input AND gate, a sixth contact hole is formed on the second polysilicon to form a common connection terminal of the gates of the second PMOS transistor unit PMOS2 and the second NMOS transistor unit NMOS2 to form an input terminal of the n-fold drive inverter, the second metal wire is further connected with the sixth contact hole to connect the output terminals of the two-input AND gate to the input terminal of the n-fold drive inverter, n seventh contact holes are formed on the third active region to form source terminals of n PMOS transistors in the second PMOS transistor unit PMOS2, the n seventh contact holes are connected together by a third metal wire to connect the voltage terminal VDD, and n eighth contact holes are formed on the fourth active region, the n eighth contact holes constitute source terminals of the n NMOS transistors in the second NMOS transistor unit NMOS2, the n eighth contact holes being connected together by the first metal line to the ground terminal VSS; and a plurality of ninth contact holes are formed in the third active region, the plurality of ninth contact holes form drain terminals of n PMOS transistors in the second PMOS transistor unit PMOS2, a plurality of tenth contact holes are formed in the fourth active region, the plurality of tenth contact holes form drain terminals of n NMOS transistors in the second NMOS transistor unit NMOS2, and the plurality of ninth contact holes and the plurality of tenth contact holes are connected together through a third metal wire to form an output terminal X of the n-fold driving two-input NAND gate standard unit.
Technical Field
The invention relates to a semiconductor integrated circuit design, in particular to an n-fold driving two-input NAND gate standard unit and a layout thereof.
Background
A two-input NAND gate standard cell (NAND2) is a common standard cell in semiconductor integrated circuit designs.
Specifically, referring to the circuit diagram of the prior art two-input NAND standard cell shown in fig. 1, fig. 1 shows a two-input NAND standard cell (NAND2_2) with twice driving, which is composed of four PMOS transistors and four NMOS transistors (nf-2 represents 2 transistors connected in parallel). Wherein the sources of the first to fourth PMOS transistors (PMOS1 to PMOS4) are connected in parallel to VDD, the gates of the first and second PMOS transistors (PMOS1 and PMOS2) are connected to the first input signal A1, the gates of the third and fourth PMOS transistors (PMOS3 and PMOS4) are connected to the second input signal A2, the drains of the first to fourth PMOS transistors (PMOS1 to PMOS4) are connected, the drains of the first and second NMOS transistors (NMOS1 and NMOS2) are connected in parallel to form the output terminal X of the NAND2_2, the gates of the first and second NMOS transistors (NMOS1 and NMOS2) are connected in parallel to the first input signal a1, the sources of the first and second NMOS transistors (NMOS1 and NMOS2) are connected in parallel to the drains of the third and fourth NMOS transistors (NMOS3 and NMOS4), the gates of the third and fourth NMOS transistors (NMOS3 and NMOS4) are connected in parallel to the second input signal a2, and the sources of the third and fourth NMOS transistors (NMOS3 and NMOS4) are connected in parallel to VSS, thereby implementing the logic function of the
As shown in fig. 1, 8 transistors are required to implement the logic function of
Disclosure of Invention
The invention aims to provide a standard unit of a two-input NAND gate driven by n times so as to save the number of transistors and reduce the layout area.
The invention provides an n-time driving two-input NAND gate standard unit, which comprises: a two-input and gate for receiving a first input signal a1 and a second input signal a2, and outputting an intermediate output signal Sinter after performing and operation on the first input signal a1 and the second input signal a 2; and the n-time driving inverter receives the intermediate output signal Sinter and is used for outputting a final output signal Sf after performing inversion operation on the intermediate output signal Sinter, wherein n is an even number which is more than or equal to 2.
Further, the two-input and gate includes a first PMOS transistor PMOS1 and a first
Furthermore, the source of the first PMOS transistor PMOS1 is grounded VSS, the gate of the first PMOS transistor PMOS1 is connected to the gate of the first NMOS transistor NMOS1 to form a first input terminal of the two-input and gate for receiving the first input signal a1, the drain of the first PMOS transistor PMOS1 is connected to the drain of the first NMOS transistor NMOS1 to form an output terminal of the two-input and gate for outputting the intermediate output signal Sinter, and the source of the first NMOS transistor NMOS1 forms a second input terminal of the two-input and gate for receiving the second input signal a 2.
Further, the two-input and
Furthermore, the source of the first PMOS transistor PMOS1 is grounded VSS, the gate of the first PMOS transistor PMOS1 is connected to the gate of the first NMOS transistor NMOS1 to form a first input terminal of the two-input and gate for receiving the first input signal a1, the drain of the first PMOS transistor PMOS1 is connected to the drain of the first NMOS transistor NMOS1 to form an output terminal of the two-input and gate for outputting the intermediate output signal Sinter, and the source of the first NMOS transistor NMOS1 forms a second input terminal of the two-input and gate for receiving the second input signal a 2.
Further, when the first input signal a1 is 0 and the second input signal a2 is 0, the first PMOS transistor PMOS1 is turned on, the first NMOS transistor NMOS1 is turned off, and the intermediate output signal Sinter is equal to the ground voltage VSS and equal to 0; when the first input signal a1 is 0 and the second input signal a2 is 1, the first PMOS transistor PMOS1 is turned on, the first NMOS transistor NMOS1 is turned off, and the intermediate output signal Sinter is equal to the ground voltage VSS and equal to 0; when the first input signal a1 is 1 and the second input signal a2 is 0, the first PMOS transistor PMOS1 is turned off, the first NMOS transistor NMOS1 is turned on, and the intermediate output signal Sinter is equal to the second input signal a2 and is equal to 0; when the first input signal a1 is 1 and the second input signal a2 is 1, the first PMOS transistor PMOS1 is turned off, the first NMOS transistor NMOS1 is turned on, and the intermediate output signal Sinter is equal to the second input signal a2 and is equal to 1.
Further, the n-fold driving inverter includes a second PMOS transistor unit PMOS2 and a second NMOS
Further, the source of the second PMOS transistor unit PMOS2 is connected to the voltage terminal VDD, the drain of the second PMOS transistor unit PMOS2 is connected to the drain of the second NMOS transistor unit NMOS2 and forms an n-fold output terminal X of the driving nand standard unit for outputting the final output signal Sf, the source of the second NMOS transistor unit NMOS2 is grounded VSS, and the gate of the second NMOS transistor unit NMOS2 is connected to the gate of the second PMOS transistor unit PMOS2 and forms an n-fold input terminal of the driving inverter for receiving the intermediate output signal Sinter output by the two-input and gate.
Further, the n-fold drive inverter includes only the second PMOS transistor unit PMOS2 and the second NMOS
Further, the source of the second PMOS transistor unit PMOS2 is connected to the voltage terminal VDD, the drain of the second PMOS transistor unit PMOS2 is connected to the drain of the second NMOS transistor unit NMOS2 and forms an n-fold output terminal X of the driving nand standard unit for outputting the final output signal Sf, the source of the second NMOS transistor unit NMOS2 is grounded VSS, and the gate of the second NMOS transistor unit NMOS2 is connected to the gate of the second PMOS transistor unit PMOS2 and forms an n-fold input terminal of the driving inverter for receiving the intermediate output signal Sinter output by the two-input and gate.
Further, the second PMOS transistor unit PMOS2 includes n PMOS transistors connected in parallel, and the second NMOS transistor unit NMOS2 includes n NMOS transistors connected in parallel, where n is a driving multiple of the inverter and is an even number equal to or greater than 2.
Furthermore, when the intermediate output signal Sinter is 0, the second PMOS transistor unit PMOS2 is turned on, the second NMOS transistor unit NMOS2 is turned off, and the final output signal Sf is equal to the voltage terminal VDD and is equal to 1; when the intermediate output signal Sinter is 1, the second PMOS transistor unit PMOS2 is turned off, the second NMOS transistor unit NMOS2 is turned on, and the intermediate output signal Sinter is equal to the ground voltage VSS and equal to 0.
Furthermore, n times of the number m of the transistors used for driving the two-input nand standard cell is 2+2n, where n is the driving multiple of the two-input nand standard cell and is an even number greater than or equal to 2.
The invention also provides a layout of an n-time driving two-input nand gate standard cell, which comprises a two-input and gate formed by a first PMOS transistor PMOS1 and a first NMOS transistor NMOS1, and an n-time driving inverter formed by a second PMOS transistor PMOS2 and a second NMOS transistor NMOS2, wherein the second PMOS transistor PMOS2 comprises n PMOS transistors connected in parallel, the second NMOS transistor NMOS2 comprises n NMOS transistors connected in parallel, wherein n is a driving multiple of the inverter and is an even number greater than or equal to 2, and the layout is characterized by comprising: a first active region in which a first PMOS transistor PMOS1 is formed; a second active region in which a first NMOS transistor NMOS1 is formed; a third active region in which a second PMOS transistor cell PMOS2 is formed; a fourth active region in which a second NMOS transistor cell NMOS2 is formed; the gate structures of the first polysilicon, the first PMOS transistor PMOS1, and the first NMOS transistor NMOS1 are formed of the first polysilicon; and a second polysilicon, the gate structures of the PMOS transistors of the n PMOS transistors in the second PMOS transistor unit PMOS2 and the NMOS transistors of the n NMOS transistors in the second NMOS transistor unit NMOS2 being formed by the second polysilicon.
Furthermore, the first active region and the third active region are located in a row, the second active region and the fourth active region are located in a row, the first active region and the second active region are located in a column, and the third active region and the fourth active region are located in a column.
Further, the second strip of polysilicon includes n vertical sides and a transverse side connecting the n vertical sides together to form the second strip of polysilicon.
Further, the gate structures of one of n PMOS transistors in the second PMOS transistor unit PMOS2 and one of n NMOS transistors in the second NMOS transistor unit NMOS2 are formed by one of n vertical sides.
Further, the gate structures of one of the n PMOS transistors in the second PMOS transistor unit PMOS2 and one of the n NMOS transistors in the second NMOS transistor unit NMOS2 form a group of gate structures, the gate structures of the n PMOS transistors in the second PMOS transistor unit PMOS2 and the gate structures of the n NMOS transistors in the second NMOS transistor unit NMOS2 form n groups of gate structures, and each group of gate structures in the n groups of gate structures is formed by a corresponding one of the n vertical sides.
Further, the lateral edge is located in a spacing region between the third active region and the fourth active region.
Furthermore, the n vertical edges are parallel to each other and to the first polysilicon.
Further, a first contact hole is formed in the first polysilicon, the first contact hole forming a common connection terminal between the gate of the first PMOS transistor PMOS1 and the gate of the first NMOS transistor NMOS1, forming a first input terminal of the n-fold-drive two-input nand standard cell for receiving the first input signal a1, a second contact hole formed in the second active region, the second contact hole forming a source of the first NMOS transistor NMOS1, forming a second input terminal of the n-fold-drive two-input nand standard cell for receiving the second input signal a2, a third contact hole formed in the first active region, the third contact hole forming a source of the first PMOS transistor PMOS1, the third contact hole connected to the ground terminal VSS through a first metal line, a fourth contact hole formed in the first active region, forming a drain terminal of the first PMOS transistor PMOS1, a fifth contact hole formed in the second active region, forming a drain terminal of the first NMOS transistor NMOS1, the second metal wire connects the fourth contact hole and the fifth contact hole to form the output end of the two-input AND gate, and a sixth contact hole is formed on the second polysilicon to form the common connection end of the gates of the second PMOS transistor unit PMOS2 and the second NMOS transistor unit NMOS2 to form the input end of the n-fold driving inverter, the second metal wire is also connected with the sixth contact hole to connect the output ends of the two-input AND gate to the input end of the n-fold driving inverter, n seventh contact holes are formed on the third active region to form the source ends of n PMOS transistors in the second PMOS transistor unit PMOS2, the n seventh contact holes are connected together through the third metal wire to connect the voltage end VDD, n eighth contact holes are formed on the fourth active region to form the n NMOS contact holes in the
The n-time driving two-input NAND gate standard unit and the layout thereof provided by the invention form the n-time driving two-input NAND gate by the two-input AND gate and the n-time driving inverter together, wherein n is an even number which is more than or equal to 2, the using number of PMOS and NMOS transistors in the n-time driving inverter is increased along with the driving multiple, and the using number of PMOS and NMOS transistors in the two-input AND gate is unchanged, so that the using number of PMOS and NMOS transistors is reduced, the layout area of the n-time driving two-input NAND gate unit is reduced, the number of transistors is saved and is in direct proportion to the driving multiple, and the reduced area is in direct proportion to the driving multiple.
Drawings
Fig. 1 is a circuit diagram of a two-input nand standard cell in the prior art.
Fig. 2 is a circuit diagram of an n-fold driving two-input nand standard cell according to an embodiment of the invention.
Fig. 3 is a layout diagram of the two-input nand gate standard cell shown in fig. 1.
Fig. 4 is a layout diagram of the two-input nand gate standard cell shown in fig. 2.
FIG. 5 is a waveform diagram illustrating functional simulations of a NAND2 employing the prior art shown in FIG. 1 and a NAND2 employing the present invention shown in FIG. 2.
The reference numerals of the main elements in the figures are explained as follows:
210. two input AND gates; 220. the inverter is driven n times.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In one embodiment of the present invention, a two-input nand gate standard cell is provided. Specifically, referring to fig. 2, fig. 2 is a circuit diagram of an n-fold driving two-input nand standard cell according to an embodiment of the present invention, and the n-fold driving two-input nand standard cell shown in fig. 2 includes: a two-input and
Specifically, in an embodiment of the present invention, the two-input and
Specifically, in an embodiment of the invention, the two-input and
Specifically, in an embodiment of the present invention, when the first input signal a1 is 0 and the second input signal a2 is 0, the first PMOS transistor PMOS1 is turned on, the first NMOS transistor NMOS1 is turned off, and the intermediate output signal Sinter is equal to the ground voltage VSS and is equal to 0; when the first input signal a1 is 0 and the second input signal a2 is 1, the first PMOS transistor PMOS1 is turned on, the first NMOS transistor NMOS1 is turned off, and the intermediate output signal Sinter is equal to the ground voltage VSS and equal to 0; when the first input signal a1 is 1 and the second input signal a2 is 0, the first PMOS transistor PMOS1 is turned off, the first NMOS transistor NMOS1 is turned on, and the intermediate output signal Sinter is equal to the second input signal a2 and is equal to 0; when the first input signal a1 is 1 and the second input signal a2 is 1, the first PMOS transistor PMOS1 is turned off, the first NMOS transistor NMOS1 is turned on, and the intermediate output signal Sinter is equal to the second input signal a2 and equal to 1, so as to implement the logical and function.
Specifically, in an embodiment of the present invention, the n-
Specifically, in an embodiment of the present invention, the second PMOS transistor unit PMOS2 includes n PMOS transistors connected in parallel, and the second NMOS transistor unit NMOS2 includes n NMOS transistors connected in parallel, where n is a driving multiple of the inverter and is an even number greater than or equal to 2.
Specifically, when the intermediate output signal Sinter is 0, the second PMOS transistor unit PMOS2 is turned on, the second NMOS transistor unit NMOS2 is turned off, and the final output signal Sf is equal to the voltage terminal VDD and is equal to 1; when the intermediate output signal Sinter is 1, the second PMOS transistor unit PMOS2 is turned off, the second NMOS transistor unit NMOS2 is turned on, and the intermediate output signal Sinter is equal to the ground voltage VSS and equal to 0, thereby implementing the negation function.
Specifically, in an embodiment of the present invention, the n-
As described above, the number m of transistors used for driving the two-input nand standard cell by n times is 2+2n, where n is a driving multiple of the two-input nand standard cell and is an even number greater than or equal to 2.
Taking twice driving of the two-input nand standard cell as an example, if the two-input nand standard cell in the prior art shown in fig. 1 is adopted, 8 transistors are needed, please refer to fig. 3, fig. 3 is a layout schematic diagram of the two-input nand standard cell shown in fig. 1, and a layout side length ratio L1: H1 formed by four PMOS transistors PMOS1-4 and four NNOS transistors NMOS1-4 is 1.6:1 (the size of the standard cell is defined by the boundary of the CB layer); if the two-input NAND standard cell of the present invention as shown in fig. 2 needs 6 transistors, please refer to fig. 4, where fig. 4 is a layout diagram of the two-input NAND standard cell as shown in fig. 2, and a side length ratio L2: H2 formed by a first PMOS transistor PMOS1 and a first NMOS transistor NMOS1 in the two-input and gate, and a second PMOS transistor unit PMOS2 formed by parallel connection of 2 PMOS transistors and a second NMOS transistor unit NMOS2 formed by parallel connection of 2 NMOS transistors in a 2-fold driving inverter is 1.5:1 (the size of the standard cell is defined by the boundary of the CB layer), so based on the characteristics of the standard cell, the cell heights are consistent, i.e., H1 is H2, and the layout area of the NAND2_2 of the present invention is reduced by 6.3% compared with the layout area of the prior art as described above.
Referring to table 1, table 1 is a table comparing the number of transistors, layout side length ratio, and layout area under 2-fold, 4-fold, 8-fold, and 16-fold driving conditions using the NAND2 of the related art shown in fig. 1 and the NAND2 of the present invention shown in fig. 2. The comparison table between the n-times driving NAND2 in the prior art and the n-times driving NAND2 in the present invention shows that the number of transistors is saved in proportion to the driving multiple, so that the area of the transistor is reduced in proportion to the driving multiple, and therefore, for the two-input NAND standard cell with a large driving multiple, the advantage of the n-times driving two-input NAND standard cell in the present invention is obvious.
TABLE 1
Referring to fig. 5, fig. 5 is a functional simulation waveform diagram of the NAND2 of the invention shown in fig. 2 and the NAND2 of the prior art shown in fig. 1, wherein the functional simulation waveform shows that the NAND2_2 cell of the invention shown in fig. 2 can implement a two-input NAND function.
In summary, the two-input and gate and the n-time driving inverter jointly form the n-time driving two-input nand gate, wherein n is an even number greater than or equal to 2, the number of the PMOS transistors and the NMOS transistors in the n-time driving inverter is increased along with the driving multiple, and the number of the PMOS transistors and the NMOS transistors in the two-input and gate is unchanged, so that the number of the PMOS transistors and the NMOS transistors is reduced, the layout area of the n-time driving two-input nand gate unit is reduced, the number of the transistors is saved and is in direct proportion to the driving multiple, and the reduced area is in direct proportion to the driving multiple.
Specifically, in an embodiment of the present invention, a layout of an n-fold driving two-input nand standard cell is further provided, where the n-fold driving two-input nand standard cell includes a two-input and gate formed by a first PMOS transistor PMOS1 and a first NMOS transistor NMOS1, and an n-fold driving inverter formed by a second PMOS transistor PMOS2 and a second NMOS transistor NMOS2, where the second PMOS transistor PMOS2 includes n PMOS transistors connected in parallel, and the second NMOS transistor NMOS2 includes n NMOS transistors connected in parallel, where n is a driving multiple of the inverter, and is an even number greater than or equal to 2, and taking double driving as an example, the specific reference may be made to fig. 4, where as shown in fig. 4, the layout includes: a first active region 210, a first PMOS transistor PMOS1 being formed in the first active region 210; a second active region 220, the second active region 220 having a first NMOS transistor NMOS1 formed therein; a third active region 230, the third active region 230 having a second PMOS transistor cell PMOS2 formed therein; and a fourth active region 240, the fourth active region 240 having a second NMOS transistor cell NMOS2 formed therein; the gate structures of the first polysilicon 301, the first PMOS transistor PMOS1, and the first NMOS transistor NMOS1 are formed of the first polysilicon 301; and a second polysilicon 302, the gate structures of the PMOS transistors of the n PMOS transistors in the second PMOS transistor unit PMOS2 and the NMOS transistors of the n NMOS transistors in the second NMOS transistor unit NMOS2 being formed by the second polysilicon 302, as shown in the second polysilicon 302 of fig. 4.
Specifically, in an embodiment of the present invention, referring to fig. 4, the first
Specifically, in one embodiment of the present invention, referring to fig. 4, the second strip of
Specifically, in an embodiment of the present invention, referring to fig. 4, a first contact hole 3011 is formed in the first polysilicon 301, the first contact hole 3011 forms a common terminal between the gate of the first PMOS transistor PMOS1 and the gate of the first NMOS transistor NMOS1, forms a first input terminal of the n-fold driving two-input nand standard cell, and is configured to receive the first input signal a1, a second contact hole 221 is formed in the second active region 220, the second contact hole 221 forms a source of the first NMOS transistor NMOS1, forms a second input terminal of the n-fold driving two-input nand standard cell, and is configured to receive the second input signal a2, a third contact hole 211 is formed in the first active region 210, the third contact hole 211 forms a source of the first PMOS transistor PMOS1, the third contact hole 211 is connected to a ground terminal VSS through the first metal line 401, a fourth contact hole 212 is formed in the first active region 210, and forms a drain terminal of the first PMOS transistor PMOS1, a fifth contact hole 222 is formed on the second active region 220 to constitute a drain terminal of the first NMOS transistor NMOS1, a second metal line 402 connects the fourth contact hole 212 and the fifth contact hole 222 to constitute an output terminal of a two-input and gate, a sixth contact hole 3021 is formed on the second polysilicon 302 to constitute a common terminal of gates of the second PMOS transistor unit PMOS2 and the second NMOS transistor unit NMOS2 to constitute an input terminal of an n-fold driving inverter, the second metal line 402 is further connected to the sixth contact hole 3021 to connect output terminals of the two-input and gate to an input terminal of the n-fold driving inverter, n seventh contact holes 2031 are further formed on the third active region 230 to constitute source terminals of n PMOS transistors in the second PMOS transistor unit 2, the n seventh contact holes 2031 are connected together through the third metal line 403 to connect the voltage terminal VDD, n eighth contact holes 2401 are further formed on the fourth active region 240, the n eighth contact holes 2401 constitute source terminals of n NMOS transistors in the second NMOS transistor unit NMOS2, and the n eighth contact holes 2401 are connected together by the first metal line 401 to the ground terminal VSS; a plurality of ninth contact holes 2032 are further formed in the third active region 230, the ninth contact holes 2032 form drain terminals of n PMOS transistors in the second PMOS transistor unit PMOS2, a plurality of tenth contact holes 2402 are further formed in the fourth active region 240, the tenth contact holes 2402 form drain terminals of n NMOS transistors in the second NMOS transistor unit NMOS2, and the ninth contact holes 2032 and the tenth contact holes 2402 are connected together by the third metal wire 403 to form an output terminal X of the n-fold-drive two-input nand standard cell.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
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