阅读说明：本技术 信号处理方法、装置及选择电路 (Signal processing method, device and selection circuit ) 是由 王宗磊 汪文祥 于 2018-08-27 设计创作，主要内容包括：本发明提供一种信号处理方法、装置及选择电路,本发明的方法,通过获取待处理的队列对应的位向量,并对所述位向量进行转换,以获取所述位向量对应的L组信号,每组信号对应于所述位向量中的每一项；根据预配置的选N逻辑,确定R选N的选择电路,所述R选N的选择电路包括至少一阶选择逻辑模块,每阶选择逻辑模块包括至少一个M选N的基本选择逻辑电路；采用所述R选N的选择电路,对所述L组信号进行选择处理,以从所述L组信号中选择表示未分配的N组信号；可以通过R选N的选择电路硬件实现从L组信号中选取出表示未分配的N组信号,R选N的选择电路的延迟时间很短,大大缩短了未分配项选择的延迟时间。(The invention provides a signal processing method, a device and a selection circuit, wherein the method comprises the steps of obtaining a bit vector corresponding to a queue to be processed, and converting the bit vector to obtain L groups of signals corresponding to the bit vector, wherein each group of signals corresponds to each item in the bit vector; determining a selection circuit of R-to-N according to pre-configured N-to-N logic, wherein the selection circuit of R-to-N comprises at least one order selection logic module, and each order selection logic module comprises at least one basic selection logic circuit of M-to-N; selecting the L groups of signals by adopting the R-to-N selection circuit so as to select N groups of signals which represent non-distribution from the L groups of signals; n groups of signals which are not distributed can be selected from the L groups of signals through the hardware of the R-to-N selection circuit, the delay time of the R-to-N selection circuit is short, and the delay time of selection of the non-distributed items is greatly shortened.)

1. A signal processing method, comprising:

acquiring a bit vector corresponding to a queue to be processed, and converting the bit vector to acquire L groups of signals corresponding to the bit vector, wherein each group of signals corresponds to each item in the bit vector;

determining a selection circuit of R-to-N according to pre-configured N-to-N logic, wherein the selection circuit of R-to-N comprises at least one order selection logic module, and each order selection logic module comprises at least one basic selection logic circuit of M-to-N;

selecting the L groups of signals by adopting the R-to-N selection circuit so as to select N groups of signals which represent non-distribution from the L groups of signals;

and both L, R, M and N are integers, R is an integral multiple of M, L is less than or equal to R and is greater than or equal to M, and M is equal to 2N.

2. The method of claim 1, wherein: the M-to-N basic selection logic circuit comprises N sub-selection logic modules, and each sub-selection logic module comprises N processing units;

for each processing unit:

receiving two groups of signals, determining one group of the two groups of signals as an unallocated group signal to be determined and determining the other group of the two groups of signals as an allocated group signal to be determined according to the numerical value of the group of signals received by a receiving terminal as an enabling terminal;

outputting the unassigned group signal to be determined to a next processing unit in the sub-selection logic module where the processing unit is located;

and outputting the distributed group signals to be determined to a processing unit in another sub-selection logic module except the sub-selection logic module where the processing unit is located.

3. The method of claim 2, wherein each set of signals comprises: an index, and a value corresponding to the index.

4. The method of claim 3, wherein the R-to-N selection circuit comprises R sets of receive terminals, and wherein the selecting the L sets of signals using the R-to-N selection circuit to select N sets of signals from the L sets of signals representing unassigned signals comprises:

outputting the L groups of signals to L groups of receiving terminals of the R-to-N selection circuit;

and if L is smaller than R, outputting a group signal with a value of 0 corresponding to an index to the rest receiving terminals except the L groups of receiving terminals corresponding to the L groups of signals in the selection circuit of the R-selected-N.

5. The method of claim 4, wherein said selecting circuit using said R to select N performs a selection process on said L groups of signals to select N groups of signals representing unassigned signals from said L groups of signals, comprising:

comparing the received R group signals by adopting a first-order selection logic module of the R-to-N selection circuit to obtain M unassigned group signals to be determined;

and comparing the M unassigned group signals to be determined by adopting a second-stage selection logic circuit of the R-to-N selection circuit to obtain N unassigned group signals.

6. A signal processing apparatus, characterized by comprising:

the information conversion module is used for acquiring a bit vector corresponding to a queue to be processed and converting the bit vector to acquire L groups of signals corresponding to the bit vector, wherein each group of signals corresponds to each item in the bit vector;

the circuit determination module is used for determining a selection circuit of R-to-N according to a pre-configured N-selection logic, wherein the selection circuit of R-to-N comprises at least one stage of selection logic module, and each stage of selection logic module comprises at least one basic selection logic circuit of M-to-N;

the selection processing module is used for selecting the L groups of signals by adopting the R-to-N selection circuit so as to select N groups of signals which are not distributed from the L groups of signals;

and both L, R, M and N are integers, R is an integral multiple of M, L is less than or equal to R and is greater than or equal to M, and M is equal to 2N.

7. An R-to-N selection circuit, comprising: the device comprises a first-stage selection logic module used for receiving R groups of signals and a second-stage selection logic module connected with the first-stage selection logic module;

the first-stage selection logic module comprises a K-to-N selection circuit and a T-to-N selection circuit, wherein the K-to-N selection circuit and the T-to-N selection circuit both comprise at least one M-to-N basic selection logic circuit, and R is K + T;

the second-stage selection logic module comprises a basic selection logic circuit for selecting N from M;

and R, N, K, T and M are integers, R, K and T are integer multiples of M, and M is equal to 2N.

8. The N-out-of-R selection circuit of claim 7, wherein: the M-to-N basic selection logic circuit comprises N sub-selection logic modules, and each sub-selection logic module comprises N processing units;

for each processing unit:

receiving two groups of signals, determining one group of the two groups of signals as an unallocated group signal to be determined and determining the other group of the two groups of signals as an allocated group signal to be determined according to the numerical value of the group of signals received by a receiving terminal as an enabling terminal;

outputting the unassigned group signal to be determined to a next processing unit in the sub-selection logic module where the processing unit is located;

and outputting the distributed group signals to be determined to a processing unit in another sub-selection logic module except the sub-selection logic module where the processing unit is located.

9. The N-out-of-R selection circuit of claim 8, wherein: the processing unit includes:

a first receiving terminal and a second receiving terminal for receiving a set of signals; a third receiving terminal and a fourth receiving terminal for receiving another set of signals;

an or gate connected with the first and third receiving terminals, and including a first output terminal;

an AND gate connected to the first and third receive terminals, the AND gate including a second output terminal;

a multi-way switch connected with the second receiving terminal, the fourth receiving terminal, and the first receiving terminal for enabling, the multi-way switch including a fourth output terminal;

a third output terminal connected to the fourth receiving terminal.

10. The N-out-of-R selection circuit of claim 9, wherein: the first output terminal and the fourth output terminal are used for outputting one group of unassigned group signals to be determined in two groups of signals received by the processing unit;

the second output terminal and the third output terminal are used for outputting a group of distributed group signals to be determined.

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a signal processing method, a signal processing apparatus, and a selection circuit.

Background

The selection logic for bits in a bit vector is one of the basic circuits often used in microprocessors. For example, in a processor that supports out-of-order multi-issue, in order to issue multiple instructions per beat of the clock, the processor needs to assign a reorder entry to the multiple instructions in a reorder queue. The same circuit can be used not only in a reorder queue, but also in other queues that need to allocate multiple items simultaneously, such as a memory access queue.

The use of the queue is represented by a bit vector: a 0 indicates allocated and a 1 indicates unallocated, and the role of the selection logic is to pick out the position of an unallocated 1-valued entry from a given bit vector.

The existing selection method of unallocated items selects the unallocated items in the bit vector by judging whether each item in the bit vector is unallocated one by one, so that the delay time is long.

Disclosure of Invention

The invention provides a signal processing method, a signal processing device and a selection circuit, which are used for solving the problem of long delay time of the existing selection method of unallocated items, wherein the problem is that the unallocated items in a bit vector are selected by judging whether each item in the bit vector is unallocated one by one.

One aspect of the present invention provides a signal processing method, including:

acquiring a bit vector corresponding to a queue to be processed, and converting the bit vector to acquire L groups of signals corresponding to the bit vector, wherein each group of signals corresponds to each bit item in the bit vector;

determining a selection circuit of R-to-N according to pre-configured N-to-N logic, wherein the selection circuit of R-to-N comprises at least one order selection logic module, and each order selection logic module comprises at least one basic selection logic circuit of M-to-N;

selecting the L groups of signals by adopting the R-to-N selection circuit so as to select N groups of signals which represent non-distribution from the L groups of signals;

and both L, R, M and N are integers, R is an integral multiple of M, L is less than or equal to R and is greater than or equal to M, and M is equal to 2N.

Another aspect of the present invention provides a signal processing apparatus including:

the information conversion module is used for acquiring a bit vector corresponding to a queue to be processed and converting the bit vector to acquire L groups of signals corresponding to the bit vector, wherein each group of signals corresponds to each item in the bit vector;

the circuit determination module is used for determining a selection circuit of R-to-N according to a pre-configured N-selection logic, wherein the selection circuit of R-to-N comprises at least one stage of selection logic module, and each stage of selection logic module comprises at least one basic selection logic circuit of M-to-N;

the selection processing module is used for selecting the L groups of signals by adopting the R-to-N selection circuit so as to select N groups of signals which are not distributed from the L groups of signals;

and both L, R, M and N are integers, R is an integral multiple of M, L is less than or equal to R and is greater than or equal to M, and M is equal to 2N.

Another aspect of the present invention provides a circuit for selecting N from R, including: the device comprises a first-stage selection logic module used for receiving R groups of signals and a second-stage selection logic module connected with the first-stage selection logic module;

the first-stage selection logic module comprises a K-to-N selection circuit and a T-to-N selection circuit, wherein the K-to-N selection circuit and the T-to-N selection circuit both comprise at least one M-to-N basic selection logic circuit, and R is K + T;

the second-stage selection logic module comprises a basic selection logic circuit for selecting N from M;

and R, N, K, T and M are integers, R, K and T are integer multiples of M, and M is equal to 2N.

According to the signal processing method, the signal processing device and the selection circuit, L groups of signals corresponding to a bit vector are obtained by obtaining the bit vector corresponding to a queue to be processed and converting the bit vector, wherein each group of signals corresponds to each item in the bit vector; determining a selection circuit of R-to-N according to pre-configured N-to-N logic, wherein the selection circuit of R-to-N comprises at least one order selection logic module, and each order selection logic module comprises at least one basic selection logic circuit of M-to-N; selecting the L groups of signals by adopting the R-to-N selection circuit so as to select N groups of signals which represent non-distribution from the L groups of signals; n groups of signals which are not distributed can be selected from the L groups of signals through the hardware of the R-to-N selection circuit, the delay time of the R-to-N selection circuit is short, and the delay time of selection of the non-distributed items is greatly shortened.

Drawings

Fig. 1 is a flowchart of a signal processing method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a selection circuit for selecting N from L according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a processing unit according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another processing unit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of an 8-to-4 basic selection logic circuit according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a selection circuit of 4-out-of-32 according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a signal processing apparatus according to an embodiment of the present invention.

With the above figures, certain embodiments of the invention have been illustrated and described in more detail below. The drawings and the description are not intended to limit the scope of the inventive concept in any way, but rather to illustrate it by those skilled in the art with reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.

The terms "first", "second", etc. referred to in the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. In the description of the following examples, "plurality" means two or more unless specifically limited otherwise.

The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present invention will be described below with reference to the accompanying drawings.