阅读说明：本技术 集成的超长时间常数时间测量设备和制造过程 (Integrated ultra-long time constant time measurement apparatus and manufacturing process ) 是由 A·马扎基 P·弗纳拉 于 2019-08-30 设计创作，主要内容包括：本公开的实施例涉及集成的超长时间常数时间测量设备和制造过程。一种集成的超长时间常数时间测量设备包括串联连接的基本电容性元件。每个基本电容性元件由第一导电区域、介电层和第二导电区域的堆叠形成,介电层具有的厚度适合于允许电荷通过直接隧道效应流动。第一导电区域容纳在从半导体衬底的正面向下延伸到半导体衬底中的沟槽中。介电层位于半导体衬底的第一面上,特别是位于沟槽中的第一导电区域的一部分上。第二导电区域位于介电层上。(Embodiments of the present disclosure relate to integrated ultralong time constant time measurement devices and manufacturing processes. An integrated ultra-long time constant time measurement device includes a series connection of elementary capacitive elements. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer and a second conductive region, the dielectric layer having a thickness suitable to allow the flow of charges through direct tunneling. The first conductive region is received in a trench extending downward into the semiconductor substrate from the front surface of the semiconductor substrate. The dielectric layer is located on the first side of the semiconductor substrate, in particular on a portion of the first conductive region in the trench. The second conductive region is on the dielectric layer.)

1. An integrated ultralong time constant time measurement device, comprising:

a plurality of elementary capacitive elements connected in series,

a capacitive storage element connected to one end of the series-connected plurality of elementary capacitive elements and configured to be charged,

wherein the series-connected plurality of elementary capacitive elements are configured to discharge the charged capacitive storage element and to transfer a physical quantity to at least one node of the series-connected plurality of elementary capacitive elements, the physical quantity representing the discharge of the capacitive storage element and representing a duration of time elapsed between a start of a discharge operation of the capacitive storage element and a time at which the physical quantity is transferred,

wherein each elementary capacitive element comprises:

a stack of a first conductive region, a dielectric layer and a second conductive region, the dielectric layer having a thickness suitable to allow charge flow by direct tunneling,

wherein the first conductive region is accommodated in a trench extending from a front side of a semiconductor substrate into the substrate, an

Wherein the dielectric layer is located on the front side of the semiconductor substrate and the second conductive region is located on the dielectric layer.

2. The apparatus of claim 1, wherein the stack is positioned facing a portion of a width of the trench that receives the first conductive region on the front side.

3. The apparatus of claim 1, wherein the series connection of the plurality of elementary capacitive elements is alternately constituted by a second conductive region common to two consecutive elementary capacitive elements and a first conductive region common to two consecutive elementary capacitive elements.

4. The apparatus of claim 1, wherein the semiconductor substrate comprises an electrically isolated region extending vertically into the semiconductor substrate from the first face, wherein the trench housing the first conductive region of each elemental capacitive element passes through the electrically isolated region.

5. The apparatus of claim 1, further comprising:

a semiconductor well housed in the substrate at a location where the series-connected plurality of elementary capacitive elements are located;

a first contact and a second contact electrically connected by an electrical path through the semiconductor well, the electrical path including a portion positioned between a bottom of a trench and a bottom of the well;

a detection circuit configured to detect an electrical discontinuity in the semiconductor well between the first contact and the second contact.

6. A method for measuring a duration, comprising:

charging a capacitive storage element;

discharging the charged capacitive storage element through a plurality of elementary capacitive elements connected in series; and

acquiring a physical quantity on at least one node of the plurality of elementary capacitive elements connected in series, the physical quantity representing a discharge of the capacitive storage element and representing a duration elapsed between a start of a discharge operation of the capacitive storage element and a time at which the physical quantity is transmitted;

wherein each elementary capacitive element comprises:

a stack of a first conductive region, a dielectric layer and a second conductive region, the dielectric layer having a thickness suitable to allow charge flow by direct tunneling,

wherein the first conductive region is accommodated in a trench extending from a front side of a semiconductor substrate into the substrate, an

Wherein the dielectric layer is located on the front side of the semiconductor substrate and the second conductive region is located on the dielectric layer.

7. A method for fabricating an integrated ultra-long time constant time measurement device, comprising:

forming a trench extending into a semiconductor substrate from a front side of the semiconductor substrate;

forming a first conductive region received in the trench;

forming a dielectric layer on the front side, the dielectric layer having a thickness suitable to allow charge flow by direct tunneling;

forming a second conductive region on the dielectric layer;

wherein respective stacks of the first conductive region, the dielectric layer, and the second conductive region form a plurality of elementary capacitive elements connected in series;

a capacitive storage element connected to one end of the series-connected plurality of elementary capacitive elements is formed.

8. The method of claim 7, wherein the dielectric layer and the second conductive region are positioned facing respective portions of a width of the trench that receives the first conductive region on the front side.

9. The method of claim 7, wherein the series connection of the plurality of elementary capacitive elements is alternately constituted by a second conductive region common to two consecutive elementary capacitive elements and a first conductive region common to two consecutive elementary capacitive elements.

10. The method of claim 7, further comprising: forming an electrically isolated region extending vertically into the substrate from the first face, and wherein forming the trench to accommodate the first electrically conductive region comprises: the trench is formed to extend to and through the electrically isolated region.

11. The method of claim 7, further comprising:

forming a semiconductor well in the semiconductor substrate; and

forming a first contact and a second contact connected by an electrical path that includes a portion of the semiconductor well positioned between a bottom of a trench and a bottom of the semiconductor well.

12. The method of claim 11, further comprising: providing a circuit connected to the first and second contacts and configured to detect an electrical discontinuity in the well between the first and second contacts.

Technical Field

Background

Ultra Long Time Constant (ULTC) time measurement circuits qualify to measure application ranges on the order of tens of minutes to hours.

In many applications, it is desirable to have information indicative of the time elapsed between two events, whether they be accurate or approximate measurements.

One example of this application relates to fraud prevention measures where the system is locked long enough to make it a deterrent. These precautions are applicable to semi-invasive attacks (e.g., analytical techniques employing fault injection) or non-invasive attacks (such as brute force attacks or side-channel attacks). Generally, this type of attack is based on a self-learning method that achieves multiple iterations and precise synchronization.

In this case, locking the system for a duration of about one hour or tens of minutes is sufficient to prevent a fraudulent party from adopting this method.

This type of prevention by the locking system has the advantage of being temporary and non-destructive, for example in the case where a fault or operating error is detected as a fraudulent attempt.

Of course, it is desirable that deactivation of the system does not disrupt the operation of measuring the duration of the lock.

An electronic device has been proposed, for example, in us patent No.8,872,177 (see also FR 2981190a1), incorporated herein by reference, in which the time elapsed between two events is determined by measuring the residual charge of a pre-charged capacitive storage element connected to a series of charge flow capacitive elements having a leakage in the dielectric space. The remaining charge of the capacitive storage element represents the time elapsed during discharge.

According to the teaching of us patent No.8,872,177, the dielectric space of the capacitive element comprises a thick dielectric layer that does not leak and a thinner leakage region to allow charge to leak through tunneling and thus is created with the purpose of controlling the size of the aforementioned leakage region.

One disadvantage is that in practice the leakage area is surrounded by a thicker dielectric layer, in particular a silicon ONO (oxide nitride oxide) layer, which uses a not negligible total substrate area and imposes high-granularity design rules, i.e. its minimum dimension is relatively large and its embodiments are bulky.

However, it is desirable to reduce the footprint of the integrated circuit.

Therefore, there is a need for an ultra-long time constant time measurement apparatus and measures that can measure the passage of time on the order of tens of minutes to days without the need for a power supply, is substantially independent of temperature, and also has a minimized footprint.

Disclosure of Invention

According to one aspect, an integrated ultralong time constant time measurement device is proposed, comprising a plurality of elementary capacitive elements in series, a capacitive storage element connected to one end of the elementary capacitive elements in series and capable of being charged, the elementary capacitive elements in series being configured to discharge the charged capacitive storage element and to transfer a physical quantity to at least one node of the elementary capacitive elements in series, the physical quantity being representative of the discharge of the capacitive storage element and representative of a duration elapsed between a start of a discharge operation of the capacitive storage element and a moment in time at which the physical quantity is transferred, wherein each elementary capacitive element comprises a stack of a first conductive region, a dielectric layer and a second conductive region, the dielectric layer having a thickness suitable to allow a flow of charges by direct tunneling, wherein the first conductive region is accommodated in a trench extending from a front surface of a semiconductor substrate down into the substrate, and a dielectric layer is on the front surface of the substrate and a second conductive region is on the dielectric layer.

Thus, such an embodiment does not cause a large area loss, since the entire interface of the dielectric layer positioned between the two conductive regions has a thickness suitable to allow the charge to circulate through the direct tunneling effect. Specifically, an area of 1/3.5 relative to the above-mentioned reference ultra-long time constant time measurement device technique has been obtained.

Furthermore, it is actually advantageous to measure the quantity representing the discharge of the capacitive storage element at least one node of the series-connected elementary capacitive elements instead of directly at the terminals of the capacitive storage element.

According to one embodiment, the stack of the first conductive region, the dielectric layer and the second conductive region of each elementary capacitive element is positioned facing a portion of the groove accommodating the first conductive region on the front surface.

This allows the use of an area to be optimized.

According to one embodiment, the elementary capacitive elements are alternately electrically connected in series with each other by the second conductive region common to two consecutive elementary capacitive elements or by the first conductive region common to two consecutive elementary capacitive elements.

This allows the use of an area to be optimized.

According to an embodiment in which the semiconductor substrate comprises an electrically isolating region extending vertically from the front side into the substrate, the above-mentioned trench accommodating the first conductive region of each elementary capacitive element passes through the electrically isolating region.

This makes it possible, for example, to prevent current leakage into the substrate without providing for this purpose a dielectric of another thickness facing the substrate.

According to one embodiment, the series connection of a plurality of elementary capacitive elements is positioned in a semiconductor well housed in the substrate and comprising a first contact and a second contact electrically connected by an electrical path through the well, the circuit comprising a portion positioned between the bottom of the trench and the bottom of the well, and the device further comprises a detection circuit configured to detect an electrical discontinuity in the well between the first contact and the second contact.

Thus, if an electrical discontinuity is detected in the well between the first contact and the second contact, which would indicate that the substrate was etched from the backside, the detection circuitry would be able to, for example, command a preventative or destructive countermeasure against such etching.

Proposed is a method for measuring a duration, comprising the following operations: the capacitive storage element of the device as described above is charged, the charged capacitive storage element is discharged through the plurality of elementary capacitive elements connected in series, and the physical quantity indicative of the discharge of the capacitive storage element and of the duration elapsed at the start of the discharge operation of the capacitive storage element and the time at which the physical quantity is acquired at least one node of the plurality of elementary capacitive elements connected in series.

According to another aspect, a method for manufacturing an integrated ultra-long time constant time measurement device is presented, comprising: an operation of forming a trench extending from a front surface of a semiconductor substrate down into the substrate; an operation of forming a first conductive region accommodated in the groove; an operation of forming a dielectric layer on the front surface, the dielectric layer having a thickness suitable for allowing the flow of charges by direct tunneling; an operation of forming a second conductive region on the dielectric layer, the respective stacks of the first conductive region, the dielectric layer and the second conductive region forming a plurality of elementary capacitive elements in series, the process further comprising: an operation of forming a capacitive storage element connected to one end of a plurality of basic capacitive elements connected in series.

According to one implementation, the operative faces forming the dielectric layer and the second conductive region are positioned facing respective portions of the width of the aforementioned trench accommodating the first conductive region on the aforementioned front face.

According to one implementation, the operations of forming the trenches and the respective first conductive regions and forming the dielectric layers and the respective second conductive regions are positioned relatively so as to alternately form a plurality of elementary capacitive elements electrically connected in series with each other through the second conductive region common to two consecutive elementary capacitive elements or through the first conductive region common to two consecutive elementary capacitive elements.

According to one implementation, the process includes an operation of forming an electrically isolated region extending vertically into the substrate from the front side, and the above-described operation of forming the trench to accommodate the first conductive region is performed through the electrically isolated region.

According to one implementation, the process includes a previous operation of forming a semiconductor well in the substrate, and an operation of forming a first contact and a second contact, the contacts being electrically connected by an electrical path through the well, the electrical path including a portion positioned between the bottom of the trench and the bottom of the well, the process further including an operation of detecting an electrical discontinuity in the well between the first contact and the second contact.

Drawings

Further advantages and features of the invention will become clear from a study of the detailed description of purely non-limiting embodiments and implementations and of the accompanying drawings, in which:

FIG. 1 illustrates an embodiment of an ultra-long time constant time measurement device;

FIG. 2 is a circuit diagram of an application of the embodiment shown in FIG. 1;

FIGS. 3 and 4 illustrate a variation of an ultralong time constant time measurement device that includes a detection circuit configured to detect electrical discontinuities; and

fig. 5 shows manufacturing steps for manufacturing a device for time measurement such as shown in fig. 1 to 4.

Embodiments and implementations relate generally to integrated circuits, and more particularly to fabrication of ultra-long time constant time measurement devices.