阅读说明：本技术 具有带有升高栅极的指形件的门控二极管 (Gated diode with fingers with raised gate ) 是由 洪全敏 尹春山 陈瑜 于 2019-09-02 设计创作，主要内容包括：集成电路具有带有一个或多个二极管指形件的第一门控二极管。每个二极管指形件具有升高栅极、底层p型扩散体和底层n型扩散体。每个扩散体具有基极区和位于所述基极区与所述升高栅极之间的环形侧区,使得所述扩散体具有支持所述二极管指形件的更大电流电平的增加的侧向表面积,这使得门控二极管比不具有升高栅极的等效常规门控二极管能够用更少指形件实施并且因此具有更小的布局面积。所述第一门控二极管可以用类似的第二门控二极管实施以形成所述集成电路的ESD保护电路系统。(The integrated circuit has a first gated diode with one or more diode fingers. Each diode finger has a raised gate, an underlying p-type diffusion, and an underlying n-type diffusion. Each diffusion has a base region and an annular side region between the base region and the raised gate such that the diffusion has an increased lateral surface area that supports a greater current level of the diode fingers, which enables the gated diode to be implemented with fewer fingers and thus a smaller layout area than an equivalent conventional gated diode without a raised gate. The first gated diode may be implemented with a similar second gated diode to form ESD protection circuitry of the integrated circuit.)

1. An integrated circuit comprising a first gated diode having one or more diode fingers, each diode finger comprising a raised gate and a p-type diffusion and an n-type diffusion on opposite sides of the raised gate, wherein:

the p-type diffusion includes a p-type base region and a p-type annular side region between the p-type base region and the raised gate; and is

The n-type diffusion includes an n-type base region and an n-type annular side region between the n-type base region and the raised gate.

2. The integrated circuit of claim 1, wherein the first gated diode comprises a plurality of the diode fingers.

3. The integrated circuit of claim 1, further comprising a high supply Voltage (VDD) node, a low supply Voltage (VSS) node, an input/output (I/O) pin, and protected circuitry connected to the VDD node, the VSS node, and the I/O pin, wherein:

the first gated diode is part of ESD protection circuitry of the integrated circuit;

the ESD protection circuitry further comprises a second gated diode;

the first gated diode is connected between the I/O pin and the VDD node and is configured to protect the protected circuitry from an overvoltage applied to the I/O pin by shunting current from the I/O pin to the VDD node by way of the first gated diode; and is

The second gated diode is connected between the I/O pin and the VSS node and is configured to protect the protected circuitry from under-voltage applied to the I/O pin by shunting current from the VSS node to the I/O pin by way of the second gated diode.

4. A method for fabricating a first gated diode of an integrated circuit, the method comprising:

forming one or more diode fingers of the first gated diode on a substrate, each diode finger comprising a raised gate and a p-type diffusion and an n-type diffusion on opposite sides of the raised gate, wherein:

the p-type diffusion includes a p-type base region and a p-type annular side region between the p-type base region and the raised gate; and is

The n-type diffusion includes an n-type base region and an n-type annular side region between the n-type base region and the raised gate; and

forming at least one first contact connected to each of the raised gate, the p-type diffusion, and the n-type diffusion of each diode finger of the first gated diode.

5. The method of claim 4, wherein each diode finger is formed by:

applying a gate material to the substrate corresponding to the raised gate;

removing material from the substrate to form first and second trenches on opposite sides of the gate material to form the raised gate;

applying a p-type dopant to the first trench to form the p-type diffusion; and

applying n-type dopants to the second trench to form the n-type diffusion.

6. The method of claim 4, wherein each diode finger is formed by:

applying a substrate material to the substrate to create an elevated region of the substrate corresponding to the elevated gate;

applying a gate material to the elevated regions to form the elevated gates;

applying a p-type dopant to the substrate on one side of the raised gate to form the p-type diffusion; and

applying n-type dopants to the substrate on the opposite sides of the raised gate to form the n-type diffusion.

7. The method of claim 4, further comprising:

forming one or more diode fingers of a second gated diode on the substrate, each diode finger of the second gated diode comprising a raised gate and a p-type diffusion and an n-type diffusion on opposite sides of the raised gate of the second gated diode, wherein:

the p-type diffusion of the second gated diode includes a p-type base region and a p-type ring-shaped side region between the p-type base region and the raised gate; and is

The n-type diffusion of the second gated diode includes an n-type base region and an n-type annular side region between the n-type base region and the raised gate; and

forming at least one second contact connected to each of the raised gate, the p-type diffusion, and the n-type diffusion of each diode finger of the second gated diode.

8. The method of claim 7, wherein:

the integrated circuit further includes a high supply Voltage (VDD) node, a low supply Voltage (VSS) node, an input/output (I/O) pin, and protected circuitry connected to the VDD node, the VSS node, and the I/O pin;

the first gated diode and the second gated diode are part of ESD protection circuitry of the integrated circuit;

the first gated diode is connected between the I/O pin and the VDD node and is configured to protect the protected circuitry from an overvoltage applied to the I/O pin by shunting current from the I/O pin to the VDD node by way of the first gated diode; and is

The second gated diode is connected between the I/O pin and the VSS node and is configured to protect the protected circuitry from under-voltage applied to the I/O pin by shunting current from the VSS node to the I/O pin by way of the second gated diode.

Technical Field

The present invention relates to Integrated Circuits (ICs), and more particularly to IC diodes, such as those used for electrostatic discharge (ESD) protection.

Background

Integrated circuits are manufactured by selectively adding and removing material to and from a semiconductor substrate in a series of manufacturing steps. For example, a p (positive) or n (negative) doped well region is formed on a substrate by masking the region that will remain undoped, and then applying an appropriate p-type dopant material or n-type dopant material to form a p/n well in the remaining unmasked region. During such fabrication steps, the p/n wells will all be formed to have the same thickness (also referred to as depth), which is determined by the requirements of the desired integrated circuit system.

One known type of integrated circuit system is ESD protection circuitry designed to protect other circuitry formed on the same substrate from electrostatic discharge (ESD) events during which an over-voltage (e.g., a voltage substantially above the IC high supply voltage VDD) or an under-voltage (e.g., a voltage substantially below the IC low supply voltage VSS) is applied to an input/output (I/O) port (also referred to as an I/O pin or I/O pad) of the IC.

Fig. 1 is a schematic circuit diagram of one known type of ESD protection circuitry 100, the ESD protection circuitry 100 being configured to protect other (i.e., protected) circuitry 120 from ESD events at an I/O pin 130. As shown in fig. 1, ESD protection circuitry 100 has a first diode 112 connected between VSS and I/O pin 130 and a second diode 114 connected between I/O pin 130 and VDD. During normal operation, in which the voltage level applied to the I/O pin 130 remains at or above the low supply voltage level VSS and at or below the high supply voltage level VDD, neither the first diode 112 nor the second diode 114 conducts current.

However, if and when the voltage level applied to the I/O pin 130 begins to drop below VSS by one diode voltage drop (about 0.7V), current will begin to flow from VSS through the first diode 112 to the I/O pin 130, thereby limiting the magnitude of the under-voltage condition at the I/O pin 130 and preventing an undesirably large under-voltage from being applied to the protected circuitry 120. Similarly, if and when the voltage level applied to the I/O pin 130 begins to exceed VDD by one diode voltage drop (about 0.7V), current will begin to flow from the I/O pin 130 through the second diode 114 to VDD, thereby limiting the magnitude of the overvoltage condition at the I/O pin 130 and preventing an undesirably large overvoltage from being applied to the protected circuitry 120. In order to provide adequate ESD protection to the protected circuitry 120, the diode 112 and the diode 114 must be designed and configured to quickly shunt a sufficiently large amount of current away from the I/O pin 130.

Fig. 2 is a cross-sectional side view of a region of a semiconductor substrate 202 corresponding to a conventional N +/isolated P-well gated diode 200 that may be used to implement the first diode 112 of fig. 1. Those skilled in the art will appreciate that similar P +/N well gated diodes may be used to implement the second diode 114 of fig. 1.

As shown in fig. 2, gated diode 200 has six diode fingers 210(1) -210(6), each including a dielectric gate 212 above and separating a P + diffusion 214 from an adjacent N + diffusion 216. Note that each of the P + diffusion 214 and the N + diffusion 216 is shared by two adjacent fingers 210, except for the outermost P + diffusion 214(1) and P + diffusion 214 (4). For example, N + diffusion 216(1) is shared by fingers 210(1) and fingers 210(2), P + diffusion 214(2) is shared by fingers 210(2) and fingers 210(3), and so on.

As represented in fig. 2, each P + diffusion 214 is connected to VSS by way of a corresponding conductive (e.g., metal) contact 218, and each N + diffusion 216 is connected to a corresponding I/O pin (e.g., I/O pin 130 of fig. 1) by way of a corresponding contact 218. Although not shown in fig. 2, each gate 212 is connected to its corresponding P + diffusion 214. Thus, the gate 212(1) is connected to the P + diffusion 214(1), the gate 212(2) and the gate 212(3) are both connected to the common P + diffusion 214(2), the gate 212(4) and the gate 212(5) are both connected to the common P + diffusion 214(3), and the gate 212(6) is connected to the P + diffusion 214 (4).

If and when the voltage applied to the I/O pin begins to drop below VSS by one diode voltage drop (approximately 0.7V), current will begin to flow from the P + diffusion 214 to the N + diffusion 216 as represented by the horizontal arrow in FIG. 2. The magnitude of the maximum current that can flow within the gated diode 200 is a function of, among other things, the number of fingers 210 in the gated diode 200 and the lateral surface area of the sidewall of each of the P + diffusion 214 and the N + diffusion 216. The lateral surface area of each diffuser is a function of the thickness of the diffuser.

In a typical IC fabrication procedure, a single fabrication step is used to form a plurality of P + diffusions on a semiconductor substrate such that all of those P + diffusions have the same thickness. Similarly, another fabrication step is used to form a plurality of N + diffusions on the semiconductor substrate such that all those N + diffusions have the same thickness, which is typically, but not necessarily, the same as the thickness of the P + diffusions.

In a typical IC, the thickness of the N + and P + diffusions in a gated diode (such as gated diode 200 of fig. 2) is determined by the requirements of other (i.e., non-ESD protection) circuitry formed on the same semiconductor substrate. Thus, since the thickness of the P + and N + diffusions is determined by those other requirements, in order for a gated diode having the architecture of gated diode 200 to be able to support a sufficient amount of current for ESD protection, the gated diode must be designed with a sufficient number of fingers, with a greater maximum current level requiring more fingers and therefore a greater footprint on the semiconductor substrate for those gated diodes.

For ESD protection devices, it would be advantageous to have a gated diode that does not require excessive substrate real estate.

Disclosure of Invention

According to a first aspect of the invention there is provided an integrated circuit comprising a first gated diode having one or more diode fingers, each diode finger comprising a raised gate and a p-type diffusion and an n-type diffusion on opposite sides of the raised gate, wherein:

the p-type diffusion includes a p-type base region and a p-type annular side region between the p-type base region and the raised gate; and is

The n-type diffusion includes an n-type base region and an n-type annular side region between the n-type base region and the raised gate.

In one or more embodiments, the first gated diode comprises a plurality of the diode fingers.

In one or more embodiments, the integrated circuit further includes a high supply Voltage (VDD) node, a low supply Voltage (VSS) node, an input/output (I/O) pin, and protected circuitry connected to the VDD node, the VSS node, and the I/O pin, wherein:

the first gated diode is part of ESD protection circuitry of the integrated circuit;

the ESD protection circuitry further comprises a second gated diode;

the first gated diode is connected between the I/O pin and the VDD node and is configured to protect the protected circuitry from an overvoltage applied to the I/O pin by shunting current from the I/O pin to the VDD node by way of the first gated diode; and is

The second gated diode is connected between the I/O pin and the VSS node and is configured to protect the protected circuitry from under-voltage applied to the I/O pin by shunting current from the VSS node to the I/O pin by way of the second gated diode.

According to a second aspect of the present invention there is provided a method for fabricating a first gated diode of an integrated circuit, the method comprising:

forming one or more diode fingers of the first gated diode on a substrate, each diode finger comprising a raised gate and a p-type diffusion and an n-type diffusion on opposite sides of the raised gate, wherein:

the p-type diffusion includes a p-type base region and a p-type annular side region between the p-type base region and the raised gate; and is

The n-type diffusion includes an n-type base region and an n-type annular side region between the n-type base region and the raised gate; and

forming at least one first contact connected to each of the raised gate, the p-type diffusion, and the n-type diffusion of each diode finger of the first gated diode.

In one or more embodiments, each diode finger is formed by:

applying a gate material to the substrate corresponding to the raised gate;

removing material from the substrate to form first and second trenches on opposite sides of the gate material to form the raised gate;

applying a p-type dopant to the first trench to form the p-type diffusion; and

applying n-type dopants to the second trench to form the n-type diffusion.

In one or more embodiments, each diode finger is formed by:

applying a substrate material to the substrate to create an elevated region of the substrate corresponding to the elevated gate;

applying a gate material to the elevated regions to form the elevated gates;

applying a p-type dopant to the substrate on one side of the raised gate to form the p-type diffusion; and

applying n-type dopants to the substrate on the opposite sides of the raised gate to form the n-type diffusion.

In one or more embodiments, the method further comprises:

forming one or more diode fingers of a second gated diode on the substrate, each diode finger of the second gated diode comprising a raised gate and a p-type diffusion and an n-type diffusion on opposite sides of the raised gate of the second gated diode, wherein:

the p-type diffusion of the second gated diode includes a p-type base region and a p-type ring-shaped side region between the p-type base region and the raised gate; and is

The n-type diffusion of the second gated diode includes an n-type base region and an n-type annular side region between the n-type base region and the raised gate; and

forming at least one second contact connected to each of the raised gate, the p-type diffusion, and the n-type diffusion of each diode finger of the second gated diode.

In one or more embodiments, the integrated circuit further includes a high supply Voltage (VDD) node, a low supply Voltage (VSS) node, an input/output (I/O) pin, and protected circuitry connected to the VDD node, the VSS node, and the I/O pin;

the first gated diode and the second gated diode are part of ESD protection circuitry of the integrated circuit;

the first gated diode is connected between the I/O pin and the VDD node and is configured to protect the protected circuitry from an overvoltage applied to the I/O pin by shunting current from the I/O pin to the VDD node by way of the first gated diode; and is

The second gated diode is connected between the I/O pin and the VSS node and is configured to protect the protected circuitry from under-voltage applied to the I/O pin by shunting current from the VSS node to the I/O pin by way of the second gated diode.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

Drawings

The invention, together with further objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments taken in conjunction with the accompanying drawings in which:

fig. 1 is a schematic circuit diagram of a known type of ESD protection circuitry;

FIG. 2 is a cross-sectional side view of a region of a semiconductor substrate corresponding to a conventional N +/isolated P-well gated diode;

FIG. 3 is a cross-sectional side view of a region of a semiconductor substrate corresponding to an N +/isolated P-well gated diode, according to one embodiment of the present invention;

FIG. 4 is an enlarged cross-sectional side view of one of the diode fingers of FIG. 3;

5A-5C are cross-sectional side views of a portion of a semiconductor substrate corresponding to the gated diode of FIG. 3 at three different stages during the IC fabrication process for the gated diode of FIG. 3; and

figure 6 is a cross-sectional side view of a region of the semiconductor substrate of figure 3 corresponding to a P +/N well-gated diode, according to one embodiment of the present invention.

Detailed Description

One aspect of the invention is an integrated circuit including a first gated diode comprising one or more diode fingers, each diode finger comprising a raised gate and a p-type diffusion and an n-type diffusion on opposite sides of the raised gate. The p-type diffusion includes a p-type base region and a p-type annular side region between the p-type base region and the raised gate, and the n-type diffusion includes an n-type base region and an n-type annular side region between the n-type base region and the raised gate.

Another aspect of the invention is a method for fabricating a first gated diode of an integrated circuit. One or more diode fingers of a first gated diode are formed on a substrate, each diode finger including a raised gate and a p-type diffusion and an n-type diffusion on opposite sides of the raised gate. The p-type diffusion includes a p-type base region and a p-type annular side region between the p-type base region and the raised gate, and the n-type diffusion includes an n-type base region and an n-type annular side region between the n-type base region and the raised gate. At least one contact is formed to connect to each of the raised gate, the p-type diffusion, and the n-type diffusion of each diode finger of the first gated diode.

In general, it is desirable to limit the footprint of integrated circuit systems formed on a semiconductor substrate. Accordingly, it is desirable to design and configure gated diodes, such as those used in ESD circuitry (such as ESD protection circuitry 100 of fig. 1), to have a relatively small footprint while still supporting sufficiently high current levels for ESD protection.

It is also generally desirable to limit the number of different fabrication steps performed in the fabrication of integrated circuit systems. Thus, it is desirable to form the P + and N + diffusions of the gated diode in ESD protection circuitry during the same fabrication steps used to form other P + and N + diffusions in other circuitry on the same semiconductor substrate.

Fig. 3 is a cross-sectional side view of a region of a semiconductor substrate 302 corresponding to an N +/isolated P-well gated diode 300 that may be used to implement the first diode 112 of fig. 1, according to one embodiment of the invention. Those skilled in the art will appreciate that similar P +/N well gated diodes may be used to implement the second diode 114 of fig. 1.

As shown in fig. 3, gated diode 300 has six diode fingers 310(1) -310(6), each including a dielectric gate 312 above and separating a P + diffusion 314 from an adjacent N + diffusion 316. Note that each of the P + diffusion 314 and the N + diffusion 316 is shared by two adjacent fingers 310, except for the outermost P + diffusion 314(1) and the P + diffusion 314 (4). For example, N + diffusion 316(1) is shared by fingers 310(1) and fingers 310(2), P + diffusion 314(2) is shared by fingers 310(2) and fingers 310(3), and so on.

Each P + diffusion 314 is connected to VSS by way of a corresponding conductive (e.g., metal) contact 318, and each N + diffusion 316 is connected to a corresponding I/O pin (e.g., I/O pin 130 of fig. 1) by way of a corresponding contact 318. Although not shown in fig. 3, each gate 312 is connected to its corresponding P + diffusion 314, for example, by a trace in metal layer M1. Thus, the grid 312(1) is connected to the P + diffusion 314(1), the grid 312(2) and the grid 312(3) are both connected to the common P + diffusion 314(2), the grid 312(4) and the grid 312(5) are both connected to the common P + diffusion 314(3), and the grid 312(6) is connected to the P + diffusion 314 (4).

If and when the voltage applied to the I/O pin begins to drop below VSS by one diode voltage drop (approximately 0.7V), current will begin to flow from the P + diffusion 314 to the N + diffusion 316 as represented by the horizontal arrow in FIG. 3. The magnitude of the current that may flow within gated diode 300 is a function of, among other things, the number of fingers 310 in gated diode 300 and the lateral surface area of the sidewall of each of P + diffusion 314 and N + diffusion 316.

Fig. 4 is an enlarged cross-sectional side view of diode finger 310(3) of fig. 3, diode finger 310(3) including gate 312(3), P + diffusion 314(2), and N + diffusion 316 (2). The P + diffusion 314(2) has a lower base region 410 of thickness T1 and an annular upper side region 420 of height T2. Similarly, the N + diffusion 316(2) has a lower base region 430 of thickness T1 and an annular upper side region 440 of height T2. It should be noted that in other embodiments, the thickness of the two base regions 410 and 430 need not be the same and/or the height of the two annular side regions 420 and 440 need not be the same.

Due to the presence of the intermediate ring-shaped side region 420 and the intermediate ring-shaped side region 440, the gate 312(3) is raised higher than the base regions 410 and 430. The same is true for each gate 312 in the gated diode 300 of fig. 3. Thus, gate 312 of fig. 3 is referred to herein as a "raised gate". This is different from the architecture of the conventional circuit shown in fig. 2, in fig. 2 there is no annular side region, and the bottom of the gate 212 substantially coincides with the top of the P + diffusion 214 and the N + diffusion 216. The gate 212 of fig. 2 is not a raised gate as used herein.

As described further below, in the presently preferred embodiment, the thickness T1 of base region 410 and base region 430 is the same as the thickness of the P + diffusion and N + diffusion in other non-ESD protection circuitry formed on the same semiconductor substrate during the same fabrication steps. Notably, the thickness T1 of base regions 410 and 430 is generally determined by the thickness requirements of those other P + and N + diffusions. However, the height T2 of side region 420 and side region 440 is not directly dependent on the thickness requirements of those other P + and N + diffusions (although the maximum possible value of height T2 would be limited by other characteristics of the integrated circuit system, such as the thickness of the underlying isolation P-well in which the P + and N + diffusions are formed).

Thus, for an integrated circuit system having the same diffuser thickness requirements as the integrated circuit system of fig. 2, the lateral surface area of each of the P + and N + diffusers 314 and 316 of fig. 3 and 4 will be greater than the lateral surface area of each of the P + and N + diffusers 214 and 216 of fig. 2 due to the presence of the annular side region 420 and 440 in the diffusers 314 and 316 of fig. 3 and 4. Specifically, the lateral surface area of each base region 410 and 430 will be substantially equal to the lateral surface area of each of the P + diffusion 214 and the N + diffusion 216 of fig. 2. Thus, due to the presence of the annular side region 420 and the annular side region 440, the total lateral surface area of each of the P + diffuser 314 and the N + diffuser 316 will be greater than the total lateral surface area of each of the P + diffuser 214 and the N + diffuser 216 of fig. 2. Thus, each finger 310 of fig. 3 will be able to conduct more current than each finger 210 of fig. 2. Thus, the gated diode of the architecture with the gated diode 300 of fig. 3 may be implemented with fewer fingers and thus have a smaller IC footprint, while supporting an equivalent maximum current level, as compared to the corresponding gated diode of the architecture with the gated diode 200 of fig. 2.

Fig. 5A-5C are cross-sectional side views of a portion of a semiconductor substrate 302 corresponding to the gated diode 300 of fig. 3 at three different stages during the IC fabrication process for the gated diode 300.

Specifically, fig. 5A shows the semiconductor substrate 302 after the following fabrication steps have been performed:

selectively applying N-type dopants to form a deep N-well 502 in the p-type substrate 302;

selectively applying P-type dopants to form an isolated P-well 504 over the deep N-well 502;

selectively applying N-type dopants to form an N + guard ring 506 around the isolated P-well 504; and

six gates 312(1) -312(6) are formed on top of the isolated P-well 504.

Those skilled in the art will appreciate that there are different possible techniques for performing each of these different fabrication steps. Typical techniques involve photolithography, where selective areas of the substrate 302 are masked to form corresponding features. One possible technique for forming gate 312 involves growing a uniform dielectric layer on top of substrate 302 and then growing a polysilicon or metal conductive layer, selectively masking regions of the dielectric and conductive layers corresponding to gate 312, and then etching away the conductive and dielectric materials from the unmasked regions (wet or dry).

Fig. 5B shows the semiconductor substrate 302 after seven trenches ED (1) -ED (7) have been formed in the substrate 302 of fig. 5A. In one possible technique, with the masking material used to form the six gates 312(1) - (312) (6) held in place (and after additional masking material is added over the exposed top surfaces of the deep N-well 502 and N + guard ring 506), the material from the isolation P-well 504 is etched away (wet or dry) to form the trench ED. It should be noted that the depth of the trench ED is substantially equal to the height T2 of the annular sidewalls 420 and 440 of the P + and N + diffusions 314 and 316 of fig. 3 and 4.

Fig. 5C shows the semiconductor substrate 302 after four P + diffusions 314(1) -314(4) and three N + diffusions 316(1) -316(3) have been formed in the substrate 302 of fig. 5B. In one possible technique, the P + diffusion 314 and the N + diffusion 316 are formed using the following fabrication steps:

selectively applying P-type dopant to form four P + diffusions 314(1) -314(4) in the isolated P-well 504;

selectively applying N-type dopant to form three N + diffusions 316(1) -316(3) in the isolated P-well 504; and

deposit dielectric over silicon and gate (not shown in the figure) and form contact 318.

In one possible technique, with the masking material used to form the seven trenches ED (1) -ED (7) remaining in place, and after additional masking material is added over the trenches ED (2), ED (4), and ED (6), P-type dopants are applied to the four unmasked trenches ED (1), ED (3), ED (5), and ED (7) to form the four P + diffusions 314(1) -314 (4). Then, with masking material removed from over the trenches ED (2), ED (4), and ED (6), and after additional masking material is added over the four P + diffusions 314(1) -314(4), N-type dopants are applied to the three unmasked trenches ED (2), ED (4), and ED (6) to form three N + diffusions 316(1) -316 (3). Note that in an alternative technique, the N + diffusion 316 is formed before the P + diffusion 314.

As represented in fig. 5C, when P-type dopants are added to form the P + diffusion 314, the P-type dopants are implanted into the sidewalls of the corresponding trenches ED and the bottoms of those trenches ED to produce the P + diffusion 314 having both base regions (such as base regions 410) and annular side regions (such as annular side regions 420). Similarly, when N-type dopants are added to form the N + diffusions 316, N-type dopants are implanted into the sidewalls of the corresponding trenches ED and the bottoms of those trenches ED to create N + diffusions 316 with both base regions (such as base regions 430) and annular side regions (such as annular side regions 440).

In one possible implementation based on 40 nanometer IC technology, the gated diode implemented for the first diode 112 of fig. 1 using the architecture of fig. 2 has 50 fingers similar to the fingers 310 of fig. 3, each finger having a gate length of about 0.27um, a gate-to-gate distance of about 0.36um, a gate height of about 1000A (i.e., T2 of fig. 4), and a base thickness of about 1000A (i.e., T1 of fig. 4). Such gated diodes may be implemented with a footprint that is about 35% less than the footprint of a gated diode implemented using the conventional architecture of fig. 2 to support an equivalent maximum current.

Fig. 5A-5C illustrate one possible technique for fabricating the gated diode 300 of fig. 3, the gated diode 300 having a raised gate 312 and a P + diffusion 314 and an N + diffusion 316 having both base regions and annular side regions. In the technique of fig. 5A-5C, the elevated gate 312 is formed by etching away the substrate material after applying the dielectric gate material to form a trench ED. In an alternative technique, which will be understood by those skilled in the art, a similar raised gate may be formed by selectively growing an underlying substrate material to form a trench ED prior to applying the dielectric gate material.

Fig. 6 is a cross-sectional side view of a region of a semiconductor substrate corresponding to a P +/N well-gated diode 600 that may be used to implement the second diode 114 of fig. 1, according to one embodiment of the invention. Those skilled in the art will appreciate that gated diode 600 can be fabricated using processing steps similar to those used to form gated diode 300 of fig. 3.

It will be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. In particular, it should be understood that the present invention may be embodied in the following forms.

Although the present invention has been described in the context of the gated diode 300 of fig. 3 having six fingers 310(1) - (310) (6), those skilled in the art will appreciate that the gated diode of the present invention may have any suitable number of one or more fingers.

Although the present invention has been described in the context of a gated diode 300 formed on a P-type semiconductor substrate 302 having a deep N-well 502 and an isolated P-well 504, those skilled in the art will appreciate that the gated diode of the present invention may be implemented on other suitable types and configurations of semiconductor substrates having different well structures. For example, in some alternative embodiments, each P + diffusion 314 is implemented within a P-type lightly doped drain (PLDD) region, and/or each N + diffusion 316 is implemented within an N-type ldd (nldd) region.

The semiconductor substrate 302 may be any suitable semiconductor material such as, but not limited to, silicon, germanium, silicon-on-insulator (SOI), and GaAs.

Although the present invention has been described in the context of a gated diode for ESD protection circuitry, those skilled in the art will appreciate that the gated diode of the present invention may also be used in other types of integrated circuitry.

Signals and corresponding ends, nodes, ports, or paths may be referred to by the same name and may be interchanged for the purposes of this document.

For the purposes of this specification, the terms "couple", "coupling", "coupled", "connect", "connecting", or "connected" refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the insertion of one or more additional elements is contemplated, although not required. Rather, the terms "directly coupled," "directly connected," and the like imply the absence of such additional elements.

The present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.