阅读说明：本技术 系统级芯片及其测试方法、存储介质、终端 (System-on-chip and test method, storage medium and terminal thereof ) 是由 孟宪余 于 2019-11-25 设计创作，主要内容包括：一种系统级芯片及其测试方法、存储介质、终端,系统级芯片包括：UART控制器,用以产生UART信号；JTAG控制器,用以产生JTAG信号；USB端口物理层,用以产生USB信号；数据选择器,所述数据选择器的输入端分别接入所述UART信号、所述JTAG信号和所述USB信号,用以选取所述UART信号、所述JTAG信号和所述USB信号中一路信号进行输出,所述数据选择器的输出端耦接所述系统级芯片的外接管脚。本发明技术方案能够提升芯片测试的效率。(A system-on-chip and test method, storage medium, terminal thereof, the system-on-chip includes: the UART controller is used for generating a UART signal; a JTAG controller for generating JTAG signals; a USB port physical layer for generating a USB signal; the input end of the data selector is respectively connected with the UART signal, the JTAG signal and the USB signal and used for selecting one of the UART signal, the JTAG signal and the USB signal to output, and the output end of the data selector is coupled with an external pin of the system-level chip. The technical scheme of the invention can improve the efficiency of chip testing.)

1. A system-on-chip, comprising:

the UART controller is used for generating a UART signal;

a JTAG controller for generating JTAG signals;

a USB port physical layer for generating a USB signal;

the input end of the data selector is respectively connected with the UART signal, the JTAG signal and the USB signal, the data selector is used for selecting one of the UART signal, the JTAG signal and the USB signal to output, and the output end of the data selector is coupled with an external pin of the system-level chip.

2. The system-on-chip of claim 1, further comprising:

and the USB pin is coupled with the output end of the data selector to receive the signal output by the data selector.

3. The system-on-chip of claim 1, further comprising:

and the input end of the signal amplifier is coupled with the output end of the data selector, and the output end of the signal amplifier is coupled with an external pin of the system-on-chip.

4. The system-on-chip of claim 1, wherein the UART signals comprise a UART transmit signal and a UART receive signal, the JTAG signals comprise a JTAG input-output signal and a JTAG clock signal, and the USB signals comprise a data positive signal and a data negative signal.

5. The system-on-chip of claim 4, wherein the data selector comprises:

the input end of the first data selector is respectively connected with a first signal for selecting one path of signal in the first signal to output, the first signal comprises one signal of the UART sending signal and the UART receiving signal, one signal of the JTAG input and output signal and the JTAG clock signal, and one signal of the data positive signal and the data negative signal;

and the input end of the second data selector is respectively connected with a second signal for selecting one path of signal in the second signals to output, the second signal comprises the other signal in the UART sending signal and the UART receiving signal, the other signal in the JTAG input and output signal and the JTAG clock signal, and the other signal in the data positive signal and the data negative signal.

6. The system-on-chip of claim 5, further comprising:

the input end of the first signal amplifier is coupled to the output end of the first data selector, and the output end of the first signal amplifier is coupled to an external pin of the system-on-chip;

and the input end of the second signal amplifier is coupled to the output end of the second data selector, and the output end of the second signal amplifier is coupled to an external pin of the system-on-chip.

7. The system-on-chip of claim 6, further comprising:

a USB pin; the USB pins comprise a data positive signal pin and a data negative signal pin;

the output end of the first signal amplifier is coupled with one pin of the positive signal pin and the negative data signal pin; the output end of the second signal amplifier is coupled with the other pin of the positive signal pin and the negative signal pin.

8. The method for testing a system-on-chip according to any one of claims 1 to 7, comprising:

when testing UART signals or JTAG signals, enabling the data selector to select the UART signals or the JTAG signals;

and outputting the selected UART signal or the JTAG signal to an external test instrument through an external pin of the system-on-chip.

9. A storage medium having stored thereon computer instructions which, when executed, perform the steps of the test method of claim 8.

10. A terminal comprising a memory and a processor, the memory having stored thereon computer instructions executable on the processor, wherein the processor, when executing the computer instructions, performs the steps of the test method of claim 8.

11. A terminal, characterized in that it comprises a system-on-chip according to any of claims 1 to 7.

Technical Field

The invention relates to the technical field of chips, in particular to a system-level chip, a test method thereof, a storage medium and a terminal.

Background

In the current System on Chip (SoC) design of a mobile terminal, data transmission between a Universal Asynchronous Receiver/Transmitter (UART), a Universal Serial Bus (USB), and a Joint Test Action Group (JTAG) is independent. Moreover, in mass production products, only a USB interface is usually set for connecting an external device to the mobile terminal product.

However, when testing (debug) the UART or JTAG of the mobile terminal, test points are reserved in the mobile terminal, and the mobile phone and the test points are soldered by flying leads. When the flying wire is welded, the shielding case is often required to be removed, so that the testing efficiency is low, and the hardware of the mobile phone can be damaged, so that the problem site is damaged.

Disclosure of Invention

The invention solves the technical problem of how to improve the efficiency of chip testing.

To solve the above technical problem, an embodiment of the present invention provides a system-on-chip, where the system-on-chip includes: the UART controller is used for generating a UART signal; a JTAG controller for generating JTAG signals; a USB port physical layer for generating a USB signal; the input end of the data selector is respectively connected with the UART signal, the JTAG signal and the USB signal and used for selecting one of the UART signal, the JTAG signal and the USB signal to output, and the output end of the data selector is coupled with an external pin of the system-level chip.

Optionally, the system on chip further includes: and the USB pin is coupled with the output end of the data selector to receive the signal output by the data selector.

Optionally, the system on chip further includes: and the input end of the signal amplifier is coupled with the output end of the data selector, and the output end of the signal amplifier is coupled with an external pin of the system-on-chip.

Optionally, the UART signal includes a UART transmit signal and a UART receive signal, the JTAG signal includes a JTAG input-output signal and a JTAG clock signal, and the USB signal includes a data positive signal and a data negative signal.

Optionally, the data selector includes: the input end of the first data selector is respectively connected with a first signal for selecting one path of signal in the first signal to output, the first signal comprises one signal of the UART sending signal and the UART receiving signal, one signal of the JTAG input and output signal and the JTAG clock signal, and one signal of the data positive signal and the data negative signal; and the input end of the second data selector is respectively connected with a second signal for selecting one path of signal in the second signals to output, the second signal comprises the other signal in the UART sending signal and the UART receiving signal, the other signal in the JTAG input and output signal and the JTAG clock signal, and the other signal in the data positive signal and the data negative signal.

Optionally, the system on chip further includes: the input end of the first signal amplifier is coupled to the output end of the first data selector, and the output end of the first signal amplifier is coupled to an external pin of the system-on-chip; and the input end of the second signal amplifier is coupled to the output end of the second data selector, and the output end of the second signal amplifier is coupled to an external pin of the system-on-chip.

Optionally, the system on chip further includes: a USB pin; the USB pins comprise a data positive signal pin and a data negative signal pin; the output end of the first signal amplifier is coupled with one pin of the positive signal pin and the negative data signal pin; the output end of the second signal amplifier is coupled with the other pin of the positive signal pin and the negative signal pin.

In order to solve the above technical problem, an embodiment of the present invention further discloses a test method based on the system-on-chip, where the test method includes: when testing UART signals or JTAG signals, enabling the data selector to select the UART signals or the JTAG signals; and outputting the selected UART signal or the JTAG signal to an external test instrument through an external pin of the system-on-chip.

The embodiment of the invention also discloses a storage medium, on which computer instructions are stored, and is characterized in that the computer instructions are executed when running to execute the steps of the test method of claim 8.

The embodiment of the invention also discloses a terminal which comprises a memory and a processor, wherein the memory is stored with a computer instruction capable of running on the processor, and the processor executes the steps of the test method when running the computer instruction.

The embodiment of the invention also discloses a terminal which comprises the system-on-chip.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the technical scheme of the invention, the system-level chip comprises a UART controller used for generating UART signals; a JTAG controller for generating JTAG signals; a USB port physical layer for generating a USB signal; the input end of the data selector is respectively connected with the UART signal, the JTAG signal and the USB signal and used for selecting one of the UART signal, the JTAG signal and the USB signal to output, and the output end of the data selector is coupled with an external pin of the system-level chip. According to the technical scheme, the UART signals, the JTAG signals and the USB signals are output through the same output port through the data selector, namely the output end of the data selector is coupled with the external pin of the system-on-chip, so that the UART controller and the JTAG controller can be directly connected to a test instrument through the external pin of the system-on-chip when being tested, the disassembling operation of terminal equipment is avoided, and the test efficiency is improved.

Drawings

FIG. 1 is a diagram illustrating a chip structure in the prior art;

FIG. 2 is a diagram illustrating a system-on-chip architecture according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of another system-on-chip according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating a method for testing a system-on-chip according to an embodiment of the invention.

Detailed Description

As shown in fig. 1, the chip in the prior art includes UART101, JTAG102, and USB103, wherein UART signals generated by UART101, JTAG signals generated by JTAG102, and USB signals generated by USB103 have respective signal paths. Specifically, the UART signal interacts with other chips in the mobile terminal through internal interfaces a, b; JTAG signals are interacted with other chips in the mobile terminal through internal interfaces c and d; the USB signal interacts with other chips in the mobile terminal through internal interfaces e and f. In addition, the internal interfaces e, f may also be coupled with external interfaces g, h (which may be referred to as USB interfaces) provided on the hardware system 30 of the mobile terminal, so that USB signals interact with external devices through the external interfaces g, h.

Due to the structure of the chip in the prior art, when testing (debug) is performed on the UART or JTAG of the mobile terminal, test points are reserved in the mobile terminal, and meanwhile, the mobile phone and the test points are required to be detached and soldered by flying wires. When the flying wire is welded, the shielding case is often required to be removed, so that the testing efficiency is low, and the hardware of the mobile phone can be damaged, so that the problem site is damaged.

According to the technical scheme, the UART signals, the JTAG signals and the USB signals are output through the same output port through the data selector, namely the output end of the data selector is coupled with the external pin of the system-on-chip, so that the UART controller and the JTAG controller can be directly connected to a test instrument through the external pin of the system-on-chip when being tested, the disassembling operation of terminal equipment is avoided, and the test efficiency is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 is a schematic structural diagram of a system-on-chip according to an embodiment of the invention.

The system-on-chip 20 shown in fig. 2 may be built in a mobile terminal device, such as a mobile phone, a computer, a tablet computer, and so on.

Referring to fig. 2, the system-on-chip 20 may include a UART controller 201, a JTAG controller 202, a USB port physical layer 203, and a data selector 204.

The UART controller 201 is configured to generate a UART signal; JTAG controller 202 is configured to generate JTAG signals; the USB port phy 203 is used to generate USB signals. The input end of the data selector 204 is respectively connected to the UART signal, the JTAG signal, and the USB signal, the data selector 204 is configured to select one of the UART signal, the JTAG signal, and the USB signal for output, and the output end of the data selector 204 is coupled to the external pins g and h of the system-on-chip 20.

It should be noted that the data selector 204 may also be referred to as a data multiplexer, a multiplexer, and the like, which is not limited in the embodiments of the present invention.

In this embodiment, the external pins g and h may be pins for connecting an external device with the mobile terminal. The external pins g, h may be provided on the hardware system 40 of the mobile terminal. For example, the external pins g, h may be USB interfaces of the mobile terminal.

Specifically, the UART controller 201, the JTAG controller 202, and the USB port physical layer 203 may refer to chip internal circuits. In an actual application scenario, the UART controller 201, the JTAG controller 202, and the USB port physical layer 203 may also be any other practicable names, and the embodiment of the present invention is not limited thereto.

In the embodiment of the present invention, the UART signal, the JTAG signal, and the USB signal are output through the same output port through the data selector 204, that is, the output port of the data selector 204 is coupled to the external pin of the system-on-chip 20, so that when the UART controller 201 and the JTAG controller 202 are tested, the UART signal can be directly connected to a test instrument through the external pin of the system-on-chip 20, thereby avoiding a disassembly operation of a terminal device and improving the test efficiency.

In a non-limiting embodiment of the present invention, the system-on-chip 20 shown in fig. 2 may further include a USB pin (not shown) coupled to the output terminal of the data selector 204 for receiving the signal output by the data selector 204.

The USB pins in this embodiment may be pins of the system-on-chip 20. In the prior art, it can only output USB signals, and in this embodiment, the USB pin may output any one of UART signals, the JTAG signals, and the USB signals. That is, through the coupling relationship between the USB pin and the external pins g and h, the UART signal, the JTAG signal and the USB signal can be transmitted to the external device through the external pins g and h.

In a non-limiting embodiment of the present invention, the system-on-chip 20 shown in fig. 2 may further include a signal amplifier (not shown), an input of the signal amplifier is coupled to the output of the data selector 204, and an output of the signal amplifier is coupled to an external pin of the system-on-chip 20.

In this embodiment, since the signal provided by the system-on-chip 20 is usually weak and can be amplified before being output, a signal amplifier may be disposed in the system-on-chip 20 for amplifying the signal output by the data selector 204, that is, amplifying the UART signal, the JTAG signal, or the USB signal.

In a non-limiting embodiment of the present invention, the UART Signal includes a UART transmit Signal (transmit Signal) and a UART Receive Signal (Receive Signal), the JTAG Signal includes a JTAG input output Signal (SWDIO) and a JTAG clock Signal (SWCLK), and the USB Signal includes a Data Positive Signal (DP) and a Data negative Signal (Data Minus, DM).

That is, each type of signal includes two signals. When the subsequent data selector 201 outputs each type of signal, the two signals may be selected and output separately.

Further, referring to fig. 2 and 3 together, the data selector 204 shown in fig. 2 may include the first data selector 2041 and the second data selector 2042 shown in fig. 3.

The input end of the first data selector 2041 is respectively connected to a first signal for selecting one of the first signals to output, the first signal is selected from one of the UART transmission signal and the UART reception signal, one of the JTAG input/output signal and the JTAG clock signal, and one of the data positive signal and the data negative signal; the input end of the second data selector 2042 is respectively connected to a second signal for selecting one path of signal in the second signal to output, where the second signal is selected from another signal in the UART sending signal and the UART receiving signal, another signal in the JTAG input/output signal and the JTAG clock signal, and another signal in the data positive signal and the data negative signal.

In this embodiment, three signals of the above six signals (i.e., the UART transmit signal, the UART receive signal, the JTAG input/output signal, the JTAG clock signal, the data positive signal, and the data negative signal) may be input to the input terminal of the first data selector 2041, and the remaining three signals may be input to the input terminal of the second data selector 2042.

Further, referring to fig. 3, the system-on-chip 20 may further include a first signal amplifier 2051 and a second signal amplifier 2052.

An input terminal of the first signal amplifier 2051 is coupled to the output terminal of the first data selector 2041, and an output terminal of the first signal amplifier 2051 is coupled to an external pin of the system-on-chip 20; an input terminal of the second signal amplifier 2052 is coupled to the output terminal of the second data selector 2042, and an output terminal of the second signal amplifier 2052 is coupled to an external pin of the system-on-chip 20.

In this embodiment, the output signals of the first data selector 2041 and the second data selector 2042 are amplified by the first signal amplifier 2051 and the second signal amplifier 2052, respectively, and then output to an external device.

In an embodiment of the present invention, the switching of the output signal of the data selector may be implemented by a preset boot loader (bootloader). The specific switching operation may be completed in a Read-Only Memory (ROM) stage during booting, or in a bootloader stage.

Or, the switching of the output signal of the data selector can be realized through a preset key or a combination of the keys after the terminal is started.

Or after the terminal is normally started, inputting a password to enable the terminal to enter a special engineering mode, and switching the output signal of the data selector in the engineering mode; and exiting the engineering mode to test the signal after the switching is finished.

Still further, the system-on-chip 20 may further include USB pins; the USB pins comprise a data positive signal pin and a data negative signal pin;

an output end of the first signal amplifier 2051 is coupled to one of the positive signal pin and the negative data signal pin; an output terminal of the second signal amplifier 2052 is coupled to the other of the positive signal pin and the data negative signal pin.

In this embodiment, the USB pins may be an external pin g and an external pin h. The external pin g can be a data positive signal pin, and the external pin h can be a data negative signal pin; alternatively, the external pin h may be a data positive signal pin, and the external pin g may be a data negative signal pin.

Referring to fig. 4, an embodiment of the present invention further discloses a method for testing a system-level chip, where the method includes the following steps:

step S401: when testing UART signals or JTAG signals, enabling the data selector to select the UART signals or the JTAG signals;

step S402: and outputting the selected UART signal or the JTAG signal to an external test instrument through an external pin of the system-on-chip.

It should be noted that the sequence numbers of the steps in this embodiment do not represent a limitation on the execution sequence of the steps.

In the case where the UART signal or the JTAG signal needs to be tested, the UART signal or the JTAG signal needs to be output to an external test instrument. In this embodiment, the data selector may be controlled by the control signal, so that the data selector selects a signal to be tested (a UART signal or a JTAG signal), and outputs the selected signal to be tested to the test instrument.

Compared with the mode that parts are required to be disassembled and test points are welded by flying leads in the prior art, the test method provided by the embodiment of the invention is simple and easy to operate, and can improve the test efficiency.

For more contents of the working principle and the working mode of the test method of the system-on-chip, reference may be made to the relevant descriptions in fig. 1 to fig. 2, which are not described herein again.

The embodiment of the invention also discloses a storage medium, which stores computer instructions, and the computer instructions can execute the steps of the method shown in the figure 4 when running. The storage medium may include ROM, RAM, magnetic or optical disks, etc. The storage medium may further include a non-volatile memory (non-volatile) or a non-transitory memory (non-transient), and the like.

The embodiment of the invention also discloses a terminal which can comprise a memory and a processor, wherein the memory is stored with computer instructions capable of running on the processor. The processor, when executing the computer instructions, may perform the steps of the method shown in fig. 4. Alternatively, the terminal may also include the system-on-chip 20 shown in fig. 2 or fig. 3.

The terminal includes, but is not limited to, a mobile phone, a computer, a tablet computer and other terminal devices.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.