阅读说明：本技术 磁存储器 (Magnetic memory ) 是由 上田善宽 宫野信治 麦可·阿尔诺·坎萨 近藤刚 于 2019-02-25 设计创作，主要内容包括：根据实施方式,提供一种包含磁性体柱、移位控制电路及写入控制电路的磁存储器。移位控制电路在写入数据时使电流流到磁性体柱。写入控制电路在将第1值的数据写入到磁性体柱的情况下,使电流流到写入线。写入线是通过磁性体柱的一端附近的线。写入控制电路在将第2值的数据写入到磁性体柱的情况下,不使电流流到写入线。(According to an embodiment, a magnetic memory is provided that includes a magnetic pillar, a shift control circuit, and a write control circuit. The shift control circuit causes a current to flow to the magnetic body pillar when writing data. The write control circuit causes a current to flow to the write line when data of a 1 st value is written to the magnetic body pillar. The write line is a line passing near one end of the magnetic body pillar. The write control circuit does not cause a current to flow to the write line when the 2 nd value data is written to the magnetic body pillar.)

1. A magnetic memory is characterized by comprising:

a magnetic body column;

a shift control circuit connected to the magnetic body pillar, and configured to cause a current to flow to the magnetic body pillar when data is written; and

and a write control circuit that, when writing data of a 1 st value to the magnetic body pillar, causes a current to flow to a write line passing through a vicinity of one end of the magnetic body pillar, and when writing data of a 2 nd value to the magnetic body pillar, does not cause a current to flow to the write line.

2. The magnetic memory according to claim 1, wherein the write control circuit causes a current to flow to the write line before writing the 1 st bit of data when receiving a write operation command.

3. The magnetic memory according to claim 2, wherein the write control circuit causes a current to flow to the write line in a 1 st direction before writing the 1 st bit of data, and causes a current to flow to the write line in a 2 nd direction opposite to the 1 st direction in a case where the 1 st value of data is written to the magnetic body pillar for the first time after the 1 st bit.

4. The magnetic memory according to claim 1, wherein the write control circuit causes a current to flow to the write line in a 1 st direction to write the 1 st value of data to the magnetic body pillar during a 1 st period, and causes a current to flow to the write line in a 2 nd direction opposite to the 1 st direction to write the 1 st value of data to the magnetic body pillar during a 2 nd period after the 1 st period.

5. The magnetic memory according to claim 4, wherein the write control circuit causes a current to flow to the write line in the 1 st direction to write the 1 st value of data to the magnetic body pillar during a 3 rd period after the 2 nd period.

6. The magnetic memory according to claim 4, wherein the write control circuit causes a current to flow to the write line in the 2 nd direction to write an initial value to the magnetic body pillar during a 4 th period before the 1 st period.

7. The magnetic memory of claim 1, wherein the shift control circuit causes current to flow to the magnetic body pillar if the 1 st value of data is written to the magnetic body pillar, and causes current to flow to the magnetic body pillar if the 2 nd value of data is written to the magnetic body pillar.

8. The magnetic memory according to claim 4, wherein the shift control circuit causes a current to flow to the magnetic body pillar in a 3 rd direction during a 5 th period between the 1 st period and the 2 nd period.

9. The magnetic memory according to claim 5, wherein the shift control circuit causes current to flow to the magnetic pillar in the 3 rd direction during a 6 th period between the 2 nd period and the 3 rd period.

10. The magnetic memory according to claim 6, wherein the shift control circuit causes current to flow to the magnetic pillar in the 3 rd direction during a 7 th period between the 4 th period and the 1 st period.

11. A magnetic memory is characterized by comprising:

a magnetic body column;

a shift control circuit connected to the magnetic body column;

a write line passing near the magnetic body pillar and having a 1 st end and a 2 nd end; and

and a write control circuit configured to make a 1 st potential difference between the 1 st end and the 2 nd end when the 1 st value data is written in the magnetic column larger than a 2 nd potential difference between the 1 st end and the 2 nd end when the 2 nd value data is written in the magnetic column.

12. The magnetic memory according to claim 11, wherein the write control circuit generates the 1 st potential difference between the 1 st terminal and the 2 nd terminal before writing the 1 st bit of data when receiving a write operation command.

13. The magnetic memory according to claim 12, wherein the write control circuit sets the voltage of the 1 st terminal to be larger than the voltage of the 2 nd terminal before writing the data of the 1 st bit, and sets the voltage of the 2 nd terminal to be larger than the voltage of the 1 st terminal in a case where the data of the 1 st value is written to the magnetic body pillar for the first time after the 1 st bit.

14. The magnetic memory according to claim 11, wherein the write control circuit sets the voltage of the 1 st terminal to be greater than the voltage of the 2 nd terminal during a 1 st period in which the 1 st value of data is written, and sets the voltage of the 2 nd terminal to be greater than the voltage of the 1 st terminal during a 2 nd period in which the 1 st value of data is written after the 1 st period.

15. The magnetic memory according to claim 14, wherein the write control circuit sets the voltage of the 1 st terminal to be greater than the voltage of the 2 nd terminal during a 3 rd period in which the data of the 1 st value is written after the 2 nd period.

16. The magnetic memory according to claim 14, wherein the write control circuit sets the voltage of the 2 nd terminal to be larger than the voltage of the 1 st terminal during a 4 th period before the 1 st period.

17. The magnetic memory of claim 11, wherein the magnetic body pillar has a 3 rd end and a 4 th end, and

the shift control circuit sets the voltage of the 3 rd terminal to be greater than the voltage of the 4 th terminal in a case where the 1 st value of data is written to the magnetic body pillar, and sets the voltage of the 3 rd terminal to be greater than the voltage of the 4 th terminal in a case where the 2 nd value of data is written to the magnetic body pillar.

18. The magnetic memory according to claim 14, wherein the shift control circuit sets the voltage of the 3 rd terminal to be greater than the voltage of the 4 th terminal during a 5 th period between the 1 st period and the 2 nd period.

19. The magnetic memory according to claim 15, wherein the shift control circuit sets the voltage of the 3 rd terminal to be greater than the voltage of the 4 th terminal during a 6 th period between the 2 nd period and the 3 rd period.

20. The magnetic memory according to claim 16, wherein the shift control circuit sets the voltage of the 3 rd terminal to be greater than the voltage of the 4 th terminal during a 7 th period between the 4 th period and the 1 st period.

Technical Field

The present embodiment relates to a magnetic memory.

Background

Magnetic memories having magnetic pillars form magnetic regions in the magnetic pillars and write information. In this case, it is desirable to operate the magnetic memory with low power consumption.

Disclosure of Invention

One embodiment provides a magnetic memory capable of operating with low power consumption.

According to the present embodiment, a magnetic memory including a magnetic pillar, a shift control circuit, and a write control circuit is provided. The shift control circuit causes a current to flow to the magnetic body pillar when writing data. The write control circuit causes a current to flow to the write line when data of a 1 st value is written to the magnetic body pillar. The write line is a line passing near one end of the magnetic body pillar. The write control circuit does not cause a current to flow to the write line when the 2 nd value data is written to the magnetic body pillar.

Drawings

Fig. 1 is a block diagram showing a configuration of a magnetic memory according to an embodiment.

Fig. 2 is a circuit diagram showing a configuration of a memory cell array in the embodiment.

Fig. 3 is a perspective view showing the structure of the memory cell array in the embodiment.

Fig. 4 is a diagram showing a method of recording information on the magnetic material column according to the embodiment.

Fig. 5A to 5R are diagrams illustrating a write operation and a read operation in the embodiment.

Fig. 6A to 6E are diagrams illustrating a writing operation in the embodiment.

Fig. 7 is a diagram showing a circuit used for a write operation in the embodiment.

Fig. 8 is a flowchart showing a writing method in the embodiment.

Fig. 9 is a waveform diagram showing a write operation in the embodiment.

Fig. 10A to 10D are diagrams illustrating a reading operation in the embodiment.

Fig. 11 is a diagram showing a circuit used for a read operation in the embodiment.

Fig. 12 is a diagram showing a memory chip in which the magnetic memory according to the embodiment is arranged.

Fig. 13 is a diagram showing a memory system mounted on a memory chip on which the magnetic memory according to the embodiment is disposed.

Detailed Description

Hereinafter, the magnetic memory according to the embodiment will be described in detail with reference to the drawings. The present invention is not limited to the embodiment.

(embodiment mode)

The magnetic memory of the embodiment will be explained. The magnetic memory has magnetic pillars, and magnetic regions are formed in the magnetic pillars and information is written thereto. For example, a 1 st writing method of writing a binary value in the magnetization direction of each magnetic region in a magnetic body pillar is considered. In the 1 st writing method, each time a domain wall in a magnetic pillar is displaced by causing a displacement current to flow to the magnetic pillar, a current in a direction corresponding to data to be written is caused to flow to a write line passing near one end of the magnetic pillar. In the 1 st write mode, a current in the 1 st direction is caused to flow to the write line when the 1 st value data is written, and a current in the 2 nd direction opposite to the 1 st direction is caused to flow to the write line when the 2 nd value data is written. This causes an induced magnetic field in a direction corresponding to the data to be written to be generated in a region near one end of the magnetic pillar, thereby performing writing. In the 1 st write scheme, a relatively large current for generating an induced magnetic field is supplied to the write line every time writing is performed, and thus power consumption tends to increase.

Therefore, in this embodiment, in the magnetic memory, a current is applied to the write line so as to form a magnetic domain wall when data of the 1 st value is written, and a current is not applied to the write line so as not to form a magnetic domain wall when data of the 2 nd value is written, thereby achieving low power consumption of the magnetic memory.

Specifically, in the magnetic memory, a 2 nd write scheme different from the 1 st write scheme is adopted. The magnetic memory writes data to the magnetic pillars in the 2 nd writing mode. In the 2 nd writing method, a binary value (1 st value or 2 nd value) is written depending on the presence of a magnetic domain wall in a nonmagnetic column. When the magnetic domain is observed in units of the magnetic domain shifted by the shift current, a state in which a domain wall exists between the magnetic domain and the magnetic domain adjacent thereto due to the difference in magnetization direction between the magnetic domain and the magnetic domain adjacent thereto can be set to a 1 st value written state. The 1 st value can be set to "1", for example. The state in which the magnetization directions of the magnetic region and the adjacent magnetic region are the same and no domain wall exists between the magnetic region and the adjacent magnetic region can be set to the 2 nd value written state. The 2 nd value can be set to "0", for example.

In the 2 nd write mode, the magnetic memory causes a current to flow in a direction forming a magnetic domain having a magnetization direction opposite to a magnetization direction of a magnetic domain in the vicinity of one end of the magnetic body, for a write line, based on the data of the 1 st value. Thereby, an induced magnetic field is generated around the write line, the direction of magnetization of the uppermost magnetic region near one end of the magnetic body is inverted from the direction of magnetization of the magnetic region below the uppermost magnetic region, a magnetic domain wall is formed between the uppermost magnetic region and the magnetic region below the uppermost magnetic region, and the 1 st value is written.

The magnetic memory does not pass current to the write line based on the 2 nd value of data. Thus, no induced magnetic field is generated around the write line, the direction of magnetization of the uppermost magnetic region near one end of the magnetic material is kept equal to the direction of magnetization of the magnetic region below the uppermost magnetic region, and no domain wall is formed between the uppermost magnetic region and the magnetic region below the uppermost magnetic region, and as a result, the 2 nd value is written.

More specifically, the magnetic memory 1 may be configured as shown in fig. 1. Fig. 1 is a block diagram showing a configuration of a magnetic memory 1.

The magnetic memory 1 shown in fig. 1 includes a memory cell array 10, a Word Line (WL) decoder 20, a Bit Line (BL) decoder 30, a read circuit 40, a shift control circuit 50, a Field Line (FL) driver 60, a write control circuit 80, and a controller 70.

The memory cell array 10 has a plurality of magnetic body pillars. Each magnetic pillar includes a plurality of magnetic regions (or magnetic domain walls) for storing data. In the memory cell array 10, magnetic material pillars are arranged in a matrix. The magnetic pillar is electrically connected between the word line WL and the bit line BL. The magnetic body pillar is also called a magnetic thin line or a magnetic storage thin line. Details of the magnetic body pole will be described later.

The word line decoder (WL decoder) 20 selects 1 word line from the plurality of word lines WL based on the row address. The bit line decoder (BL decoder) 30 selects 1 bit line from the plurality of bit lines BL based on the column address. The read circuit 40 has a sense amplifier, and reads data from the magnetic body column in the memory cell array 10. The shift control circuit 50 applies a voltage for moving a magnetic domain (or a magnetic domain wall) in the magnetic pillar during a read operation. That is, a shift current for shifting each magnetic domain arranged in the magnetic body pillar is outputted. The write control circuit 80 writes data to the magnetic columns in the memory cell array 10. The field line driver (FL driver) 60, when writing, causes a current to flow to the field lines under the control of the write control circuit 80, and generates an induced magnetic field corresponding to write data from the field lines.

Next, a circuit configuration of the memory cell array 10 will be described with reference to fig. 2. Fig. 2 is a diagram showing a circuit configuration of the memory cell array 10.

The magnetic pillar MML is electrically connected between the word line WL and the bit line BL. One end of the magnetic body column MML is connected to the word line WL through the magnetoresistive element (or resistance change element, variable resistance element) 11 and the selection element (selector) 12 in this order. That is, one end of the magnetic body column MML is connected to one end of the magnetoresistance effect element 11, and the other end of the magnetoresistance effect element 11 is connected to one end of the selection element 12. The other end of the selection element 12 is connected to a word line WL. Further, the other end of the magnetic body pillar MML is connected to the bit line BL.

The magnetoresistance effect element 11 includes, for example, a MTJ (Magnetic tunnel junction) element whose resistance changes according to the magnetization state. The selection element 12 includes, for example, an element that becomes a low resistance state when a voltage equal to or higher than a threshold voltage is applied and becomes a high resistance state when a voltage lower than the threshold voltage is applied. The selection element 12 may also be, for example, a two-terminal switching element. When the voltage applied between the terminals is equal to or lower than the threshold value, the switching element is in a high-resistance state, for example, an electrically non-conductive state. When the voltage applied between the two terminals is equal to or higher than the threshold value, the switching element is brought into a low resistance state, for example, an electrically conductive state. The switching element may have this function regardless of the polarity of the voltage. The switching element contains 1 or more chalcogen elements selected from the group consisting of Te, Se, and S. Alternatively, a chalcogenide compound which is a compound containing the chalcogen element may be contained. The switching element may further contain at least 1 or more element selected from the group consisting of B, Al, Ga, In, C, Si, Ge, Sn, As, P, and Sb.

For example, the plurality of magnetic material columns MML, the magnetoresistance effect element 11, and the selection element 12 arranged in the 1 st direction are connected to the same word line WL from the other end of the selection element 12. On the other hand, the plurality of magnetic material columns MML arranged in the 2 nd direction intersecting the 1 st direction, the magnetoresistance effect element 11, and the selection element 12 are connected to the same bit line BL from the other end of the magnetic material column MML.

Fig. 3 is a perspective view showing an example of the structure of the memory cell array 10. In fig. 3, two directions orthogonal to each other are defined as an X direction and a Y direction, and a direction orthogonal to these X direction and Y direction (XY plane) and extending the magnetic material column MML is defined as a Z direction.

A plurality of bit lines BL extending in the Y direction are arranged in the X direction. On the bit line BL, the magnetic body column MML, the magnetoresistance effect element 11, and the selection element 12 are arranged in the Z direction. The magnetoresistive element 11 is formed of, for example, an MTJ element. The MTJ element includes a magnetic layer 11R, a nonmagnetic layer 11N, and a magnetic layer 11S. Details of the MTJ element will be described later.

If the constitution of the memory cell array 10 is described in detail, the magnetic body pillar MML is provided on the bit line BL. The magnetic layer 11S is provided on the magnetic body pillar MML. The magnetic layer 11S extends in the Y direction by a certain distance, and the nonmagnetic layer 11N and the magnetic layer 11R are provided in this order on the extended magnetic layer 11S. On the magnetic layer 11R, a word line WL is provided via the selection element 12.

The magnetic material columns MML, the magnetoresistive elements 11, and the selection elements 12 arranged in the Z direction are arranged in a matrix in the X and Y directions. Word lines WL are provided on the selection elements 12 arranged in the X direction. Further, field lines (write lines) FL are provided on the magnetic layer 11S. The field lines FL are arranged in a zigzag manner in the X direction so as to pass between the magnetoresistive elements 11 adjacent in the X direction and the Y direction.

The magnetoresistive element (MTJ element) 11 will be described in detail below. The magnetoresistance effect element 11 includes a magnetic layer 11R, a nonmagnetic layer 11N, and a magnetic layer 11S. A nonmagnetic layer 11N is disposed between the magnetic layer 11R and the magnetic layer 11S. The magnetic layer 11R functions as a reference layer, and the magnetic layer 11S functions as a memory layer. The nonmagnetic layer 11N functions as a tunnel barrier. Further, the MTJ element may also include other layers.

The magnetic layer (storage layer) 11S is magnetized in a direction along a certain axis. For example, the magnetization of the magnetic layer 11S is stabilized in a direction perpendicular to the interfaces of the layers 11S, 11R, and 11N. The magnetization direction of the magnetic layer 11S can be inverted according to the magnetization direction of the magnetic region that the magnetic pillar MML has.

The magnetic layer (reference layer) 11R has a magnetization with a fixed or constant direction, for example, a coercive force larger than that of the magnetic layer (storage layer) 11S. The "fixed" or "unchanged" magnetization direction of the magnetic layer 11R means that the magnetization direction of the magnetic layer 11R is not inverted according to the magnetization direction of the magnetic region of the magnetic body column MML that inverts the magnetization of the magnetic layer (storage layer) 11S.

The group of the magnetic layer 11R, the nonmagnetic layer 11N, and the magnetic layer 11S exhibits the magnetoresistance effect. Specifically, if the magnetization directions of the magnetic layer 11S and the magnetic layer 11R are parallel and antiparallel, the MTJ element shows minimum and maximum resistance values, respectively. The magnetoresistance effect element (MTJ element) 11 is capable of obtaining a low resistance state when the relative relationship of the magnetization directions of the magnetic layer (storage layer) 11S and the magnetic layer (reference layer) 11R is parallel, and a high resistance state when antiparallel.

Next, the structure of the magnetic material column MML and the information storage method will be described with reference to fig. 4. Fig. 4 shows a cross-sectional structure of the 1 magnetic column MML shown in fig. 3 taken along the line a-a', an example of the magnetic domain (or magnetization state) of the magnetic column MML, and an information storage method using the magnetic domain.

The magnetic body column MML included in the magnetic memory is formed of a linear ferromagnetic body extending in the Z direction as shown in fig. 3, for example. The linear ferromagnetic member may be, for example, a cylindrical shape (for example, a cylindrical shape) having a hollow central portion as shown in fig. 4, or may be a shape having no hollow central portion. The ferromagnetic body has a plurality of magnetic regions along the Z direction. For example, the magnetic material column MML has magnetic regions M1, M2, and M3 … along the Z direction in the cross section of the cylindrical magnetic thin film.

Each magnetic region can maintain magnetization (or a magnetization state) in one direction or in a direction opposite to the one direction. As shown in fig. 4, each magnetic domain has a magnetization direction formed in the order of N-pole and S-pole from the outside of the cylinder, and conversely, a magnetization direction formed in the order of S-pole and N-pole from the outside of the cylinder. The boundary between magnetic regions where the magnetization directions are different from each other is called a magnetic domain wall. The magnetization direction of each magnetic domain may be a perpendicular direction (perpendicular magnetization film) to the Z direction in which the magnetic pillars MML extend, or may be a Z direction (in-plane magnetization film) in which the magnetic pillars MML extend.

In the case where the magnetization directions of two magnetic regions adjacent in the Z direction are the same, 2 nd data is stored. On the other hand, when the magnetization directions of two adjacent magnetic regions are different, 1 st data different from the 2 nd data is stored. For example, since the magnetization directions of the magnetic regions M1 and M2 are the same, "0" is stored. On the other hand, since the magnetization directions of the magnetic region M2 and the magnetic region M3 are different, a "1" is stored. In addition, when the magnetization directions are the same as between the magnetic region M1 and the magnetic region M2, no domain wall exists between the magnetic region M1 and the magnetic region M2.

Next, the write and read operations in the magnetic memory will be described. In reading and writing data, a magnetic domain to be read or written is shifted to a position of a mechanism for reading or writing (hereinafter, referred to as a read position or a write position). That is, the domain wall in the magnetic domain section is shifted so that the target magnetic region to be read or written moves to the read position or the write position. The displacement of the magnetic domain wall is performed, for example, by flowing a current (displacement current) to the magnetic body pillar MML.

Fig. 5A to 5R conceptually show the order of writing and reading to and from the magnetic material column MML.

First, the writing order will be described. In writing, "0" is written to the 1 st magnetic compartment of the magnetic body column MML if "0" is written by the writing unit as shown in fig. 5B from the state before writing shown in fig. 5A. Next, as shown in fig. 5C, if "1" is written by the writing unit, then "0" of the 1 st magnetic section of the magnetic body column MML is shifted to the 2 nd magnetic section, and "1" is written to the 1 st magnetic section. Further, as shown in fig. 5D, if "0" is written by the writing unit, "0" of the 2 nd magnetic segment of the magnetic body column MML is shifted to the 3 rd magnetic segment, "1" of the 1 st magnetic segment is shifted to the 2 nd magnetic segment, and "0" is written to the 1 st magnetic segment.

In the subsequent writing, similarly as shown in fig. 5E to 5I, the previously written data is shifted in a direction away from the writing position, and the data is written into the 1 st magnetic sector.

Next, the order of reading will be described. Fig. 5J to 5R are schematic diagrams of readout of the magnetic material column MML. In reading, as shown in fig. 5J, a read current is caused to flow to the magnetic body column MML, and "1" stored in the 1 st magnetic segment of the magnetic body column MML is read by the read unit.

Next, as shown in fig. 5J, a shift current is caused to flow to the magnetic body column MML, and the magnetic region in the magnetic body column MML is shifted in a direction approaching the read position. Thus, for example, "0" existing in the 2 nd magnetic segment before reading is shifted to the 1 st magnetic segment, and "1" existing in the 3 rd magnetic segment is shifted to the 2 nd magnetic segment. Next, as shown in fig. 5K, a read current is caused to flow to the magnetic material column MML, and "0" stored in the 1 st magnetic segment of the magnetic material column MML is read by the read unit.

Next, as shown in fig. 5K, a shift current is caused to flow to the magnetic body column MML, and the magnetic domain in the magnetic body column MML is shifted in a direction approaching the read position. Thus, for example, in the readout shown in fig. 5K, "1" existing in the 2 nd magnetic segment shifts to the 1 st magnetic segment, and "0" existing in the 3 rd magnetic segment shifts to the 2 nd magnetic segment. Next, as shown in fig. 5L, a read current is caused to flow to the magnetic material column MML, and "1" stored in the 1 st magnetic section of the magnetic material column MML is read by the read unit.

In the subsequent readout, similarly as shown in fig. 5M to 5R, the data stored in the 1 st magnetic domain is read by shifting each magnetic domain (or each domain wall) in the magnetic pillar MML in a direction close to the readout position.

Next, an outline of the write operation in the magnetic memory 1 will be described with reference to fig. 6A to 6E. Fig. 6A to 6E are diagrams showing a write operation in the magnetic memory 1, and schematically show the magnetic material columns MML.

The positional relationship between the field lines FL and the writing position WP is set so that the magnetic domain at the writing position WP has a desired magnetization direction by an induced magnetic field generated when a current flows to the field lines FL.

In the initial state shown in fig. 6A, as preparation for writing data, a specified magnetization direction is written as an initial magnetization direction to the magnetic body column MML (Pre Write). The write control circuit 80, as shown by a broken line in fig. 6A, for example, causes a current to flow in the field line FL in a direction from the front side toward the back side of the sheet, and writes the magnetization direction "←" in the magnetic domain M5 at the write position WP.

As shown in FIG. 6B, if the shift control circuit 50 causes a shift current to flow into the magnetic body column MML, the magnetic region M5 in the magnetic body column MML is shifted below the write position WP, thereby setting the magnetic region M4 at the write position WP. The write control circuit 80 receives data "0" and does not cause a current to flow to the field line FL according to the data "0". Thus, in sector M4 at the write position WP, the magnetization direction of "←" transferred from sector M5 is written. That is, a magnetic domain wall is not formed between the magnetic region M4 and the magnetic region M5, and data "0" is written (0 (Write).

As shown in FIG. 6C, if the shift control circuit 50 causes a shift current to flow into the magnetic body column MML, the magnetic region M4 in the magnetic body column MML is shifted below the write position WP, and the magnetic region M5 is further shifted downward, thereby setting the magnetic region M3 at the write position WP. The write control circuit 80 receives the data "1", and based on the data "1", as shown by a broken line in fig. 6C, causes a current to flow to the field line FL in a direction from the depth side toward the front side of the paper surface, and writes a magnetization direction "→" to the magnetic region M3 at the write position WP. Thus, a magnetization direction different from that of the magnetic domain M4 is written in the magnetic domain M3 at the writing position WP. That is, a magnetic domain wall is formed between the magnetic region M3 and the magnetic region M4, thereby writing data "1" (Write 1(1 Write)).

As shown in FIG. 6D, if the shift control circuit 50 causes a shift current to flow into the magnetic body column MML, the magnetic region M3 in the magnetic body column MML is shifted below the write position WP, and the magnetic regions M4, M5 are respectively further shifted downward, thereby setting the magnetic region M2 at the write position WP. The write control circuit 80 receives data "0", and according to the data "0", does not cause a current to flow to the field line FL. Thus, in the magnetic domain M2 at the writing position WP, the magnetization direction "→" transferred from the magnetic domain M3 is written. That is, no magnetic domain wall is formed between the magnetic region M2 and the magnetic region M3, and data "0" is written (0 is written).

As shown in FIG. 6E, if the shift control circuit 50 causes a shift current to flow into the magnetic body column MML, the magnetic region M2 in the magnetic body column MML is shifted below the write position WP, and the magnetic regions M3 to M5 are respectively further shifted downward, thereby setting the magnetic region M1 at the write position WP. The write control circuit 80 receives data "1", and according to the data "1", as shown by a broken line in fig. 6E, causes a current to flow to the field line FL in a direction from the front side toward the depth side of the paper, and writes the magnetization direction of "←" to the sector M1 at the write position WP. Thus, a magnetization direction different from that of the magnetic domain M2 is written in the magnetic domain M1 at the writing position WP. That is, a magnetic domain wall is formed between the magnetic region M1 and the magnetic region M2, thereby writing data "1" (write 1).

Next, a circuit related to the write operation will be described with reference to fig. 7. Fig. 7 is a diagram showing a circuit for a write operation.

The shift control circuit 50 is disposed on one end side of the magnetic body column MML. The shift control circuit 50 is disposed on the opposite side of the magnetic column MML with an n-channel MOS transistor (hereinafter referred to as nMOS transistor) NT13, a multiplexer 42, and a field line FL interposed therebetween.

The nMOS transistor NT13 has a gate electrically connected to the shift control circuit 50, a source electrically connected to the shift reference potential Vs, and a drain electrically connected to the multiplexer 42. The shift reference potential Vs is a potential higher than the ground potential. The shift control circuit 50 generates and outputs a shift signal SFT. The nMOS transistor NT13 is turned on when the shift signal SFT of an active level is received through the gate, thereby enabling a shift current to flow to the magnetic body column MML. The multiplexer 42 can select any one of the shift circuit for writing (nMOS transistor NT13) and the shift circuit for reading (see fig. 11) and electrically connect to the magnetic body pillar MML. In the write operation, the multiplexer 42 can select a shift circuit (nMOS transistor NT13) for writing and electrically connect to the magnetic pillar MML.

The field line FL passes near one end of the magnetic body column MML. The field line FL passes near one end of the magnetic body cylinder MML at a position eccentric from the central axis of the magnetic body cylinder MML. Thus, when a current (write current) in a desired direction is caused to flow to the field line FL, the vicinity of one end of the magnetic body column MML can be magnetized in the desired magnetization direction. For example, when a current in a desired direction is caused to flow to the field line FL, a part of the portion near one end of the magnetic body column MML in the circumferential direction is magnetized, but the magnetization direction is transmitted in the circumferential direction, so that the magnetization directions can be distributed radially when viewed in cross section (see fig. 4).

The FL driver 60 includes a plurality of inverters INVa, INVb. A plurality of inverters INVa, INVb are arranged across field line FL.

The inverter INVa includes an nMOS transistor NT11 and a p-channel MOS transistor (hereinafter, referred to as a pMOS transistor) PT 11. nMOS transistor NT11 and pMOS transistor PT11 are connected in reverse between the ground potential and write reference potential Vw. The writing reference potential Vw is a potential higher than the ground potential and is a potential different from the shift reference potential Vs. The drain of nMOS transistor NT11 and the drain of pMOS transistor PT11 are connected to one end FLa of field line FL in common. A gate of nMOS transistor NT11 and a gate of pMOS transistor PT11 are connected in common to write control circuit 80. Upon receiving the control signal WTAn of the active level, the inverter INVa turns off the nMOS transistor NT11 and turns on the pMOS transistor PT11, thereby being able to pull up the potential of the one end FLa of the field line FL to the write reference potential Vw side. The control signal WTAn can be set to an active low control signal (n indicates active low). At this time, the control signal WTBn is at an inactive level (H level), and the inverter INVb pulls down the potential of the other end FLb of the field line FL to the ground potential. Thereby, a current (write current) can be caused to flow to the field line FL in a direction from the one end FLa toward the other end FLb.

Inverter INVb includes nMOS transistor NT12 and pMOS transistor PT 12. nMOS transistor NT12 and pMOS transistor PT12 are connected in reverse between the ground potential and write reference potential Vw. The drain of nMOS transistor NT12 and the drain of pMOS transistor PT12 are connected to the other end FLb of field line FL in common. A gate of nMOS transistor NT12 and a gate of pMOS transistor PT12 are connected in common to write control circuit 80. When receiving the active-level control signal WTBn, the inverter INVb turns off the nMOS transistor NT12 and turns on the pMOS transistor PT12, thereby pulling up the potential of the other end FLb of the field line FL to the write reference potential Vw side. The control signal WTBn may be set to an active low control signal (n indicates active low). At this time, the control signal WTAn is at an inactive level (H level), and the inverter INVa pulls down the potential of one end FLa of the field line FL to the ground potential. Thereby, a current (write current) can be caused to flow to the field line FL in a direction from the other end FLb toward the one end FLa.

Next, a writing method will be described with reference to fig. 8. Fig. 8 is a flowchart showing a writing method.

When the magnetic memory 1 selects the magnetic material column MML to which data is to be written among the plurality of magnetic material columns MML in the memory cell array 10, it is determined whether data is written into the selected magnetic material column MML for the first time (S1). For example, the magnetic memory 1 has management information for managing the write state of data for each of the plurality of magnetic columns MML in the memory cell array 10, and by referring to the management information, it is possible to determine whether or not the data is written to the selected magnetic column MML for the first time.

When the data is written into the selected magnetic columns MML for the first time (Yes in S1), the magnetic memory 1 sets the control signal WTAn or the control signal WTBn to the active level as preparation for writing data (prewrite) and writes the magnetic columns MML with the specified magnetization direction as the initial magnetization direction (S2). The magnetic memory 1 causes a shift current to flow into the magnetic body pillars MML (S3). Thereby, the magnetic area of the writing position within the magnetic body column MML is shifted to below the writing position, and a new magnetic area is set at the writing position. Next, the magnetic memory 1 determines which value the data to be written to the magnetic columns MML has (S4).

On the other hand, when the data is not written to the selected magnetic pillars MML for the first time (No in S1), the magnetic memory 1 does not perform S2 and S3, but determines which value the data to be written to the magnetic pillars MML is (S4).

The magnetic memory 1 returns the process to S3 without performing the write line control operation when the data value is "0" (S10), and performs the write line control operation when the data value is "1" (S10). Specifically, the magnetic memory 1 performs the processing from S5 to S7 in fig. 10.

The magnetic memory 1 determines what the control signal used in the control of the last write line is (S5).

When the control signal WTAn of the previous time is WTAn (WTAn in S5), the magnetic memory 1 sets the control signal WTBn to the active level and writes "1" to the magnetic body column MML (S6) so that the direction of magnetization written to the magnetic body column MML becomes opposite to the previous time.

On the other hand, when the previous control signal is WTBn (WTBn in S5), the magnetic memory 1 sets the control signal WTAn to the active level and writes "1" to the magnetic body column MML (S7) so that the direction of magnetization written to the magnetic body column MML becomes opposite to the previous time.

The magnetic memory 1 determines whether or not all the data to be written has been written to the magnetic columns MML (S8). For example, the magnetic memory 1 refers to the management information, and determines that all data to be written has been written in the magnetic columns MML when the number of data written in the magnetic columns MML reaches the upper limit of the number of data that can be written. The magnetic memory 1 returns the process to S3 when all the data to be written is not written in the magnetic column MML (no in S8), and ends the process when all the data to be written is written in the magnetic column MML (yes in S8).

Next, the details of the write operation will be described with reference to fig. 9. Fig. 9 is a waveform diagram showing a write operation.

At time t1, the write control circuit 80 maintains the control signals WTAn and WTBn at inactive levels (e.g., H level). The shift control circuit 50 maintains the shift control signal SFT at an inactive level (e.g., L level).

At time t2, when receiving an instruction to prepare for writing data (Pre Write) from the controller 70, the Write control circuit 80 switches the control signal WTAn from the inactive level to the active level (e.g., L level) in accordance with the instruction. At this time, the write control circuit 80 maintains the control signal WTBn at an inactive level (e.g., H level). This enables a current (write current) to flow in the field line FL in a direction from one end FLa toward the other end FLb, and for example, enables the magnetization direction of "←" to be written in the magnetic domain M5 (see fig. 6A) at the write position WP.

At time t3, the write control circuit 80 transitions the control signal WTAn from an active level to an inactive level.

At time t4, the shift control circuit 50 makes the shift control signal SFT transition from the inactive level to the active level (e.g., H level). Thus, a shift current is caused to flow to the magnetic body column MML, and for example, the magnetic region M5 in the magnetic body column MML is shifted to a position below the writing position WP, whereby the magnetic region M4 is set at the writing position WP (see fig. 6B).

At time t5, the shift control circuit 50 switches the shift control signal SFT from the active level to the inactive level.

At time t6, the write control circuit 80 maintains the control signals WTAn and WTBn at inactive levels (e.g., H level) when receiving data "0". Thus, since the write current is not applied to the field line FL, a magnetic domain wall is not formed between the magnetic domain M4 and the magnetic domain M5, and data "0" is written (see fig. 6B).

At time t7, the shift control circuit 50 switches the shift control signal SFT from the inactive level to the active level. Thereby, a shift current is caused to flow to the magnetic body column MML, and for example, the magnetic region M4 in the magnetic body column MML is shifted to below the writing position WP, and the magnetic region M5 is further shifted downward, whereby the magnetic region M3 is set at the writing position WP (see fig. 6C).

At time t8, the shift control circuit 50 switches the shift control signal SFT from the active level to the inactive level.

At time t9, when the write control circuit 80 receives data "1", it determines that the control signal WTBn should be set to the active level, corresponding to the case where the control signal WTAn set to the active level at the previous time (time t2 to t3) was WTAn.

At time t10, the write control circuit 80 transitions the control signal WTBn from the inactive level to the active level. At this time, the write control circuit 80 maintains the control signal WTAn at the inactive level. As a result, a current (write current) can be caused to flow to the field line FL in a direction from the other end FLb toward the one end FLa, and a magnetic domain wall can be formed between the magnetic domain M3 and the magnetic domain M4, for example, to write data "1" (see fig. 6C).

At time t11, the write control circuit 80 transitions the control signal WTBn from the active level to the inactive level.

At time t12, the shift control circuit 50 switches the shift control signal SFT from the inactive level to the active level. Thereby, the magnetic domain M3 in the magnetic column MML is displaced below the writing position WP, and the magnetic domains M4 and M5 are displaced further downward, respectively, whereby the magnetic domain M2 is set at the writing position WP (see fig. 6D).

At time t13, the shift control circuit 50 switches the shift control signal SFT from the active level to the inactive level.

At time t14, the write control circuit 80 maintains the control signals WTAn and WTBn at inactive levels when receiving data "0". Thus, since the write current is not applied to the field line FL, a magnetic domain wall is not formed between the magnetic domain M2 and the magnetic domain M3, and data "0" is written (see fig. 6D).

At time t15, the shift control circuit 50 switches the shift control signal SFT from the inactive level to the active level. Thus, a shift current is caused to flow to the magnetic column MML, and for example, the magnetic region M2 in the magnetic column MML is shifted to a position below the writing position WP, and the magnetic regions M3 to M5 are further shifted downward, respectively, whereby the magnetic region M1 is set at the writing position WP (see fig. 6E).

At time t16, the shift control circuit 50 switches the shift control signal SFT from the active level to the inactive level.

At time t17, when the write control circuit 80 receives data "1", it determines that the control signal WTAn should be set to the active level, corresponding to the case where the control signal that was set to the active level last (time t10 to t11) was WTBn.

At time t18, the write control circuit 80 transitions the control signal WTAn from the inactive level to the active level. At this time, the write control circuit 80 maintains the control signal WTBn at the inactive level. As a result, a current (write current) can be caused to flow in the field line FL in a direction from the one end FLa to the other end FLb, and a magnetic domain wall can be formed between the magnetic domain M1 and the magnetic domain M2, for example, to write data "1" (see fig. 6E).

At time t19, the write control circuit 80 transitions the control signal WTAn from an active level to an inactive level.

At time t20, the shift control circuit 50 switches the shift control signal SFT from the inactive level to the active level. Thereby, the magnetic domain M1 in the magnetic column MML is displaced below the writing position WP, and the magnetic domains M2 to M5 are further displaced below, respectively, whereby the magnetic domain M0 (not shown) is set at the writing position WP.

At time t21, the shift control circuit 50 switches the shift control signal SFT from the active level to the inactive level.

Next, an outline of a reading method in the magnetic memory will be described with reference to fig. 10A to 10D. Fig. 10A to 10D are diagrams illustrating a reading method in the magnetic memory, and schematically illustrate the magnetoresistive element (for example, MTJ element) 11 and the magnetic body pillar MML.

The positional relationship between the magnetic layer 11S of the magnetoresistive element 11 and the read position RP is set so that the magnetic layer 11S has the same magnetization direction as the magnetic region at the read position RP by magnetic induction (or an induced magnetic field) from the magnetic region existing at the read position RP to the magnetic layer 11S of the magnetoresistive element 11.

In the initial state shown in fig. 10A, the magnetic domain M1 is disposed at the reading position RP, and the magnetic domains M2, M3, M4, and M5 are disposed in this order in the direction away from the reading position RP. At this time, the magnetic layer 11S maintains the same magnetization direction as the magnetic domain M1 by magnetic induction from the magnetic domain M1 disposed at the read position RP. Thereby, the magnetic layer 11S of the magnetoresistance effect element 11 has a magnetization direction parallel to (in the same direction as) the magnetic layer 11R. Thereby, the resistance of the magnetoresistance effect element 11 becomes low, and the read circuit 40 senses that the magnetoresistance effect element 11 is in the low resistance state.

Next, as shown in fig. 10B, the magnetic region within the magnetic body column MML is displaced in the direction of the readout position RP, and the magnetic region M2 is set at the readout position RP. The magnetic layer 11S maintains the same magnetization direction as the magnetic domain M2 by magnetic induction from the magnetic domain M2 disposed at the reading position RP. Thereby, the magnetic layer 11S has a magnetization direction antiparallel to the magnetic layer 11R. Thus, as in the case of fig. 10A, the resistance of the magnetoresistance effect element 11 becomes high, and the read circuit 40 senses that the magnetoresistance effect element 11 is in the high resistance state.

As described above, in the case where the 1 st sensing shown in fig. 10A and the 2 nd sensing shown in fig. 10B are different resistance states, the readout circuit 40 outputs, for example, "1".

That is, "1" is output as data stored in the magnetic regions M1 and M2. Note that, although the case where the 1 st sensing is in the low resistance state and the 2 nd sensing is in the high resistance state is described here, the readout circuit 40 outputs "0" also in the case where the 1 st sensing is in the high resistance state and the 2 nd sensing is in the low resistance state.

Next, as shown in fig. 10C, the magnetic region within the magnetic body column MML is displaced in the direction of the readout position RP, and the magnetic region M3 is set at the readout position RP. The magnetic layer 11S maintains the same magnetization direction as the magnetic domain M3 by magnetic induction from the magnetic domain M3 disposed at the reading position RP. Thus, the magnetic layer 11S has a magnetization direction antiparallel (in the opposite direction) to the magnetic layer 11R. Thereby, the resistance of the magnetoresistance effect element 11 becomes high, and the read circuit 40 senses that the magnetoresistance effect element 11 is in the high resistance state.

As described above, in the case where both the 2 nd sensing shown in fig. 10B and the 3 rd sensing shown in fig. 10C are in the high resistance state, the readout circuit 40 outputs, for example, "0". That is, as the data stored in the magnetic regions M2 and M3, "0" is output. Note that, although the case where both the 1 st and 2 nd sensing are in the high resistance state is described here, the readout circuit 40 also outputs "0" when both the 1 st and 2 nd sensing are in the low resistance state.

Next, as shown in fig. 10D, the magnetic region in the magnetic body column MML is displaced in the direction of the readout position RP, and the magnetic region M4 is set at the readout position RP. The magnetic layer 11S maintains the same magnetization direction as the magnetic domain M4 by magnetic induction from the magnetic domain M4 disposed at the reading position RP. Thereby, the magnetic layer 11S has a magnetization direction parallel to the magnetic layer 11R.

Thereby, the resistance of the magnetoresistance effect element 11 becomes low, and the read circuit 40 senses that the magnetoresistance effect element 11 is in the low resistance state.

As described above, in the case where the 3 rd sensing shown in fig. 10C and the 4 th sensing shown in fig. 10D are different resistance states, the readout circuit 40 outputs, for example, "1".

That is, "1" is output as data stored in the magnetic regions M3 and M4.

In this readout method, when the resistance state sensed last time is the same as the resistance state sensed at present, it is determined as the 2 nd data (for example, "0"). On the other hand, in the case where the resistance state sensed last time is different from the resistance state sensed at present, it is determined as the 1 st data (for example, "1"). That is, in the case where both of the low resistance state and the high resistance state are sensed in the two consecutive senses, the 2 nd data is determined, and in the case where different resistance states are sensed, the 1 st data is determined. In other words, the resistance of the magnetoresistive element 11 with respect to the two magnetic regions in contact with each other in the magnetic material column MML is sensed, and when the resistance of the magnetoresistive element 11 does not change, the data 2 is determined, and when the resistance of the magnetoresistive element 11 changes, the data 1 is determined.

Fig. 11 is a circuit diagram showing a configuration of a circuit related to a read operation. The readout circuit 40 includes a capacitor C1, a sense amplifier 46, an equalizing circuit 41, a multiplexer (Mux)42, p-channel MOS transistors (hereinafter, referred to as pMOS transistors) PT1 and PT2, and n-channel MOS transistors (hereinafter, referred to as nMOS transistors) NT1 and NT 2.

The circuit connection of the readout circuit shown in fig. 11 will be described below. The 1 st input terminal of the sense amplifier 46 is connected to the 1 st electrode of the capacitor C1, the gate of the pMOS transistor PT1, and the 1 st terminal of the equalizing circuit 41. The 2 nd input terminal of the sense amplifier 46 is connected to the drain of the pMOS transistor PT1, the drain of the nMOS transistor NT1, and the 2 nd terminal of the equalizing circuit 41. A source of nMOS transistor NT1 is connected to a drain of pMOS transistor PT2 and an input terminal of multiplexer 42 via nMOS transistor NT 2. A readout reference potential VR is supplied to the 2 nd electrode of the capacitor C1 and the source of the pMOS transistor PT 1. The read reference potential VR is a potential higher than the ground potential. Further, the shift reference potential Vs is supplied to the source of the pMOS transistor PT 2. The shift reference potential Vs is a potential higher than the ground potential and is a potential different from the read reference potential VR.

A shift signal SFTn is input to the gate of the pMOS transistor PT 2. The clamp signal VCLMP is input to the gate of the nMOS transistor NT1, and the read enable signal RE is input to the gate of the nMOS transistor NT 2. The equalization signals EQ, EQn are input to the gates of the transistors of the equalization circuit 41. The output signal DOUT is output from the sense amplifier 46. In addition, "n" denoted in the symbol of the signal indicates an active low signal.

The output terminal of the multiplexer 42 is connected to the ground potential via the magnetoresistive element 11 and the magnetic body column MML.

In the read circuit 40, a circuit at a stage preceding the sense amplifier 46 functions as a preamplifier for sensing the resistance state of the magnetoresistive element 11. The preamplifier causes a state signal corresponding to the resistance state of the magnetoresistance effect element 11 to be stored in the capacitor C1.

Fig. 12 is a diagram showing a memory chip (semiconductor device) in which a plurality of magnetic memories 1 are arranged. Fig. 13 is a diagram showing a memory system on which a memory chip is mounted. The memory system is, for example, an SSD (Solid State Drive).

As shown in fig. 12, a plurality of magnetic memories 1 may be arranged in an array on the memory chip 100. A peripheral circuit and a pad 2 are provided on the memory chip 100. The peripheral circuit includes a circuit for controlling write and read operations of the magnetic memory 1, a power supply circuit for generating various power supplies to the magnetic memory 1, and the like. The pad includes an electrode or the like for connection with the outside.

As shown in fig. 13, for example, a plurality of memory chips 100 are stacked to form a multi-chip 200. Further, the multichip 200 is mounted on the memory system 400 together with the memory controller 300 that controls the multichip 200.

As described above, in the present embodiment, in the magnetic memory 1, a current is caused to flow to the write line so as to form a magnetic domain wall when data of the 1 st value is written, and a current is not caused to flow to the write line so as not to form a magnetic domain wall when data of the 2 nd value is written. This enables the write operation of the magnetic memory 1 to be performed with low power consumption. That is, the magnetic memory 1 can be made low in power consumption.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.