阅读说明：本技术 一种具有复合结构的双向esd防护器件 (Bidirectional ESD protection device with composite structure ) 是由 梁海莲 朱玲 顾晓峰 虞致国 姜岩峰 闫大为 于 2019-11-19 设计创作，主要内容包括：本发明公开了一种具有复合结构的双向ESD防护器件,属于集成电路的静电放电防护及抗浪涌领域。所述器件主要由一P型浅掺杂衬底、N型掺杂阱、第一P型中掺杂阱、第二P型中掺杂阱、第一P型重掺杂注入区、第一N型重掺杂注入区、第二P型重掺杂注入区、第二N型重掺杂注入区、第一多晶硅栅及其覆盖的第一薄栅氧化层、第三N型重掺杂注入区、第四N型重掺杂注入区、第二多晶硅栅及其覆盖的第二薄栅氧化层和第五N型重掺杂注入区构成。本发明通过版图设计和利用P型中掺杂阱,提高器件内部寄生NPN三极管的基区浓度,降低内部寄生NPN三极管放大倍数,削弱寄生SCR结构的正反馈程度,可提高器件的维持电压,增强ESD鲁棒性。(The invention discloses a bidirectional ESD protective device with a composite structure, and belongs to the field of electrostatic discharge protection and surge resistance of integrated circuits. The device mainly comprises a P-type shallow doped substrate, an N-type doped well, a first P-type middle doped well, a second P-type middle doped well, a first P-type heavily doped injection region, a first N-type heavily doped injection region, a second P-type heavily doped injection region, a second N-type heavily doped injection region, a first polysilicon gate and a first thin gate oxide layer, a third N-type heavily doped injection region, a fourth N-type heavily doped injection region, a second polysilicon gate and a second thin gate oxide layer and a fifth N-type heavily doped injection region which are covered by the second polysilicon gate. According to the invention, through layout design and utilization of the P-type middle doped well, the base region concentration of the parasitic NPN triode inside the device is improved, the amplification factor of the parasitic NPN triode inside the device is reduced, the positive feedback degree of the parasitic SCR structure is weakened, the maintaining voltage of the device can be improved, and the ESD robustness is enhanced.)

1. A bidirectional ESD protection device with a composite structure is characterized in that: the device mainly comprises a P-type shallow doped substrate, an N-type doped well, a first P-type middle doped well, a second P-type middle doped well, a first P-type heavily doped injection region, a first N-type heavily doped injection region, a second P-type heavily doped injection region, a second N-type heavily doped injection region, a first polysilicon gate and a first thin gate oxide layer, a third N-type heavily doped injection region, a fourth N-type heavily doped injection region, a second polysilicon gate and a second thin gate oxide layer and a fifth N-type heavily doped injection region which are covered by the second polysilicon gate;

an N-type doped well is arranged in the surface region of the P-type shallow doped substrate, the left side edge of the P-type shallow doped substrate is connected with the left side edge of the N-type doped well, and the right side edge of the P-type shallow doped substrate is connected with the right side edge of the first P-type middle doped well;

a first P-type middle doped well and a second P-type middle doped well are arranged in the surface region of the N-type doped well, the left side edge of the N-type doped well is connected with the left side edge of the first P-type middle doped well, a safety distance is arranged between the first P-type middle doped well and the second P-type middle doped well, and the right side edge of the N-type doped well is connected with the right side edge of the second P-type middle doped well;

along the length direction of the device, a first P-type heavily doped injection region spans a surface region between a first P-type middle doped well and an N-type doped well, a first N-type heavily doped injection region spans a surface region of an N-type doped well between the first P-type middle doped well and a second P-type middle doped well, a second P-type heavily doped injection region spans a surface region between the N-type doped well and the second P-type middle doped well, and safety distances are arranged between the first N-type heavily doped injection region and the first P-type heavily doped injection region and between the first N-type heavily doped injection region and the second P-type heavily doped injection region; the width of the first N type heavily doped injection region is equal to that of the device, and the widths of the first P type heavily doped injection region, the second P type heavily doped injection region and the second P type heavily doped injection region are equal to half of the width of the device;

a first MOS (metal oxide semiconductor) with the same length as the first P-type heavily doped injection region is arranged along the width direction of the first P-type heavily doped injection region, a safety interval is arranged between the first P-type heavily doped injection region and the first MOS, the first MOS consists of a second N-type heavily doped injection region, a first polysilicon gate, a first thin gate oxide layer covered by the first polysilicon gate and a third N-type heavily doped injection region, wherein the right side edge of the second N-type heavily doped injection region is connected with the left side edge of the first polysilicon gate and a first thin gate oxide layer covered by the first polysilicon gate, the right side edge of the first polysilicon gate and a first thin gate oxide layer covered by the first polysilicon gate is connected with the left side edge of the third N-type heavily doped injection region, and the right side edge of the first MOS is connected with the left side edge of the first N-type heavily doped injection region;

a second MOS with the same length as the second P-type heavily doped injection region is arranged along the width direction of the second P-type heavily doped injection region, a safety interval is arranged between the second P-type heavily doped injection region and the second MOS, the second MOS consists of a fourth N-type heavily doped injection region, a second polysilicon gate, a second thin gate oxide layer covered by the second polysilicon gate and a fifth N-type heavily doped injection region, wherein the right side edge of the fourth N-type heavily doped injection region is connected with the left side edge of the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate, the right side edge of the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate is connected with the left side edge of the fifth N-type heavily doped injection region, and the left side edge of the second MOS is connected with the right side edge of the first N-type heavily doped injection region;

the first P type heavily doped injection region is connected with a first metal 1, the second N type heavily doped injection region is connected with a second metal 1, the first polysilicon gate is connected with a third metal 1, the second P type heavily doped injection region is connected with a fourth metal 1, the second polysilicon gate is connected with a fifth metal 1, and the fifth N type heavily doped injection region is connected with a sixth metal 1;

the first metal 1, the second metal 1 and the third metal 1 are all connected with the first metal 2, and a first electrode is led out from the first metal 2;

the fourth metal 1, the fifth metal 1 and the sixth metal 1 are all connected with the second metal 2, and a second electrode is led out from the second metal 2.

2. A bi-directional ESD protection device with composite structure as claimed in claim 1, characterized in that: under the action of ESD stress, the first MOS (M1) is in an on state, the second MOS is in an off state, and an auxiliary trigger SCR path is formed by the first MOS, the second MOS and the first N-type heavily doped injection region so as to reduce the trigger voltage of the device and reduce the hysteresis amplitude of the device.

3. A bi-directional ESD protection device with composite structure as claimed in claim 1, characterized in that: a parasitic SCR consisting of a first P type heavily doped injection region, an N type doped well, a first N type heavily doped injection region, a second P type middle doped well and a third N type heavily doped injection region reduces the area of an emitter of an internal parasitic NPN triode through a new layout design, and meanwhile, the second P type middle doped well can improve the base region concentration of the internal parasitic NPN triode of the device, reduce the amplification factor of the internal parasitic NPN triode, weaken the positive feedback degree of the parasitic SCR structure, improve the maintaining voltage of the device and enhance the robustness of the device.

4. A bi-directional ESD protection device with composite structure as claimed in claim 1, characterized in that: a first unit formed by the first P type heavily doped injection region and the first MOS, a second unit formed by the second P type heavily doped injection region and the second MOS and the first N type heavily doped injection region can be stacked along the width direction of the device, so that the robustness of the device is enhanced.

5. A bi-directional ESD protection device with composite structure as claimed in claim 1, characterized in that: the lengths of the first polysilicon gate and the first thin gate oxide layer covered by the first polysilicon gate, the first N-type heavily doped injection region, the second polysilicon gate and the first thin gate oxide layer covered by the second polysilicon gate are adjusted, so that the wide power domain protection requirement of ESD/EOS can be met.

6. A bi-directional ESD protection device with composite structure as claimed in claim 1, characterized in that: the first unit and the second unit are completely symmetrical relative to the first N-type heavily doped injection region, and when a forward electrical stress and a backward electrical stress are applied between the first electrode and the second electrode of the device, the internal electrical characteristics of the interior of the device under the action of the forward electrical stress are the same as the internal electrical characteristics of the interior of the device under the action of the backward electrical stress, so that the device has the functions of bidirectional overvoltage protection, overcurrent protection or surge resistance.

7. A bidirectional ESD protection method is characterized in that a plurality of structures are combined together and optimized in layout design, and the unit area utilization rate of a device is improved; on one hand, the on-state NMOS and the off-state NMOS are connected in series to form an auxiliary trigger SCR path, so that the trigger voltage of the device is reduced, and the hysteresis amplitude of the device is reduced; on the other hand, the area of an emitter of the internal parasitic NPN triode is reduced by providing a layout design, the base region concentration of the internal parasitic NPN triode is improved by adding a P-type middle doped well in the device, the amplification factor of the internal parasitic NPN triode is reduced, the positive feedback degree of a parasitic SCR structure is weakened, the holding voltage of the device is improved, and the robustness of the device is enhanced.

8. The bi-directional ESD protection method according to claim 7, wherein the ESD protection device is mainly composed of a P-type lightly doped substrate, an N-type doped well, a first P-type middle doped well, a second P-type middle doped well, a first P-type heavily doped implantation region, a first N-type heavily doped implantation region, a second P-type heavily doped implantation region, a second N-type heavily doped implantation region, a first polysilicon gate and a first thin gate oxide layer, a third N-type heavily doped implantation region, a fourth N-type heavily doped implantation region, a second polysilicon gate and a second thin gate oxide layer and a fifth N-type heavily doped implantation region;

an N-type doped well is arranged in the surface region of the P-type shallow doped substrate, the left side edge of the P-type shallow doped substrate is connected with the left side edge of the N-type doped well, and the right side edge of the P-type shallow doped substrate is connected with the right side edge of the first P-type middle doped well;

a first P-type middle doped well and a second P-type middle doped well are arranged in the surface region of the N-type doped well, the left side edge of the N-type doped well is connected with the left side edge of the first P-type middle doped well, a safety distance is arranged between the first P-type middle doped well and the second P-type middle doped well, and the right side edge of the N-type doped well is connected with the right side edge of the second P-type middle doped well;

along the length direction of the device, a first P-type heavily doped injection region spans a surface region between a first P-type middle doped well and an N-type doped well, a first N-type heavily doped injection region spans a surface region of an N-type doped well between the first P-type middle doped well and a second P-type middle doped well, a second P-type heavily doped injection region spans a surface region between the N-type doped well and the second P-type middle doped well, and safety distances are arranged between the first N-type heavily doped injection region and the first P-type heavily doped injection region and between the first N-type heavily doped injection region and the second P-type heavily doped injection region; the width of the first N type heavily doped injection region is equal to that of the device, and the widths of the first P type heavily doped injection region, the second P type heavily doped injection region and the second P type heavily doped injection region are equal to half of the width of the device;

a first MOS (metal oxide semiconductor) with the same length as the first P-type heavily doped injection region is arranged along the width direction of the first P-type heavily doped injection region, a safety interval is arranged between the first P-type heavily doped injection region and the first MOS, the first MOS consists of a second N-type heavily doped injection region, a first polysilicon gate, a first thin gate oxide layer covered by the first polysilicon gate and a third N-type heavily doped injection region, wherein the right side edge of the second N-type heavily doped injection region is connected with the left side edge of the first polysilicon gate and a first thin gate oxide layer covered by the first polysilicon gate, the right side edge of the first polysilicon gate and a first thin gate oxide layer covered by the first polysilicon gate is connected with the left side edge of the third N-type heavily doped injection region, and the right side edge of the first MOS is connected with the left side edge of the first N-type heavily doped injection region;

a second MOS with the same length as the second P-type heavily doped injection region is arranged along the width direction of the second P-type heavily doped injection region, a safety interval is arranged between the second P-type heavily doped injection region and the second MOS, the second MOS consists of a fourth N-type heavily doped injection region, a second polysilicon gate, a second thin gate oxide layer covered by the second polysilicon gate and a fifth N-type heavily doped injection region, wherein the right side edge of the fourth N-type heavily doped injection region is connected with the left side edge of the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate, the right side edge of the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate is connected with the left side edge of the fifth N-type heavily doped injection region, and the left side edge of the second MOS is connected with the right side edge of the first N-type heavily doped injection region;

the first P type heavily doped injection region is connected with a first metal 1, the second N type heavily doped injection region is connected with a second metal 1, the first polysilicon gate is connected with a third metal 1, the second P type heavily doped injection region is connected with a fourth metal 1, the second polysilicon gate is connected with a fifth metal 1, and the fifth N type heavily doped injection region is connected with a sixth metal 1;

the first metal 1, the second metal 1 and the third metal 1 are all connected with the first metal 2, and a first electrode is led out from the first metal 2;

the fourth metal 1, the fifth metal 1 and the sixth metal 1 are all connected with the second metal 2, and a second electrode is led out from the second metal 2.

9. Use of the bidirectional ESD protection device with composite structure according to any of claims 1 to 6 in electrostatic discharge and surge protection.

10. An integrated circuit comprising a bi-directional ESD protection device with a composite structure according to any of claims 1 to 6.

Technical Field

The invention relates to a bidirectional ESD protective device with a composite structure, belonging to the field of electrostatic discharge protection and surge resistance of integrated circuits.

Background

The surge phenomenon of electronic products refers to the peak current or voltage which is generated by a circuit at the moment of power-on or in abnormal conditions and is far greater than the steady state, and is essentially a violent pulse generated in a very short time. Because the surge occurs for a very short time and the magnitude of the surge voltage or current is much larger than the steady-state voltage and current, the damage caused by the surge to devices, circuits and electronic products is not negligible. The source of the surge is many, and the electrostatic discharge is one of the main sources. The electrostatic discharge refers to charge transfer caused by the fact that objects with different electrostatic potentials are close to each other or directly contact with each other, and an instantaneously generated ESD current peak value can cause chip failure and damage of an electronic product. And electrostatic discharge (ESD) generally exists in the production, storage, transportation and use processes of electronic products, so that the yield of the electronic products is greatly influenced. Therefore, in order to improve the yield of electronic products and reduce the production cost, it is important to design the ESD protection for the electronic products.

In the research and application of anti-surge and ESD protection, a Silicon Controlled Rectifier (SCR) has become a mainstream device in the current ESD protection application due to the advantages of simple structure, strong robustness, few parasitic effects and the like. However, the SCR has the problems of too high trigger voltage, too low holding voltage, easy latch-up, etc., which results in the limitation of the SCR in the application of the actual ESD protection field.

Disclosure of Invention

[ problem ] to

The SCR trigger circuit aims at the problems that the traditional SCR trigger circuit is too high in voltage, too low in maintaining voltage, prone to latch-up risks and the like.

[ solution ]

The invention provides a protective device with ESD protective performance, which has a composite structure and is improved in layout design, wherein multiple structures are combined together, and the unit area utilization rate of the device is improved. On one hand, an auxiliary trigger SCR path is formed by connecting an on-state NMOS (N-Metal-Oxide-Semiconductor) and an off-state NMOS in series, so that the trigger voltage of the device is reduced, and the hysteresis amplitude of the device is reduced. On the other hand, the area of an emitter of the internal parasitic NPN triode is reduced through layout design, the base region concentration of the internal parasitic NPN triode in the device can be improved by adding the P-type middle doped trap in the device, the amplification factor of the internal parasitic NPN triode is reduced, the positive feedback degree of a parasitic SCR structure is weakened, the maintaining voltage of the device can be improved, and the robustness of the device is enhanced. The symmetrical composite structure helps the device to achieve a two-way protection function.

The protective device with the ESD protection performance mainly comprises a P-type shallow doped substrate, an N-type doped well, a first P-type middle doped well, a second P-type middle doped well, a first P-type heavily doped injection region, a first N-type heavily doped injection region, a second P-type heavily doped injection region, a second N-type heavily doped injection region, a first polysilicon gate and a first thin gate oxide layer, a third N-type heavily doped injection region, a fourth N-type heavily doped injection region, a second polysilicon gate and a second thin gate oxide layer and a fifth N-type heavily doped injection region which are covered by the second polysilicon gate;

an N-type doped well is arranged in the surface region of the P-type shallow doped substrate, the left side edge of the P-type shallow doped substrate is connected with the left side edge of the N-type doped well, and the right side edge of the P-type shallow doped substrate is connected with the right side edge of the first P-type middle doped well;

a first P-type middle doped well and a second P-type middle doped well are arranged in the surface region of the N-type doped well, the left side edge of the N-type doped well is connected with the left side edge of the first P-type middle doped well, a safety distance is arranged between the first P-type middle doped well and the second P-type middle doped well, and the right side edge of the N-type doped well is connected with the right side edge of the second P-type middle doped well;

along the length direction of the device, a first P-type heavily doped injection region spans a surface region between a first P-type middle doped well and an N-type doped well, a first N-type heavily doped injection region spans a surface region of an N-type doped well between the first P-type middle doped well and a second P-type middle doped well, a second P-type heavily doped injection region spans a surface region between the N-type doped well and the second P-type middle doped well, and safety distances are arranged between the first N-type heavily doped injection region and the first P-type heavily doped injection region and between the first N-type heavily doped injection region and the second P-type heavily doped injection region; the width of the first N type heavily doped injection region is equal to that of the device, and the widths of the first P type heavily doped injection region, the second P type heavily doped injection region and the second P type heavily doped injection region are equal to half of the width of the device;

a first MOS (metal oxide semiconductor) with the same length as the first P-type heavily doped injection region is arranged along the width direction of the first P-type heavily doped injection region, a safety interval is arranged between the first P-type heavily doped injection region and the first MOS, the first MOS consists of a second N-type heavily doped injection region, a first polysilicon gate, a first thin gate oxide layer covered by the first polysilicon gate and a third N-type heavily doped injection region, wherein the right side edge of the second N-type heavily doped injection region is connected with the left side edge of the first polysilicon gate and a first thin gate oxide layer covered by the first polysilicon gate, the right side edge of the first polysilicon gate and a first thin gate oxide layer covered by the first polysilicon gate is connected with the left side edge of the third N-type heavily doped injection region, and the right side edge of the first MOS is connected with the left side edge of the first N-type heavily doped injection region;

a second MOS with the same length as the second P-type heavily doped injection region is arranged along the width direction of the second P-type heavily doped injection region, a safety interval is arranged between the second P-type heavily doped injection region and the second MOS, the second MOS consists of a fourth N-type heavily doped injection region, a second polysilicon gate, a second thin gate oxide layer covered by the second polysilicon gate and a fifth N-type heavily doped injection region, wherein the right side edge of the fourth N-type heavily doped injection region is connected with the left side edge of the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate, the right side edge of the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate is connected with the left side edge of the fifth N-type heavily doped injection region, and the left side edge of the second MOS is connected with the right side edge of the first N-type heavily doped injection region;

the first P type heavily doped injection region is connected with a first metal 1, the second N type heavily doped injection region is connected with a second metal 1, the first polysilicon gate is connected with a third metal 1, the second P type heavily doped injection region is connected with a fourth metal 1, the second polysilicon gate is connected with a fifth metal 1, and the fifth N type heavily doped injection region is connected with a sixth metal 1;

the first metal 1, the second metal 1 and the third metal 1 are all connected with the first metal 2, and a first electrode is led out from the first metal 2;

the fourth metal 1, the fifth metal 1 and the sixth metal 1 are all connected with the second metal 2, and a second electrode is led out from the second metal 2.

The beneficial technical effects of the invention are as follows:

under the action of ESD stress, the first MOS is in an on state, the second MOS is in an off state, and the first MOS, the second MOS and the first N-type heavily doped injection region form an auxiliary trigger SCR path so as to reduce the trigger voltage of the device and reduce the hysteresis amplitude of the device.

The protection device with the ESD protection performance provided by the invention is a parasitic SCR consisting of a first P type heavily doped injection region, an N type doped well, a first N type heavily doped injection region, a second P type middle doped well and a third N type heavily doped injection region, and the area of an emitter of an internal parasitic NPN triode is reduced through a new layout design.

The protection device with the ESD protection performance provided by the invention has the advantages that the first unit formed by the first P type heavily doped injection region and the first MOS and the second unit formed by the second P type heavily doped injection region and the second MOS can be stacked along the width direction of the device so as to enhance the robustness of the device.

The protective device with the ESD protection performance provided by the invention can adjust the lengths of the first polysilicon gate and the first thin gate oxide layer, the first N-type heavily doped injection region, the second polysilicon gate and the first thin gate oxide layer covered by the second polysilicon gate, and can realize the wide power domain protection requirement of ESD/EOS.

In the protection device with the ESD protection performance, the first unit and the second unit are completely symmetrical about the first N-type heavily doped injection region, when forward and reverse electrical stress is applied between the first electrode and the second electrode of the device, the internal electrical characteristics under the action of the forward electrical stress in the device are the same as the internal electrical characteristics under the action of the reverse electrical stress, and the protection device has the functions of bidirectional overvoltage protection, overcurrent protection or surge resistance.

Drawings

FIG. 1 is a three-dimensional block diagram of a device of the present invention;

FIG. 2 is a diagram of the metal connections of the device of the present invention;

FIG. 3 is a different cross-sectional position of the device structure of the present invention;

FIG. 4 is a cross-sectional view of the device along direction AA';

fig. 5 is a cross-sectional view of the device along the BB' direction.

101: p-type lightly doped substrate, 102: n-type doped well, 103: first P-type doped well, 104: second P-type middle doped well, 105: first P-type heavily doped implant region, 106: first N-type heavily doped implant region, 107: second P-type heavily doped implant region, 108: second N-type heavily doped implant region, 109: first polysilicon gate, 110: first thin gate oxide covered by first polysilicon gate, 111: third heavily N-doped implant region, 112: fourth heavily doped N-type implant region, 113: second polysilicon gate, 114: first thin gate oxide covered by second polysilicon gate, 115: a fifth N-type heavily doped injection region;

201: first metal 1, 202: second metal 1, 203: third metal 1, 204: fourth metal 1, 205: fifth metal 1, 206: sixth metal 1, 207: seventh metal 1, 208: an eighth metal 1;

301: first electrode, 302: a second electrode. U1, U2, M1, M2 are internal cell modules.

Detailed Description