Integrated circuit memory and preparation method thereof
阅读说明:本技术 集成电路存储器及其制备方法 (Integrated circuit memory and preparation method thereof ) 是由 不公告发明人 于 2018-09-13 设计创作,主要内容包括:本发明提供了一种集成电路存储器及其制备方法,所述制备方法通过采用具有倾斜角的倾斜离子注入工艺,使得两个近邻的牺牲结构因具有不同的掺杂浓度而具有不同的刻蚀选择性,进而在掩膜材料层中形成深度不同的掩膜开口,以所述掩膜材料层为掩膜刻蚀半导体衬底,可以获得深度不同的凹槽,进而可以形成埋设深度的相邻的埋入式字线,由此通过相邻埋入式字线的底表面之间的高度差,可以约束和减轻相邻埋入式字线之间的耦合效应,提高器件效能及可靠度。(The invention provides an integrated circuit memory and a preparation method thereof, wherein the preparation method adopts an inclined ion implantation process with an inclined angle to ensure that two adjacent sacrificial structures have different etching selectivity due to different doping concentrations, so as to form mask openings with different depths in a mask material layer, and a semiconductor substrate is etched by taking the mask material layer as a mask, so that grooves with different depths can be obtained, and further adjacent embedded word lines with embedded depths can be formed, so that the coupling effect between the adjacent embedded word lines can be restrained and alleviated through the height difference between the bottom surfaces of the adjacent embedded word lines, and the device efficiency and the reliability are improved.)
1. A method of manufacturing an integrated circuit memory, comprising the steps of:
providing a semiconductor substrate, wherein a sacrificial layer is formed on the semiconductor substrate, and a plurality of auxiliary lines are formed on the sacrificial layer and extend along a first direction;
forming side walls on the side walls of the auxiliary lines, wherein the side walls facing each other between the adjacent auxiliary lines define first spaced openings;
removing the auxiliary lines, and etching the sacrificial layer by using the side walls as masks to form a plurality of sacrificial structures extending along the first direction, wherein a second interval opening is formed between two side walls corresponding to the same auxiliary line side wall, and the opening size of the second interval opening is larger than that of the first interval opening;
doping the sacrificial structures by adopting an inclined ion implantation process so as to enable the adjacent sacrificial structures to have different doping concentrations;
filling a mask material layer between the adjacent sacrificial structures and exposing the top surfaces of the sacrificial structures;
etching the sacrificial structures to form mask openings extending into the mask material layer, wherein the depths of the mask openings formed by the adjacent sacrificial structures are different;
etching the residual sacrificial structure by taking the mask material layer as a mask and extending and etching the residual sacrificial structure into the semiconductor substrate to form grooves corresponding to the mask openings, wherein the depths of the adjacent grooves are different; and the number of the first and second groups,
and forming embedded word lines in the grooves, wherein the embedded word lines are asymmetrically arranged in the adjacent grooves.
2. The method of claim 1, wherein the lateral dimension of the sidewall is 12nm to 18nm, the dimension of the first spaced opening is 90nm to 100nm, and the dimension of the second spaced opening is 20nm to 30 nm.
3. The method of claim 1, wherein the sacrificial structure is doped using a single tilted ion implantation process, and an angle between an implantation direction of the single tilted ion implantation process and a surface of the semiconductor substrate is 5 ° to 85 ° or 95 ° to 175 °.
4. The method of claim 3, wherein the implanted ions of the tilted ion implantation process comprise at least one of N-type ions, P-type ions, carbon ions, fluorine ions, nitrogen ions, hydrogen ions, oxygen ions, and metal ions.
5. The method of claim 1, wherein the difference in depth between adjacent recesses is between 5nm and 200 nm.
6. The method of claim 1, wherein the step of forming the buried word line comprises:
forming a gate dielectric layer on the surface of the groove;
filling a conductive layer in the groove, wherein the top surface of the conductive layer is lower than the surface of the semiconductor substrate, and the depth difference between the conductive layers in the adjacent grooves is 80 nm-170 nm; and
and filling a grid isolation layer in the groove, wherein the grid isolation layer is laminated on the conductive layer and fills the groove.
7. An integrated circuit memory, comprising:
the semiconductor device comprises a semiconductor substrate, wherein grooves with different depths are formed in the semiconductor substrate; and the number of the first and second groups,
and the embedded word lines are embedded in the grooves, and the embedded word lines are asymmetrically arranged in the adjacent grooves.
8. The integrated circuit memory of claim 7 wherein the difference in depth between adjacent said recesses is between 5nm and 200 nm.
9. The integrated circuit memory of claim 7 wherein said recesses have a lateral opening dimension of 12nm to 18nm and a spacing between adjacent ones of said recesses of 20nm to 30 nm.
10. The integrated circuit memory of claim 7, wherein the buried word lines include gate dielectric layers covering sidewalls and bottom surfaces of the recesses, and conductive layers and gate isolation layers sequentially stacked in the recesses having the gate dielectric layers from bottom to top, and a depth difference between the conductive layers of adjacent buried word lines is 80nm to 170 nm.
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to an integrated circuit memory and a preparation method thereof.
Background
Dynamic Random Access Memory (DRAM) is a well-known semiconductor Memory device, and is widely used in various electronic devices. A Dynamic Random Access Memory (DRAM) is composed of a plurality of repetitive memory cells (cells), each of which is mainly composed of a transistor and a capacitor operated by the transistor, and the memory cells are arranged in an array form, and each of the memory cells is electrically connected to a Bit Line (BL) through a Word Line (WL). In order to increase the density of Dynamic Random Access Memory (DRAM) devices to increase the operating speed of the devices and meet the demands of consumers for miniaturized electronic devices, the design of the transistor channel region length in the DRAM devices has been continuously shortened recently. However, the transistor has serious problems of short channel effect (short channel effect) and on current (on current) drop.
One known solution is to change a horizontal Transistor structure in a Dynamic Random Access Memory (DRAM) to a vertical Buried Channel Array Transistor (BCAT) structure, and the structure of the Dynamic Random Access Memory (DRAM) having the Buried Channel Array Transistor (BCAT) is shown in fig. 1A and 1B and includes: the semiconductor device comprises a
However, due to the miniaturization of semiconductor devices, the memory cells of a Dynamic Random Access Memory (DRAM) are spaced closer to each other, which often results in a very strong word-line coupling effect (word-line coupling), i.e., a severe coupling effect is easily generated between two adjacent buried
Therefore, it is desirable to design a new integrated circuit memory and a method for manufacturing the same to solve the above-mentioned problems.
Disclosure of Invention
The invention provides an integrated circuit memory and a manufacturing method thereof, which can improve the coupling effect between adjacent embedded word lines and improve the device efficiency and reliability.
To solve the above technical problem, the present invention provides a method for manufacturing an integrated circuit memory, comprising the following steps:
providing a semiconductor substrate, wherein a sacrificial layer is formed on the semiconductor substrate, and a plurality of auxiliary lines are formed on the sacrificial layer and extend along a first direction;
forming side walls on the side walls of the auxiliary lines, wherein the side walls facing each other between the adjacent auxiliary lines define first spaced openings;
removing the auxiliary lines, and etching the sacrificial layer by using the side walls as masks to form a plurality of sacrificial structures extending along the first direction, wherein a second interval opening is formed between two side walls corresponding to the same auxiliary line side wall, and the opening size of the second interval opening is larger than that of the first interval opening;
doping the sacrificial structures by adopting an inclined ion implantation process so as to enable the adjacent sacrificial structures to have different doping concentrations;
filling a mask material layer between the adjacent sacrificial structures and exposing the top surfaces of the sacrificial structures;
etching the sacrificial structures to form mask openings extending into the mask material layer, wherein the depths of the mask openings formed by the adjacent sacrificial structures are different;
etching the residual sacrificial structure by taking the mask material layer as a mask and extending and etching the residual sacrificial structure into the semiconductor substrate to form grooves corresponding to the mask openings, wherein the depths of the adjacent grooves are different; and the number of the first and second groups,
and forming embedded word lines in the grooves, wherein the embedded word lines are asymmetrically arranged in the adjacent grooves.
Optionally, the lateral size of the side wall is 12nm to 18nm, the size of the first spaced opening is 90nm to 100nm, and the size of the second spaced opening is 20nm to 30 nm.
Optionally, the sacrificial structure is doped by using a same tilted ion implantation process, and an included angle between an implantation direction of the same tilted ion implantation process and the surface of the semiconductor substrate is 5 ° to 85 ° or 95 ° to 175 °.
Optionally, the implanted ions of the tilted ion implantation process include at least one of N-type ions, P-type ions, carbon ions, fluorine ions, nitrogen ions, hydrogen ions, oxygen ions, and metal ions.
Optionally, the depth difference between the adjacent grooves is 5nm to 200 nm.
Optionally, the step of forming the buried word line includes:
forming a gate dielectric layer on the surface of the groove;
filling a conductive layer in the groove, wherein the top surface of the conductive layer is lower than the surface of the semiconductor substrate, and the depth difference between the conductive layers in the adjacent grooves is 80 nm-170 nm; and
and filling a grid isolation layer in the groove, wherein the grid isolation layer is laminated on the conductive layer and fills the groove.
The present invention also provides an integrated circuit memory, comprising:
the semiconductor device comprises a semiconductor substrate, wherein grooves with different depths are formed in the semiconductor substrate; and the number of the first and second groups,
and the embedded word lines are embedded in the grooves, and the embedded word lines are asymmetrically arranged in the adjacent grooves.
Optionally, the depth difference between adjacent grooves is 5nm to 200 nm.
Optionally, the size of the transverse opening of each groove is 12nm to 18nm, and the distance between every two adjacent grooves is 20nm to 30 nm.
Optionally, the embedded word lines include gate dielectric layers covering the sidewalls and the bottom surfaces of the recesses, and conductive layers and gate isolation layers sequentially stacked in the recesses having the gate dielectric layers from bottom to top, and a depth difference between the conductive layers of adjacent embedded word lines is 80nm to 170 nm.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. the method for preparing the integrated circuit memory comprises the steps of adopting an inclined ion implantation process with an inclined angle, enabling one sacrificial structure in adjacent sacrificial structures to be shielded by the other sacrificial structure in the inclined ion implantation process and doped slightly or not doped, enabling the two sacrificial structures to have different doping concentrations and different etching selectivity, and accordingly forming mask openings with different depths in a mask material layer due to the fact that the sacrificial structure etched slowly is remained when the sacrificial structure etched quickly is etched, obtaining a first groove and a second groove with different groove depths when the mask material layer is used as a mask and continuously etched downwards to a semiconductor substrate, and further forming embedded word lines with different depths embedded in the first groove and the second groove, by the height difference (i.e., the gap) between the bottom surfaces of the two buried word lines, the coupling effect (i.e., WL-WL coupling effect) between the adjacent buried word lines can be restrained and reduced, and the device performance and reliability can be improved.
2. The integrated circuit memory of the invention is provided with the embedded word lines with different depths embedded in the semiconductor substrate, and the coupling effect (namely WL-WL coupling effect) between the adjacent embedded word lines can be restrained and lightened through the height difference (namely the gap) between the bottom surfaces of the adjacent embedded word lines, thereby improving the device efficiency and the reliability.
Drawings
FIG. 1A is a schematic diagram of a top view of a conventional DRAM with a BCAT.
FIG. 1B is a cross-sectional structure view of the DRAM of FIG. 1A taken along line LL' (only the structure at one active region is shown).
FIG. 2 is a flow chart of a method for fabricating an integrated circuit memory according to an embodiment of the invention.
Fig. 3A to 3I are schematic cross-sectional views of device structures in the method for manufacturing the integrated circuit memory shown in fig. 2.
Wherein the reference numbers are as follows:
100. 300-a semiconductor substrate;
101. 301-shallow trench isolation structures;
102. 302-an active region;
x-a second direction;
y-a first direction;
302 a-a first groove;
302 b-a second groove;
103. 315-buried word line;
104-word line;
303-pad oxide layer;
304-a hard mask layer;
305-a cover layer;
306-a first etch stop layer;
307-sacrificial layer;
308-a second etch stop layer;
309-auxiliary line;
310-side wall material layer;
310 a-side wall;
310 b-a first spaced opening;
310 c-a second spaced opening;
307a, 307 b-sacrificial structures;
307c — remaining sacrificial structures;
311-a layer of masking material;
311 a-first mask opening;
311 b-second mask opening;
312-a gate dielectric layer;
312-a gate dielectric layer;
312 a-a gate dielectric layer in the first recess and the second recess;
313-a conductive layer; 314-a gate isolation layer;
314 a-a gate isolation layer in the first and second recesses;
d1-the sum of the line width of one auxiliary line and the opening size of the interval between two adjacent auxiliary lines;
d2 — line width of auxiliary line, opening size of second spaced opening 310 c;
d3 — opening size of the space between two adjacent auxiliary lines;
d31-line width of the
d32 — opening size of first spaced
d4-the difference in groove depth (gap) of the
Detailed Description
As mentioned above, the electrical characteristics of the Buried Channel Array Transistor (BCAT) in a Dynamic Random Access Memory (DRAM) may vary according to the depth from the upper surface of the semiconductor substrate to the bottom surface of its buried word line, for example, the magnitude of the coupling effect between two adjacent buried word lines in a Dynamic Random Access Memory (DRAM) may vary according to the depth.
Based on the above, the invention provides an integrated circuit memory and a manufacturing method thereof, wherein two adjacent embedded word lines are asymmetrically arranged, a certain height difference is formed between the bottom surfaces of the two embedded word lines, and the height difference is utilized to restrict and reduce the coupling effect between the two adjacent embedded word lines, so that the device efficiency and the reliability are improved.
The integrated circuit memory and the method for manufacturing the integrated circuit memory according to the present invention will be described in detail with reference to fig. 2, fig. 3A to fig. 3H and the following embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2, the present invention provides a method for manufacturing an integrated circuit memory, comprising the following steps:
s1, providing a semiconductor substrate, wherein a sacrificial layer is formed on the semiconductor substrate, and a plurality of auxiliary lines are formed on the sacrificial layer and extend along a first direction to be formed;
s2, forming side walls on the side walls of the auxiliary lines, and defining first interval openings between the side walls facing each other between the adjacent auxiliary lines;
s3, removing the auxiliary lines, and etching the sacrificial layer by using the side walls as masks to form a plurality of sacrificial structures extending along the first direction, wherein a second interval opening is formed between two side walls corresponding to the same auxiliary line side wall, and the opening size of the second interval opening is larger than that of the first interval opening;
s4, doping the sacrificial structures by adopting an inclined ion implantation process so that two adjacent sacrificial structures have different doping concentrations;
s5, filling a mask material layer between the adjacent sacrificial structures and exposing the top surfaces of the sacrificial structures;
s6, etching the sacrificial structures to form mask openings extending into the mask material layer, wherein the depths of the mask openings formed by the adjacent sacrificial structures are different;
s7, with the mask material layer as a mask, etching the remaining sacrificial structures and extending and etching the sacrificial structures into the semiconductor substrate to form grooves corresponding to the mask openings, wherein the depths of the adjacent grooves are different; and the number of the first and second groups,
s8, forming buried word lines in the grooves, wherein the buried word lines are asymmetrically disposed in the adjacent grooves.
First, step S1 is executed, and referring to fig. 2 and fig. 3A specifically, a
referring to fig. 3A, a shallow trench is formed in the
step two, with continued reference to fig. 3A, forming a liner oxide (not shown) on the sidewalls and bottom surface of the shallow trench; specifically, a liner oxide layer can be formed on the side wall and the bottom surface of the shallow trench through a vapor deposition process or a thermal oxidation process;
step three, with continued reference to fig. 3A, filling the shallow trench with silicon dioxide on the liner oxide layer, specifically, first, applying processes such as chemical vapor deposition to the surface of the shallow trench and the surface of the shallow trenchDepositing silicon dioxide on the surface of the silicon nitride hard mask layer until the shallow trench is filled with the silicon dioxide; then, performing top surface planarization on the silicon dioxide by adopting a chemical mechanical planarization process until the top surface of the silicon dioxide is flush with the top surface of the silicon nitride hard mask layer to form a shallow
In addition, in step S1, after the shallow
It should be noted that the
Next, with reference to fig. 3A, a
first, a hard mask layer 304 may be formed on the surface having the shallow trench isolation structure 301 and the pad oxide layer 303 by a Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD), the hard mask layer 304 may be formed on the surface having the shallow trench isolation structure 301 and the pad oxide layer 303 by a chemical vapor deposition (PVD), Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD), the hard mask layer 304 may be made of a material including at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, metal nitride, metal oxide and metal carbide, preferably silicon nitride (SiN), silicon nitride is readily available, low cost, mature in manufacturing method, and has a high etching selectivity with respect to the pad oxide layer 303, and then the cap layer 305 may be formed on the surface of the hard mask layer 304 by a spin coating process, a vacuum evaporation process, a sputtering deposition process or a chemical vapor deposition process, etc., the cap layer 305 may be mainly used to provide a flat process surface for the subsequent formation of the sacrificial layer 307 and to provide a high etching selectivity and a low-Line Edge Roughness (LER) for improving the subsequent transfer effect of the hard mask layer 304, the silicon nitride, the silicon nitride, the silicon nitride, the silicon nitride, the silicon nitride, the.
Step two, forming a sacrificial layer 307 and a second etch stop layer 308 on the surface of the first etch stop layer 306 in sequence, specifically, depositing the sacrificial layer 307 and the second etch stop layer 308 on the surface of the first etch stop layer 306 in sequence by using a Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD), and the like, since the capping layer 305 provides a flat process surface, the thickness of the formed sacrificial layer 307 can be made uniform in the whole, which is beneficial for improving the appearance of a subsequently formed sacrificial structure, the material of the sacrificial layer 307 can be any suitable material capable of changing the etching selectivity by ion doping, and can include at least one of polysilicon, amorphous silicon, monocrystalline silicon, silicon germanium, silicon carbide, a metal and a metal compound, wherein the metal compound is a metal nitride, a metal oxide, a silicon carbide, a metal carbide, The metal carbide, the metal silicide, the metal boride or the metal phosphide, wherein the metal can be a pure metal or an alloy, the pure metal is copper, aluminum, gold, silver, tantalum, titanium, nickel or tungsten, and the alloy comprises at least one of copper, aluminum, gold, silver, tantalum, titanium, nickel and tungsten; the sacrificial layer 307 is preferably polysilicon, which has the advantages of easily available materials, low cost, mature manufacturing method, and capability of changing the etching selection ratio through an ion implantation process. The second
Step three, forming a plurality of
In addition, in order to improve the forming effect of the
Referring to fig. 3B and 3C, in step S2, first, a sidewall material layer 310 may be deposited on the surfaces of the second etch stop layer 308 and the auxiliary line 309 by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like, where the material of the sidewall material layer 310 is selected as long as the material has a higher etching selectivity ratio with respect to the auxiliary line 309 and the second etch stop layer 308, for example, when the auxiliary line 309 is a photoresist and the second etch stop layer 308 is silicon oxynitride, the material of the sidewall material layer 310 may be silicon nitride, silicon oxide, titanium nitride, or other metal compounds; next, the sidewall material layer 310 may be etched by a dry etching process such as plasma etching, so as to form a sidewall 310a on the sidewall of the auxiliary line 309, a line width D31 of the sidewall 310a determines line widths of the first groove 302a and the second groove 302b formed subsequently, that is, a line width of the embedded word line 315 formed subsequently, a line width D31 of the sidewall 310a may be 12nm to 18nm, the sidewall 310a facing each other between the adjacent auxiliary lines 309 defines a first spaced opening 310b, a line width D32 of the first spaced opening 310b determines a spacing distance between the first groove 302a and the second groove 302b formed subsequently in a horizontal direction, a line width D32 of the first spaced opening 310b may be 20nm to 30nm, wherein 2D 31+ D32 is D3.
Referring to fig. 3D and 3E, in step S3, first, the
With continued reference to fig. 3E, in step S4, the
Referring to fig. 3F, in step S5, first, in order to avoid difficulty in filling the adjacent sacrificial structures 307a and 307b with a high aspect ratio and avoid the influence of the existence of the sidewall 310a and the second etch stop layer 308 on the effect of forming the first groove 302a and the second groove 302b by subsequent etching, the sidewall 310a and the remaining second etch stop layer 308 may be removed by wet etching, Chemical Mechanical Planarization (CMP), and other processes; next, a mask material layer 311 may be deposited on the surfaces of the sacrificial structures 307a and 307b and the first etch stop layer 306 by using a Chemical Vapor Deposition (CVD), a Physical Vapor Deposition (PVD), or an Atomic Layer Deposition (ALD), the deposition thickness of the mask material layer 311 is sufficient to fill the gap between the adjacent sacrificial structures 307a and 307b, the material of the mask material layer 311 is required to have a higher etching selectivity than the sacrificial structures 307a and 307b and the first etch stop layer 306, for example, when the sacrificial structures 307a and 307b are made of polysilicon and the first etch stop layer 306 is made of silicon oxynitride, the material of the mask material layer 311 may include at least one of silicon nitride, silicon carbide, silicon oxycarbide (SiOC), and silicon carbonitride (SiCN); the masking material layer 311 may then be processed by an etch-back process or a chemical mechanical planarization process to expose the top surfaces of the sacrificial structures 307a, 307b to facilitate the subsequent etching of the sacrificial structures 307a, 307b, thereby filling the masking material layer between the adjacent sacrificial structures 307a, 307b and exposing the top surfaces of the sacrificial structures 307a, 307 b. In other embodiments of the present invention, when the
Referring to fig. 3G, in step S6, the
Referring to fig. 3H, in step S7, first, the remaining sacrificial structure 307c (i.e., the remaining portion of the sacrificial structure 307b that is etched slowly) and the first etch stop layer 306 and the capping layer 305 are sequentially etched by using the mask material layer 311 as a mask to transfer the pattern in the mask material layer 311 to the capping layer 305, where the capping layer 305 has a deeper opening (corresponding to the first mask opening 311a) that can expose the top surface of the hard mask layer 304 and a shallower opening (corresponding to the second mask opening 311b) that does not expose the top surface of the hard mask layer 304; then, in order to reduce the aspect ratio of the subsequent etching and reduce the generation of etching by-products to improve the etching effect, the mask material layer 311 and the remaining first etching stop layer 306 may be removed by an etching process or a chemical mechanical planarization process; then, with the covering layer 305 with the openings of different depths as a mask, the hard mask layer 304, the pad oxide layer 303, and the semiconductor substrate 300 (including the active region 302 and the shallow trench isolation structure 301) with a partial depth are sequentially etched, so as to form a first groove 302a corresponding to the first mask opening 311a and a second groove 302b corresponding to the second mask opening 311b in the semiconductor substrate 300, where the first groove 302a and the second groove 302b are parallel to each other and have different groove depths, and both shapes may be U-shaped. In this embodiment, the depth of the
In other embodiments of the present invention, in order to avoid the
Referring to fig. 3I, in step S8, the embedded word line 315 embedded in the
first, the pad oxide layer 303, the hard mask layer 304, and the like on the surface of the semiconductor substrate 300 may be removed by an etching process, a chemical mechanical planarization process, or the like, and further cleaned to expose clean surfaces of the active region 302 and sidewalls and bottom surfaces of the first and second grooves 302a and 302 b; then, a thermal oxidation (dry oxygen or wet oxygen) process, a chemical vapor deposition, an atomic layer deposition, or the like may be adopted, a gate dielectric layer 312 covers the sidewalls and the bottom surfaces of the active region 302 and the first and second recesses 302a and 302b, when it is finally required to form the embedded word lines 315 made of polysilicon in the first and second recesses 302a and 302b, the gate dielectric layer 312 may be made of silicon dioxide, and when it is finally required to form the embedded word lines made of metal gate material in the first and second recesses 302a and 302b, the gate dielectric layer 312 may be made of a high-K dielectric (dielectric constant K is greater than 7) such as hafnium oxide; then, a conductive layer 313 is deposited on the surface of the gate dielectric layer 312 by processes such as evaporation, electroplating, chemical vapor deposition, atomic layer deposition, and the like, the deposition thickness of the conductive layer 313 on the bottom surfaces of the first recess 302a and the second recess 302b at least reaches the thickness required by the embedded word line 315 to be formed, the conductive layer 313 may be a single-layer structure or a stacked-layer structure, the material of the conductive layer 313 may be a material for manufacturing a polysilicon gate, such as undoped polysilicon or doped polysilicon, or a material for manufacturing a metal gate, such as a metal barrier layer (TiN, etc.), a work function layer (TiAl, TiN, etc.), and a metal electrode layer (tungsten W, etc.) sequentially stacked on the surface (including the bottom surface and the sidewall) of the gate dielectric layer 312; thereafter, the conductive layer 313 on the region other than the first and second grooves 302a and 302b may be removed by an etch-back or chemical mechanical planarization process, etc., so that the conductive layer 313 is filled only in the first and second grooves 302a and 302b to serve as a conductive portion of the buried word line 315; next, a gate isolation layer 314 may be deposited on the surfaces of the gate dielectric layer 312 (including the portion 312a located in the first and second grooves 302a and 302b) and the conductive layer 313 by using a physical vapor deposition, a chemical vapor deposition, an atomic layer deposition, or the like, wherein the material of the gate isolation layer 314 includes, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride. Thereafter, the excess
Then, LDD (lightly doped drain) ion implantation, Halo (Halo) ion implantation, source-drain heavily doped ion implantation, and the like may be performed on the
Therefore, the method for manufacturing the integrated circuit memory has the advantages that the ion doping concentrations in the two adjacent sacrificial structures are different by adopting the inclined ion implantation process, different etching selection ratios are generated, so that mask openings with different depths can be formed in the second mask layer, the second mask layer can be used as a mask, the semiconductor substrate is etched to form grooves with different groove depths, and further a plurality of embedded word lines with different embedding depths are formed, on one hand, the method can avoid the problem that the photoetching and etching processes are additionally added when one groove is continuously etched on the basis of the two grooves with the same depth to deepen the groove, the process is simple, and the cost is low; on the other hand, the coupling effect between two adjacent embedded word lines can be restrained and reduced by utilizing the height difference between the bottom surfaces of the two embedded word lines embedded in the adjacent grooves with different depths, and the device performance and the reliability are improved.
In addition, the present invention also provides an integrated circuit memory prepared by the above method for preparing an integrated circuit memory, referring to fig. 1 and 3I, the integrated circuit memory includes: a
In this embodiment, the
Since the depth difference between the
The
Furthermore, it should be appreciated that the integrated circuit memory further includes source/drain regions (not shown) formed in the
Further, the top surface of the work function layer in the embedded word line 315 is lower than the top surface of the semiconductor substrate 300 (i.e., the source/drain region), so that the distance between the work function layer and the source/drain region is increased, which is beneficial to preventing gate-to-drain doped region (GIDL) of the work function layer between the source/drain regions.
It should be understood that the respective depths of the
In an embodiment of the present invention, the source/drain region between two buried word lines 315 intersecting with the same
As can be seen from the above description, the embedded word lines are embedded in the first and second recesses having different depths of the semiconductor substrate, and the height difference (i.e., the gap) between the bottom surfaces of the two embedded word lines can restrict and reduce the coupling effect (i.e., the WL-WL coupling effect) between the adjacent embedded word lines, thereby improving the device performance and reliability. The integrated circuit memory of the present invention is suitable for use in applications such as Dynamic Random Access Memory (DRAM).
In addition, the invention also provides an electronic device comprising the integrated circuit memory. That is, the electronic device of the present invention uses the integrated circuit memory of the present invention as a memory for storing data and the like. The electronic equipment can be various mobile terminals such as mobile phones, wearable equipment, notebook computers and tablet computers, and the wearable equipment comprises intelligent glasses, head-wearing equipment and wrist-wearing equipment such as watches and bracelets.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
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