阅读说明：本技术 半导体器件及其制备方法
(Semiconductor device and method for manufacturing the same
) 是由 不公告发明人 于 2018-09-13 设计创作，主要内容包括：本发明提供了一种半导体器件及其制备方法,通过将金属接点和多晶硅接点依次堆叠而形成位元线与半导体衬底(即源/漏区)之间的复合接点,可以降低位元线与半导体衬底(即源/漏区)之间的接触电阻,还能够避免现有技术中当位元线下方基本上是多晶硅接点时,以位元线(即存储器中的位线)为掩膜,刻蚀下方的多晶硅接点过程中的侧向刻蚀导致多晶硅接点中段处截面积变小而阻值升高的问题。(The invention provides a semiconductor device and a preparation method thereof, which can reduce the contact resistance between a bit line and a semiconductor substrate (namely a source/drain region) by sequentially stacking a metal contact and a polysilicon contact to form a composite contact between the bit line and the semiconductor substrate (namely the source/drain region), and can also avoid the problem that the sectional area at the middle section of the polysilicon contact is reduced and the resistance value is increased due to lateral etching in the process of etching the polysilicon contact below the bit line (namely the bit line in a memory) as a mask when the polysilicon contact is basically arranged below the bit line in the prior art.)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate with a grid;
forming a metal contact on the semiconductor substrate on one side of the grid;
forming a first polysilicon contact on the metal contact; and the number of the first and second groups,
forming a bit line on the first polysilicon contact.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the gate electrode includes:
providing a semiconductor substrate, and etching the semiconductor substrate to form a grid groove;
forming a gate dielectric layer on the side wall and the bottom wall of the gate trench;
filling a gate material in the gate trench to form the gate, wherein the top surface of the gate is lower than the top surface of the semiconductor substrate on the side wall of the gate trench; and the number of the first and second groups,
and filling a grid isolation layer in the grid groove, wherein the grid isolation layer fills the grid groove to bury the grid in the grid groove.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the gate is a metal gate, and the gate dielectric layer is a high-K dielectric having a dielectric constant greater than 4; after the gate dielectric layer is formed and before the gate electrode is filled, a metal blocking layer is formed on the surface of the gate dielectric layer, and after the gate electrode is filled, the metal blocking layer surrounds the bottom wall and the side wall of the gate electrode and exposes out of the surface of the gate dielectric layer above the gate electrode, so that the side wall of the gate electrode isolation layer is directly contacted with the surface of the side wall of the gate dielectric layer.
4. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the metal contact and the first polysilicon contact comprises:
forming a hard mask layer on the semiconductor substrate with the grid, wherein the hard mask layer is provided with an opening exposing part of the surface of the semiconductor substrate on one side of the grid;
etching the semiconductor substrate by taking the hard mask layer as a mask to form a contact groove;
filling the metal contact in the contact trench, wherein the top surface of the metal contact is lower than the top surface of the hard mask layer;
and filling the first polysilicon contact in the contact trench.
5. The method of manufacturing a semiconductor device according to claim 4, wherein a second polysilicon contact is filled in the contact trench before the metal contact is filled in the contact trench, the metal contact being stacked on the second polysilicon contact.
6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the step of forming the bit line comprises:
forming a sacrificial layer covering the semiconductor substrate and the first polysilicon contact, wherein the sacrificial layer is provided with an opening exposing partial top surface of the first polysilicon contact;
filling the bit lines in the openings of the sacrificial layer; and the number of the first and second groups,
and removing the sacrificial layer, and sequentially etching the first polysilicon contact and the metal contact to the top interface of the semiconductor substrate by using the bit line as a mask so as to enable the first polysilicon contact and the metal contact to be as wide as the bit line.
7. The method for manufacturing a semiconductor device according to claim 6, further comprising:
forming an interlayer dielectric layer on the semiconductor substrate and the grid electrode, wherein the interlayer dielectric layer buries the bit line; and the number of the first and second groups,
and forming a conductive plug in the interlayer dielectric layer, wherein the bottom surface of the conductive plug is in contact with the surface of the semiconductor substrate on the other side of the grid.
8. The method of manufacturing a semiconductor device according to claim 7, wherein at least one active region is formed in the semiconductor substrate, two gate trenches are arranged side by side in the active region, each gate trench is filled with the gate, a first source/drain region is formed in the active region between the two gate trenches, a second source/drain region is formed in the active region on the opposite side of the two gate trenches, the metal contact is formed above and in electrical contact with the first source/drain region, and the conductive plug is formed above and in electrical contact with the second source/drain region.
9. A semiconductor device, comprising:
a semiconductor substrate having a gate;
the metal contact is positioned on the semiconductor substrate on one side of the grid electrode;
a first polysilicon contact stacked on the metal contact; and the number of the first and second groups,
and a bit line laminated on the first polysilicon contact.
10. The semiconductor device according to claim 9, wherein a gate trench is formed in the semiconductor substrate, the gate is filled in the gate trench and has a top surface lower than a top surface of the semiconductor substrate on sidewalls of the gate trench; the semiconductor device further comprises a gate dielectric layer and a gate isolation layer, wherein the gate dielectric layer is formed on the side wall and the bottom wall of the gate groove; the grid isolation layer is filled in the grid groove and fills the grid groove so as to bury the grid.
11. The semiconductor device according to claim 9, wherein a contact trench is formed in the semiconductor substrate on the gate side, the metal contact is filled in the contact trench, and a top surface of the metal contact is not higher than a top surface of the semiconductor substrate on a sidewall of the contact trench.
12. The semiconductor device of claim 11 further comprising a second polysilicon contact, said second polysilicon contact filling said contact trench, said metal contact overlying said second polysilicon contact.
13. The semiconductor device according to claim 9, further comprising:
the interlayer dielectric layer covers the semiconductor substrate and the grid electrode, and buries the bit line in the interlayer dielectric layer; and the number of the first and second groups,
and the conductive plug is formed in the interlayer dielectric layer, and the bottom surface of the conductive plug is in contact with the surface of the semiconductor substrate on the other side of the grid electrode.
14. The semiconductor device according to claim 13, wherein at least one active region is formed in the semiconductor substrate, two gate trenches are arranged side by side in the active region, each gate trench is filled with the gate, a first source/drain region is formed in the active region between the two gate trenches, a second source/drain region is formed in the active region on the opposite side of the two gate trenches, the metal contact is formed over and in electrical contact with the first source/drain region, and the conductive plug is formed over and in electrical contact with the second source/drain region; gaps are formed between the metal contact and the side walls, opposite to the grid groove, of the first polycrystalline silicon contact, and the gaps are filled with the interlayer dielectric layer.
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a semiconductor device and a preparation method thereof.
Background
Dynamic Random Access Memory (DRAM) is a well-known semiconductor Memory device, and is widely used in various electronic devices. A Dynamic Random Access Memory (DRAM) is composed of a plurality of repetitive memory cells (cells), each of which is mainly composed of a transistor and a capacitor operated by the transistor, and the memory cells are arranged in an array form, and each of the memory cells is electrically connected to a Bit Line (BL) through a Word Line (WL).
In order to increase the integration of Dynamic Random Access Memory (DRAM), increase the operation speed of devices, and meet the demand of consumers for miniaturized electronic devices, the design of the channel region length of the transistor in the DRAM has been continuously shortened recently, but the transistor will generate serious short channel effect (short channel effect) and on-current (on-current) decrease. One known solution is to change a horizontal Transistor structure in a Dynamic Random Access Memory (DRAM) to a vertical Buried Channel Array Transistor (BCAT) structure, and the structure of the Dynamic Random Access Memory (DRAM) having the Buried Channel Array Transistor (BCAT) is shown in fig. 1 and includes: a semiconductor substrate 100, a gate (i.e., a word line) 104, and a bit line (i.e., a bit line of a memory) 110. The gate 104 is embedded in a U-shaped longitudinal trench (not shown) of the semiconductor substrate 100 through a gate isolation layer 105, and is insulated and isolated from the semiconductor substrate 100 through a gate dielectric layer 102, source/drain regions (not shown) are respectively formed in the semiconductor substrate 100 at two sides of the gate 104, a bit line (i.e., a bit line of a memory) 110 is connected with the source/drain region at one side of the gate 104 through a bit line contact (BLcontact)108, the source/drain region at the other side of the gate 104 is led out through an upper conductive plug 112, and the bit line 110 and the conductive plug 112 are both formed in an interlayer dielectric layer 111. Since current needs to flow between a source region (i.e., a source/drain region on one side of the gate 104) and a drain region (i.e., a source/drain region on the other side of the gate 104, not shown) by detour along the U-shaped longitudinal channel portion, the effective channel length is increased, which reduces the area occupied by the transistor in each memory cell and suppresses the short channel effect.
The bit line contact 108 under the bottom of the bit line 110 of the conventional DRAM is mostly formed by polysilicon, that is, the bit line contact 108 is mostly a polysilicon conductive contact structure, and the resistance of polysilicon is high relative to metal, and after the bit line 110 is formed, the bit line contact 108 is etched by using the bit line 110 as a mask, so that the line width of the bit line contact 108 is equal to the line width of the bit line 110, when the bit line complex contact 108 is polysilicon, the process of etching the bit line contact 108 by using the bit line 110 as a mask will generate lateral etching on the middle section of the bit line contact 108, thereby causing the sectional area of the middle section of the bit line contact 108 to be reduced, causing the resistance of the bit line contact 108 to be increased, which will affect the performance and reliability of the memory cell, and even cause the data access error of the.
Therefore, it is necessary to design a new semiconductor device and a method for manufacturing the same to solve the above problems.
Disclosure of Invention
The invention provides a semiconductor device and a manufacturing method thereof, which can reduce the contact resistance of a bit line contact and improve the performance of the device.
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate with a grid;
forming a metal contact on the semiconductor substrate on one side of the grid;
forming a first polysilicon contact on the metal contact; and the number of the first and second groups,
forming a bit line on the first polysilicon contact.
Optionally, the step of forming the gate electrode includes:
providing a semiconductor substrate, and etching the semiconductor substrate to form a grid groove;
forming a gate dielectric layer on the side wall and the bottom wall of the gate trench;
filling a gate material in the gate trench to form the gate, wherein the top surface of the gate is lower than the top surface of the semiconductor substrate on the side wall of the gate trench; and the number of the first and second groups,
and filling a grid isolation layer in the grid groove, wherein the grid isolation layer fills the grid groove to bury the grid in the grid groove.
Optionally, the gate is a metal gate, and the gate dielectric layer is a high-K dielectric with a dielectric constant greater than 4; after the gate dielectric layer is formed and before the gate electrode is filled, a metal blocking layer is formed on the surface of the gate dielectric layer, and after the gate electrode is filled, the metal blocking layer surrounds the bottom wall and the side wall of the gate electrode and exposes out of the surface of the gate dielectric layer above the gate electrode, so that the side wall of the gate electrode isolation layer is directly contacted with the surface of the side wall of the gate dielectric layer.
Optionally, the step of forming the metal contact and the first polysilicon contact comprises:
forming a hard mask layer on the semiconductor substrate with the grid, wherein the hard mask layer is provided with an opening exposing part of the surface of the semiconductor substrate on one side of the grid;
etching the semiconductor substrate by taking the hard mask layer as a mask to form a contact groove;
filling the metal contact in the contact trench, wherein the top surface of the metal contact is lower than the top surface of the hard mask layer;
and filling the first polysilicon contact in the contact trench.
Optionally, before filling the metal contact in the contact trench, a second polysilicon contact is filled in the contact trench, and the metal contact is stacked on the second polysilicon contact.
Optionally, the step of forming the bit line comprises:
forming a sacrificial layer covering the semiconductor substrate and the first polysilicon contact, wherein the sacrificial layer is provided with an opening exposing partial top surface of the first polysilicon contact;
filling the bit lines in the openings of the sacrificial layer; and the number of the first and second groups,
and removing the sacrificial layer, and sequentially etching the first polysilicon contact and the metal contact to the top interface of the semiconductor substrate by using the bit line as a mask so as to enable the first polysilicon contact and the metal contact to be as wide as the bit line.
Optionally, the method for manufacturing a semiconductor device further includes:
forming an interlayer dielectric layer on the semiconductor substrate and the grid electrode, wherein the interlayer dielectric layer buries the bit line; and the number of the first and second groups,
and forming a conductive plug in the interlayer dielectric layer, wherein the bottom surface of the conductive plug is in contact with the surface of the semiconductor substrate on the other side of the grid.
Optionally, at least one active region is formed in the semiconductor substrate, two gate trenches are arranged in the active region side by side, each gate trench is filled with the gate, a first source/drain region is formed in the active region between the two gate trenches, a second source/drain region is formed in the active region on the opposite side of the two gate trenches, the metal contact is formed above the first source/drain region and electrically contacted with the first source/drain region, and the conductive plug is formed above the second source/drain region and electrically contacted with the second source/drain region.
The present invention also provides a semiconductor device comprising:
a semiconductor substrate having a gate;
the metal contact is positioned on the semiconductor substrate on one side of the grid electrode;
a first polysilicon contact stacked on the metal contact; and the number of the first and second groups,
and a bit line laminated on the first polysilicon contact.
Optionally, a gate trench is formed in the semiconductor substrate, the gate is filled in the gate trench, and the top surface of the gate trench is lower than the top surface of the semiconductor substrate on the sidewall of the gate trench; the semiconductor device further comprises a gate dielectric layer and a gate isolation layer, wherein the gate dielectric layer is formed on the side wall and the bottom wall of the gate groove; the grid isolation layer is filled in the grid groove and fills the grid groove so as to bury the grid.
Optionally, a contact trench is formed in the semiconductor substrate on the gate side, the metal contact is filled in the contact trench, and a top surface of the metal contact is not higher than a top surface of the semiconductor substrate on the sidewall of the contact trench.
Optionally, the semiconductor device further includes a second polysilicon contact filled in the contact trench, and the metal contact is stacked on the second polysilicon contact.
Optionally, the semiconductor device further includes:
the interlayer dielectric layer covers the semiconductor substrate and the grid electrode, and buries the bit line in the interlayer dielectric layer; and the number of the first and second groups,
and the conductive plug is formed in the interlayer dielectric layer, and the bottom surface of the conductive plug is in contact with the surface of the semiconductor substrate on the other side of the grid groove.
Optionally, at least one active region is formed in the semiconductor substrate, two gate trenches are arranged in the active region side by side, each gate trench is filled with the gate, a first source/drain region is formed in the active region between the two gate trenches, a second source/drain region is formed in the active region on the opposite side of the two gate trenches, the metal contact is formed above the first source/drain region and electrically contacted with the first source/drain region, and the conductive plug is formed above the second source/drain region and electrically contacted with the second source/drain region; gaps are formed between the metal contact and the side walls, opposite to the grid groove, of the first polycrystalline silicon contact, and the gaps are filled with the interlayer dielectric layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the semiconductor device and the preparation method thereof, the metal contact and the polysilicon contact are sequentially stacked to form the composite contact between the bit line and the semiconductor substrate (namely, the source/drain region), so that the contact resistance between the bit line and the semiconductor substrate (namely, the source/drain region) can be reduced, and the problem that in the prior art, when the polysilicon contact is basically arranged below the bit line, the bit line (namely, the bit line in a memory) is used as a mask, and the sectional area at the middle section of the polysilicon contact is reduced and the resistance value is increased due to lateral etching in the process of etching the polysilicon contact below the bit line can be solved.
2. The semiconductor device and the preparation method thereof are suitable for manufacturing any product with a metal grid electrode, in particular suitable for a Dynamic Random Access Memory (DRAM) with a structure of a Buried Channel Array Transistor (BCAT), and can improve the resistance of a contact at the bottom of a bit line and improve the performance of the DRAM.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional DRAM with a BCAT (only the structure at one active region is shown).
Fig. 2 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.
Fig. 3A to 3J are schematic cross-sectional views of device structures in the method of manufacturing the semiconductor device shown in fig. 2.
Wherein the reference numbers are as follows:
100-a semiconductor substrate;
1002-a first source/drain region;
1003 — second source/drain regions;
101-a gate trench;
102-a gate dielectric layer;
103. 1084, 1087, 1102-metal barrier layer;
104-a gate;
105-a gate isolation layer;
106-hard mask layer;
107-contact trenches;
107 a-gap;
108-bit line contacts;
1080-second polysilicon contact
1081-metal contact;
1082 — a first polysilicon contact;
1083. 1088, 1101 — a metal silicide layer;
1085. 1086, 1103-metal adhesion layer;
109-a sacrificial layer;
109 a-openings in the sacrificial layer;
110-bit lines;
1104-bit line metal layer;
111-interlayer dielectric layer;
112-conductive plug.
Detailed Description
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2, the present invention provides a method for manufacturing a semiconductor device, including the following steps:
s1, providing a semiconductor substrate with a grid;
s2, forming a metal contact on the semiconductor substrate at one side of the grid;
s3, forming a first polysilicon contact on the metal contact; and the number of the first and second groups,
s4, forming a bit line on the first polysilicon contact.
The method for manufacturing a semiconductor device according to the present invention will be described in detail below by taking as an example a method for manufacturing a semiconductor device having a BCAT structure.
Referring to fig. 3A, first, step S1 is executed to provide a semiconductor substrate 100 having a gate 104, which includes the following steps:
first, a semiconductor substrate 100 is provided, wherein the semiconductor substrate 100 may be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon (bulk silicon), germanium, silicon germanium, gallium arsenide, or germanium-on-insulator (ge). The semiconductor substrate 100 in this embodiment includes a base (not shown) and a semiconductor epitaxial layer (not shown) epitaxially grown on the surface thereof. At least one active region (not shown, formed in the semiconductor epitaxial layer) for forming a Buried Channel Array Transistor (BCAT) and a shallow trench isolation structure (not shown) for isolating the active region from the surrounding environment may be defined in the semiconductor substrate 100, and the active region (not shown) may be a fin-type three-dimensional structure or a planar structure. When the semiconductor device to be manufactured is a memory, the shallow trench isolation structure can isolate all active regions into array arrangement so as to manufacture a storage array of the memory. The shallow trench isolation structure canThe method includes forming a shallow trench (not shown) in the semiconductor substrate 100 and a dielectric material filling the shallow trench, where the dielectric material may include a liner oxide (line oxide) formed by a thermal oxidation process and covering the shallow trench and silicon dioxide located on a surface of the liner oxide and filling the shallow trench, so as to improve an isolation performance of the shallow trench isolation structure, and the forming process includes: (1) forming a pad oxide layer (not shown) on the surface of the semiconductor substrate 100 through a thermal oxidation process; (2) forming a silicon nitride hard mask layer (not shown) by a chemical vapor deposition process, and further forming a patterned photoresist layer (not shown) on the silicon nitride hard mask layer by photoresist coating, exposing, developing and other photolithography processes, wherein the patterned photoresist layer covers the active region and the layers above the active region and exposes the silicon nitride hard mask layer above the semiconductor substrate 100 serving as an isolation region between the active regions; (3) performing an etching process on the exposed silicon nitride hard mask layer, the pad oxide layer below the exposed silicon nitride hard mask layer and the semiconductor substrate 100 with a partial depth by using the patterned photoresist layer as a mask to form shallow trenches in the semiconductor substrate 100 between the active regions, wherein the etching process can be dry etching; (4) removing the patterned photoresist layer; (5) forming a line oxide (not shown) on the sidewalls and bottom surface of the shallow trench by a vapor deposition process or a thermal oxidation process; (6) depositing silicon dioxide on the surface of the shallow trench and the surface of the silicon nitride hard mask layer by adopting the processes of chemical vapor deposition and the like until the shallow trench is filled with the silicon dioxide; (7) carrying out top surface planarization on the silicon dioxide by adopting a chemical mechanical planarization process until the top surface of the silicon dioxide is flush with the top surface of the silicon nitride hard mask layer so as to form a shallow trench isolation structure; (8) the silicon nitride hard mask layer can be removed by wet etching and other processes. Further, after depositing silicon dioxide, or after planarizing the top surface of the silicon dioxide, or after removing the silicon nitride hard mask layer, performing densification (densification) on the silicon dioxide by using the high-temperature thermal annealing, high-energy light excitation process such as Ultraviolet (UV) light or laser (laser), and the like to obtain a silicon dioxide with a high-temperature thermal annealing process, a high-energy light excitation process such as a laser (laser), and the likeThe compactness of the dielectric material is increased, the isolation effect of the shallow trench isolation structure is ensured, and the mechanical strength of the shallow trench isolation structure is enhanced. The process temperature of the high-temperature thermal annealing process is, for example, 800 ℃ to 1200 ℃, and ozone (O) can be further introduced when the high-temperature thermal annealing process is performed3) And/or a strongly reactive gas such as carbon monoxide (CO). In addition, after the shallow trench isolation structure is formed, a well region (not shown) may be formed in each active region by an ion implantation process and further combining with annealing activation and other processes, wherein a doping type of the well region is determined by a conductivity type of a BCAT transistor to be formed, for example, in the present embodiment, if the formed BCAT transistor is an N-type transistor, the well region is a P-type doping region. The doping depth of the well region can be adjusted according to actual conditions. It should be noted that the pad oxide layer may protect the semiconductor substrate 100 and the active region during the process of forming the shallow trench isolation structure, and the pad oxide layer may remain to serve as a protection layer for the top surfaces of the semiconductor substrate 100 and the active region in the subsequent process.
Referring to fig. 3A, a patterned hard mask layer (not shown) is sequentially formed on the surface of the shallow trench isolation structure and the pad oxide layer, and the specific forming process includes: (1) a hard mask layer can be formed on the surface with the shallow trench isolation structure and the pad oxide layer through processes of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD) and the like, the material of the hard mask layer comprises at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, metal nitride, metal oxide and metal carbide, preferably silicon nitride (SiN), the silicon nitride material is easy to obtain, low in cost and mature in manufacturing method, and has a higher etching selection ratio with the pad oxide layer; (2) openings for defining gates (i.e., word lines) can be formed by a series of photolithography processes such as photoresist coating, exposure using a gate mask (which is a word line mask when the semiconductor device to be manufactured is a memory), and development; (3) taking the photoresist layer with the opening as a mask, and etching the hard mask layer to the surface of the pad oxide layer so as to transfer a grid (namely word line) pattern in the photoresist into the hard mask layer; (4) and removing the photoresist, and continuously etching downwards by taking the hard mask layer as a mask, namely sequentially etching the pad oxide layer and the semiconductor substrate 100 (comprising the active region and the shallow trench isolation structure) with partial depth to form a gate trench 101 in the semiconductor substrate 100. In this embodiment, the bottom wall of the gate trench 101 also extends down into the substrate 1001. The shape of the gate trench 101 may be a rounded U shape, a right-angled U shape, or a trapezoid with a wide top and a narrow bottom. Since the electrical characteristics of the Buried Channel Array Transistor (BCAT) may vary according to the depth from the upper surface (i.e., the top surface) of the semiconductor substrate 100 to the bottom surface of the buried gate 104 thereof, the depth of the gate trench 101 is adjusted to achieve desired electrical characteristics of the Buried Channel Array Transistor (BCAT), thereby improving the electrical performance and reliability of the finally formed semiconductor device.
With reference to fig. 3A, the pad oxide layer, the hard mask layer, and the like on the surface of the semiconductor substrate 100 may be removed by an etching process or a chemical mechanical planarization process, and further cleaned to expose the clean active region surface and the sidewalls and the bottom surface of the gate trench 101, so as to prepare for forming the gate 104. In this embodiment, two gate trenches 101 are arranged side by side in one active region of the semiconductor substrate 100, an active region between the two gate trenches 101 is subsequently used to form a first source/drain region, and active regions on opposite sides of the two gate trenches 101 are subsequently used to form second source/drain regions, respectively, so that two BCATs can be manufactured in one active region, which is beneficial to improving the device integration level.
Step five, a thermal oxidation (dry oxygen or wet oxygen) process, a chemical vapor deposition (cvd), an atomic layer deposition (ald) process, etc. may be adopted, a gate dielectric layer 102 is covered on the sidewall and the bottom surface of the active region and the gate trench 101, the gate dielectric layer 102 is preferably made of a high-K dielectric (dielectric constant K is greater than 7), for example, Ta2O5、TiO2、TiN、Al2O3、Pr2O3、La2O3、LaAlO3、HfO2、ZrO2Or metal oxides of other constituentsEtc. to be compatible with the metal gate 104 to be formed, which is beneficial to improving the mobility of carriers and improving the device performance. And preferably, the gate dielectric layer 102 made of the high-K dielectric material is prepared by using an Atomic Layer Deposition (ALD) process to maintain the film-forming quality and the thickness uniformity of the gate dielectric layer 102.
And sixthly, depositing the metal barrier layer 103 on the surface of the gate dielectric layer 102 through processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition and the like, preferably preparing the metal barrier layer 103 by adopting the atomic layer deposition process to protect the gate dielectric layer 102 and prevent the quality of the gate dielectric layer 102 from being poor. The metal barrier layer 103, also referred to as a metal barrier layer or a metal adhesion barrier layer, is intended to protect the gate dielectric layer 102 from introducing metal impurities in subsequent steps, and to improve adhesion between the gate dielectric layer 102 and the subsequently formed gate electrode 104. For example, in the present embodiment, the gate 104 includes one or more work function metal layers. Without the metal barrier layer 103, metal material from those work function metal layers would diffuse into the gate dielectric layer 102, causing manufacturing defects. In various embodiments, the metal barrier layer 103 includes a metal layer such as Ti or Ta, a metal nitride layer such as TiAlN, TaCN, TaSiN, TiN, or TaN, or any combination of metals and metal nitrides. It should be appreciated that in some cases, a single metal barrier layer 103 may not provide sufficient protection for the gate dielectric layer 102, and it is necessary to form the metal barrier layer 103 having a multi-layer stacked composite structure in the gate trench 101 to enhance protection for the gate dielectric layer 102, so as to prevent the material in the gate 104 from diffusing into the gate dielectric layer 102 and causing device defects when the surface metal barrier layer 103 is etched and damaged.
And step seven, depositing a metal gate material on the surface of the metal barrier layer 103 through processes such as evaporation, electroplating, chemical vapor deposition, atomic layer deposition and the like, wherein the deposition thickness of the metal gate material on the bottom surface of the first gate trench 101 at least reaches the thickness required by the gate 104 to be formed.
Step eight, removing the metal gate material on the region outside the gate trench 101 by back etching, and enablingThe metal gate material is only filled in the gate trench 101 and used as the gate 104, and the etch-back process makes the height of the gate 104 smaller than the depth of the gate trench 101 and makes the height of the metal barrier layer 103 not lower than the gate 104. The gate 104 is typically a stacked structure, and includes a work function metal layer overlying the metal barrier layer 103 and a metal electrode layer surrounded by the work function metal layer. The material of the work function metal layer is determined by the conductivity type of the BCAT transistor to be formed, and when the BCAT transistor to be formed is a P-type transistor, the work function metal layer in the metal gate 104 is a P-type work function metal material, which may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2、MoSi2、TaSi2、NiSi2W or other suitable p-type work function material, or a combination thereof, and when the BCAT transistor to be formed is an N-type transistor, the work function metal layer in the metal gate 104 is an N-type work function metal material, which includes Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function material, or a combination thereof. The work function metal layer may be a single layer or may be a plurality of layers. In this embodiment, the top surface of the gate 104 is lower than the top surfaces of the semiconductor substrate 100 on both sides, and further lower than the top surfaces of the first source/drain region 1002 and the second source/drain region 1003 formed subsequently, so that the distance between the work function metal layer and the first source/drain region 1002 and the second source/drain region 1003 is increased, which is beneficial to preventing gate-induced drain current leakage (GIDL) from occurring between the first source/drain region 1002 and the second source/drain region 1003. The material of the metal electrode layer may include Al, W, Cu, and/or other suitable metal materials.
Step nine, referring to fig. 3B, a gate isolation layer 105 is deposited on the semiconductor substrate 100, the gate dielectric layer 102, the metal barrier layer 103 and the gate 104 by using physical vapor deposition, chemical vapor deposition, atomic layer deposition and other processes, wherein the material of the gate isolation layer 105 includes but is not limited to silicon oxide, silicon nitride and silicon oxynitride.
Step ten, please refer to fig. 3C, can be performed by chemical mechanical planarizationThe process removes the excess gate isolation layer 105 and the gate dielectric layer 102 on the top surface of the semiconductor substrate 100 to form a gate 104 embedded in the gate trench 101, and further performs LDD (lightly doped drain) ion implantation, Halo (Halo) ion implantation, source-drain heavily doped ion implantation, and the like on the active region on both sides of the gate (i.e., the gate trench 101) with the gate 104 and the gate isolation layer 105 as masks to form a first source/drain region 1002 and a second source/drain region 1003 in the active region on both sides of the gate 104 (i.e., the gate trench 101), respectively, so that the gate 104 and the first source/drain region 1002 and the second source/drain region 1003 respectively located on both sides of the gate 104 constitute a main part of the BCAT structure. In the present embodiment, since two gate trenches 101 are formed in one active region, two BCATs can be fabricated in one active region, and a first source/drain region 1002 shared by the two BCATs is formed in the active region between the two gate trenches 101, the shared first source/drain region 1002 can be a drain region electrically connected to a subsequently formed bit line 110 (i.e., a bit line of a memory), and the second source/drain region 1003 can be a source region electrically connected to a subsequently formed conductive plug 112. In other embodiments of the present invention, the gate dielectric layer 102 and the gate isolation layer 105 on the surface of the active region between the two gates 104 and outside the two gates 104 may also be etched by an etching process to form an opening exposing the surface of the active region for forming the first source/drain region 1002 and the second source/drain region 1003, and then LDD (lightly doped drain) ion implantation, Halo (Halo) ion implantation, source-drain heavily doped ion implantation, and the like are performed on the exposed active region with the remaining gate dielectric layer 102 and the gate isolation layer 105 as masks to form the first source/drain region 1002 and the second source/drain region 1003 in the active region on both sides of the gate 104. When the gate trench 101 is a U-shaped groove, a U-shaped conductive channel may be formed in a conducting direction along a current (i.e., a current flowing direction of the source region to the drain region which are located at both sides of the gate electrode 104), thereby increasing a length of the conductive channel. Therefore, as the size of the transistor is reduced, even if the absolute distance between the source region and the drain region on both sides of the gate electrode 104 is reduced, the transistor can be effectively improved because the formed conductive channel is a U-shaped channelShort channel effects of the structure. In addition, the first source/drain region 1002 and the second source/drain region 1003 are based on transistor structures with different conductivity types, and the first source/drain region 1002 and the second source/drain region 1003 are doped with ions with corresponding conductivity types, for example, when the transistor structure is an N-type transistor, the doped ions in the source/drain regions are N-type doped ions, and the N-type doped ions are, for example, phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions; when the transistor structure is a P-type transistor, the doped ions in the source/drain region are P-type doped ions, such as boron (B) ions and Boron Fluoride (BF)2 +) Ions, gallium (Ga) ions, and indium (In) ions.
Referring to fig. 3D and 3E, in step S2, a metal contact (metal contact)1081 is formed on the first source/drain region 1002, which includes the following steps:
referring to fig. 3D, a hard mask layer 106 may be deposited by using a chemical vapor deposition, a physical vapor deposition, or the like, where the hard mask layer 106 covers the first source/drain region 1002, the second source/drain region 1003, and the gate isolation layer 105, and a material of the hard mask layer 106 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, for example. And further opening the hard mask layer 106 above the first source/drain region 1002 through photolithography and etching processes to form an opening exposing the surface of the first source/drain region 1002.
Referring to fig. 3D, the first source/drain region 1002 is etched to a certain depth by using the hard mask layer 106 having the opening as a mask, so as to form a contact trench 107, wherein a bottom surface of the contact trench 107 is higher than a top surface of the gate 104, so as to enhance isolation between the bit line 110 and the gate 104 formed subsequently. In this embodiment, the contact trenches 107 are respectively connected to two gate trenches 101 at sidewalls thereof.
Referring to fig. 3D and 3E, a first layer of polysilicon, a metal barrier layer, and a metal adhesion layer are deposited on the surfaces of the contact trench 107 and the hard mask layer 106 by using any suitable process of physical vapor deposition, chemical vapor deposition, atomic layer deposition, and the like, wherein the first layer of polysilicon may include at least one of doped polysilicon and undoped polysilicon, and the first layer of polysilicon, the metal barrier layer 1084, and the metal adhesion layer 1085 outside the contact trench 107 are further removed by an etching process or a Chemical Mechanical Planarization (CMP) process to form a second polysilicon contact 1080, a metal barrier layer 1084, and a metal adhesion layer 1085 which are sequentially stacked. The second polysilicon contact 1080 is used for protecting the first source/drain region 1002 from being damaged by the metal contact 1081 manufacturing process, the metal adhesion layer 1085 can enhance the adhesion between the subsequent metal contact 1081 and the second polysilicon contact 1080, thereby preventing the metal contact 1081 from being in poor contact with the first source/drain region 1002, and the material of the metal adhesion layer 1085 can be W, Ti or Ta; the metal barrier layer 1084 may prevent the metal in the metal contact 1081 from diffusing into the first source/drain region 1002 to affect the performance of the first source/drain region 1002, and the material of the metal barrier layer 1084 may be a metal nitride such as TiAlN, TaCN, TaSiN, TiN, or TaN; in addition, in the present embodiment, in order to reduce the contact resistance between the second polysilicon contact 1080 and the subsequently formed metal contact 1081, a metal silicide layer 1083 is further formed between the interface of the metal barrier layer 1084 and the second polysilicon contact 1080, and the metal silicide layer 1083 may be a metal silicide containing at least one of metal elements such as Ti, W, Co, Ni, Zr, Mo, and Ta. The formation process of the metal silicide layer 1083 is preferably: by using a metal material or a metal nitride material for forming the metal barrier layer 1084, a metal-containing thin film is deposited on the surface of the second polysilicon contact 1080, and then annealing is performed, so that the surface layer of the second polysilicon contact 1080 and the metal in the metal-containing thin film naturally react, and a metal silicide layer 1083 is formed at the interface of the second polysilicon contact 1080, thereby simplifying the process, saving the cost, and enhancing the adhesion between the second polysilicon contact 1080 and the metal barrier layer 1084 while reducing the contact resistance. In other embodiments of the present invention, one, two or all of the second polysilicon contact 1080, the metal barrier layer 1084 and the metal adhesion layer 1085 may be omitted.
Referring to fig. 3E, the contact trench 107 may be filled with Al, W, Cu and/or other suitable metal materials by evaporation, electroplating, chemical vapor deposition, atomic layer deposition, and the like, and the metal material on the top of the hard mask layer 106 is further removed by a chemical mechanical planarization process to form a metal contact 1081.
Referring to fig. 3E and 3F, in step S3, a first polysilicon contact (poly contact)1082 is filled in the contact trench 107, specifically, by employing any suitable one of physical vapor deposition (including sputtering, evaporation), chemical vapor deposition, atomic layer deposition and the like, a metal adhesion layer 1086, a metal barrier layer 1087, a metal silicide layer 1088 and a second polysilicon layer are sequentially formed on the surfaces of the hard mask layer 106 and the contact trench 107 having the metal contact 1081, and further removing the metal adhesion layer 1086, the metal barrier layer 1087, the metal silicide layer 1088 and the second polysilicon layer outside the contact trench 107 through an etching process or a Chemical Mechanical Planarization (CMP) process, to form a metal adhesion layer 1086, a metal barrier layer 1087, a metal silicide layer 1088 and a first polysilicon contact 1082, which are sequentially stacked on the metal contact 1081. The first polysilicon contact 1082 may include at least one of doped polysilicon and undoped polysilicon, and the thickness of the first polysilicon contact 1082 is greater than that of the second polysilicon contact 1080, which may be equal to or greater than that of the metal contact 1081, so as to reduce the contact resistance between the bit line 110 and the first source/drain region 1002 and ensure the advantages of the bit line 110 when the contact is made of polysilicon only; the metal adhesion layer 1086 can enhance the adhesion between the metal contact 1081 and the first polysilicon contact 1082, and prevent the metal contact 1081 from making poor contact with the first polysilicon contact 1082, wherein the metal adhesion layer 1086 may be W, Ti or Ta; the metal barrier layer 1087 can prevent the metal in the metal contact 1081 from diffusing into the first polysilicon contact 1082 to affect the performance of the first polysilicon contact 1082, and the material of the metal barrier layer 1087 may be TiAlN, TaCN, TaSiN, TiN, TaN, or other metal nitrides; the metal silicide layer 1088 may reduce contact resistance between the first polysilicon contact 1082 and the metal contact 1081, and the metal silicide layer 1088 may be a metal silicide including at least one of metal elements of Ti, W, Co, Ni, Zr, Mo, Ta, and the like. The formation process of the metal silicide layer 1087 is preferably: after the second polysilicon layer is deposited, an annealing process is performed to form a metal silicide layer 1088 at the interface of the metal barrier layer 1087 and the first polysilicon contact 1082 by utilizing the natural reaction of the metal and silicon at the interface of the metal barrier layer 1087 and the first polysilicon contact 1082, thereby simplifying the process, saving the cost, and enhancing the adhesion between the first polysilicon contact 1082 and the metal barrier layer 1087 while reducing the contact resistance. In other embodiments of the invention, the metal barrier layer 1087 and/or the metal adhesion layer 1086 may also be omitted.
Referring to fig. 3G and 3H, in step S4, the bit line 110 is formed on the first polysilicon contact 1082, which includes:
referring to fig. 3G, a sacrificial layer 109 may be formed by spin coating, chemical vapor deposition, physical vapor deposition, or the like to cover the hard mask layer 106 and the first polysilicon contact 1082, and an opening 109a may be further formed in the sacrificial layer 109 by photolithography, etching, or the like, wherein the width of the opening 109a is smaller than the width of the contact trench 107 shown in fig. 3D to expose a portion of the top surface of the first polysilicon contact 1082; the sacrificial layer 109 is deposited to a thickness that determines the height of the bit line 110, and may be made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material, and/or other suitable insulating material.
Referring to fig. 3G and 3H, a metal silicide layer 1101, a metal barrier layer 1102, a metal adhesion layer 1103 and a bit line metal layer 1104 are sequentially formed in the opening 109a by any suitable process of evaporation, plating, chemical vapor deposition, atomic layer deposition and the like, and a chemical mechanical planarization process is further employed to remove the metal material on the top of the sacrificial layer 109, so as to form the bit line 110. Wherein, the bit line metal layer 1104 fills the opening 109a, and may comprise Al, W, Cu and/or other suitable metal materials; the metal adhesion layer 1103 can enhance the adhesion between the bit line metal layer 1104 and the first polysilicon contact 1082, and prevent the bit line metal layer 1104 from making poor contact with the first polysilicon contact 1082, and the material of the metal adhesion layer 1103 can be W, Ti or Ta; the metal barrier layer 1102 can prevent the metal in the bit line metal layer 1104 from diffusing into the first polysilicon contact 1082 to affect the performance of the first polysilicon contact 1082, and the material of the metal barrier layer 1102 can be TiAlN, TaCN, TaSiN, TiN, TaN or other metal nitrides; the metal silicide layer 1101 may reduce contact resistance between the first polysilicon contact 1082 and the bit line metal layer 1104, and the metal silicide layer 1101 may be a metal silicide containing at least one of metal elements of Ti, W, Co, Ni, Zr, Mo, Ta, and the like. The formation process of the metal silicide layer 1101 is preferably: an annealing process is performed after the deposition of the metal barrier layer 1102 to form the metal silicide layer 1101 at the interface of the metal barrier layer 1102 and the first polysilicon contact 1082 by utilizing the natural reaction of the metal and silicon at the interface of the metal barrier layer 1102 and the first polysilicon contact 1082, thereby simplifying the process, saving the cost, and enhancing the adhesion between the first polysilicon contact 1082 and the metal barrier layer 1102 while reducing the contact resistance. In other embodiments of the present invention, one or more of the metal silicide layer 1101, the metal barrier layer 1102 and the metal adhesion layer 1103 may also be omitted.
Step three, referring to fig. 3G to fig. 3I, the sacrificial layer 109 is removed by using an appropriate process such as etching, and further the bit line 110 is used as a mask to sequentially etch the first polysilicon contact 1082 and the metal contact 1081, and the etching is stopped at the interface of the first source/drain region 1002 and the second polysilicon contact 1080 to form a gap 107a, at this time, the bit line composite contact 108 having a width equal to that of the bit line 110 is formed by a structure that the second polysilicon contact 1080 is stacked from bottom to top to the first polysilicon contact 1082, and a gap 107a is formed between the bit line composite contact 108 and the opposite side wall of the gate dielectric layer 102. Since the bit line composite contact 108 is a composite structure and mainly comprises the metal contact 1081 and the first polysilicon contact 1082 stacked on the metal contact 1081, the contact resistance can be reduced by using the low resistance characteristic of the metal material, and the problems of the prior art that the cross section area of the sidewall of the polysilicon bit line contact is reduced and the resistance value is increased due to lateral etching can be avoided.
Referring to fig. 3J, the conductive plug 112 on the second source/drain region 1003 can be fabricated later, which includes the following steps:
first, the hard mask layer 106 may be removed by a suitable process (e.g., wet etching), and a chemical mechanical planarization process may be further combined with the processes of spin coating, chemical vapor deposition, physical vapor deposition, etc., to form an interlayer dielectric layer 111 with a flat top surface to cover the gate isolation layer 105, the first source/drain region 1002, the second source/drain region 1003, and the bit line 110, the interlayer dielectric layer 111 fills the gap 107a and buries the bit line 110 and the bit line composite contact 108 therein, and the interlayer dielectric layer 111 may be made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable insulating materials.
Then, a contact hole (not shown) aligned with the second source/drain region 1003 is formed in the interlayer dielectric layer 111 by photolithography, etching, or the like, and the contact hole exposes a portion of the top surface of the second source/drain region 1003.
Then, a metal material such as W is filled into the contact hole through a plating, sputtering, or other process, so as to form a conductive plug 112 filled in the contact hole of the interlayer dielectric layer 111, wherein a bottom surface of the conductive plug 112 contacts with a top surface of the second source/drain region 1003.
The preparation method of the semiconductor device of the invention, replace the existing single polycrystalline silicon bit line joint with the bit line composite joint formed by stacking the polycrystalline silicon joint above the metal joint, thus can utilize the characteristic that the metal has low resistance to reduce the contact resistance, and because the total thickness of the bit line composite joint is limited, after setting up the metal joint, equivalent to reducing the thickness of the polycrystalline silicon joint, therefore can avoid using bit line as the lateral etching problem that the middle section of polycrystalline silicon joint causes when etching the bit line composite joint, guarantee the side wall appearance of the bit line composite joint, and then improve the efficiency and reliability of the device. The preparation method of the semiconductor device is particularly suitable for manufacturing the memory. When the method for manufacturing a semiconductor device of the present invention is applied to the fabrication of a memory, the gates 104 of the plurality of active regions are aligned and connected together to form a word line of the memory, and the bit lines 110 of the plurality of active regions are aligned and connected together to form a bit line of the memory. For example, referring to fig. 3A to 3J, in an embodiment of the present invention, the semiconductor substrate 100 has a plurality of active regions (not shown) arranged in a cell row (i.e., corresponding to a word line direction) and a cell column (i.e., corresponding to a bit line direction), and shallow trench isolation structures (not shown) are further disposed between adjacent active regions, that is, all the shallow trench isolation structures may include a plurality of parallel and a plurality of intersecting shallow trench isolation structures, so as to isolate all the active regions into an array structure arranged in a cell row and a cell column for manufacturing a memory array of a memory. Each of the active regions arranged in the word line direction intersects with two adjacent gate trenches 101. The gate 104 filled in each gate trench 101 serves as a word line corresponding to a corresponding cell row, and the bit line 110 on the active region between two gate trenches 101 serves as a bit line on a corresponding cell column.
Referring to fig. 3A to 3J, an embodiment of the present invention provides a semiconductor device, which is preferably manufactured by the above-mentioned manufacturing method of the semiconductor device of the present invention. The semiconductor device includes: a semiconductor substrate 100 having a gate 104, a bit line composite contact 108, a bit line 110, an interlayer dielectric layer 111, and a conductive plug 112.
The semiconductor device further includes a gate isolation layer 105, wherein the gate isolation layer 105 is filled in the gate trench 101 and fills the gate trench 101, and the gate isolation layer 105 is buried in the gate trench 101 and fills the gate trench 101 to bury the gate 104.
In this embodiment, the semiconductor device further includes a gate dielectric layer 102 and a metalThe gate dielectric layer 102 is formed on the side wall and the bottom wall of the gate trench 101, the metal barrier layer 103 is formed between the gate dielectric layer 102 and the gate 104 and surrounds the bottom wall and the side wall of the gate 104, and the metal barrier layer 103 exposes the surface of the side wall of the gate dielectric layer 102 above the gate 104. The gate dielectric layer 102 is preferably made of a high-K dielectric (dielectric constant K is greater than 7), such as Ta2O5、TiO2、TiN、Al2O3、Pr2O3、La2O3、LaAlO3、HfO2、ZrO2Or metal oxides of other compositions, etc. to be compatible with the gate 104, which is beneficial to improving the mobility of carriers and improving the device performance. The metal barrier layer 103 is intended to protect the gate dielectric layer 102, to prevent introduction of metal impurities into the gate dielectric layer 102, and to improve adhesion between the gate dielectric layer 102 and the gate electrode 104. The metal barrier layer 103 may have a single-layer structure or a stacked-layer structure, and include a metal layer such as Ti or Ta, a metal nitride layer such as TiAlN, TaCN, TaSiN, TiN, or TaN, or at least one of a metal and a metal nitride. In this embodiment, the gate 104 may include one or more work function metal layers and a metal electrode layer surrounded by the work function metal layers, wherein the material of the work function metal layers is determined by the conductivity type of the BCAT transistor to be formed, and when the BCAT transistor to be formed is a P-type transistor, the work function metal layer in the metal gate 104 is a P-type work function metal material, and the P-type work function metal material may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2、MoSi2、TaSi2、NiSi2W or other suitable p-type work function material, or a combination thereof, and when the BCAT transistor to be formed is an N-type transistor, the work function metal layer in the gate 104 is an N-type work function metal material, and the N-type work function metal material includes Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function material, or a combination thereof; the material of the metal electrode layer may include Al, W, Cu, and/or other suitable metal materials.
In this embodiment, the bit line composite contact 108 is formed on the first source/drain region 1002, and the top surface of the bit line composite contact 108 may be flush with the top surface of the gate isolation layer 105, may be lower than the top surface of the gate isolation layer 105, and may be higher than the top surface of the gate isolation layer 105. The bitline composite contact 108 includes a metal contact 1081 and a first polysilicon contact 1082 stacked thereon. A second polysilicon contact 1080, a metal silicide layer 1083, a metal barrier layer 1084 and a metal adhesion layer 1085 are sequentially stacked from bottom to top between the metal contact 1081 and the first source/drain region 1002, and a metal adhesion layer 1086, a metal barrier layer 1087 and a metal silicide layer 1088 are sequentially stacked from bottom to top between the metal contact 1081 and the first polysilicon contact 1082. The second polysilicon contact 1080 can protect the first source/drain region 1002, the metal adhesion layer 1085 can enhance adhesion between the metal contact 1081 and the first source/drain region 1002, prevent the bit line composite contact 108 from making poor contact with the first source/drain region 1002, the metal adhesion layer 1086 can enhance adhesion between the metal contact 1081 and the first polysilicon contact 1082, prevent the first polysilicon contact 1082 from making poor contact with the metal contact 1081, and the metal adhesion layers 1085 and 1086 can be W, Ti or Ta; the metal barrier layer 1084 can prevent the metal in the metal contact 1081 from diffusing into the first source/drain region 1002 to affect the performance of the first source/drain region 1002, the metal barrier layer 1087 can prevent the metal in the metal contact 1081 from diffusing into the first polysilicon contact 102 to affect the performance of the first polysilicon contact 1082, and the material of the metal barrier layers 1084 and 1087 can be TiAlN, TaCN, TaSiN, TiN, TaN, or other metal nitrides; the metal silicide layer 1083 may reduce contact resistance between the metal contact 1081 and the first source/drain region 1002, the metal silicide layer 1088 may reduce contact resistance between the metal contact 1081 and the first polysilicon contact, and the metal silicide layers 1083, 1088 may be a metal silicide including at least one of metal elements of Ti, W, Co, Ni, Zr, Mo, Ta, and the like.
A gap is formed between the bit line composite contact 108 and the opposite side wall of the gate trench 101; a bit line 110 formed on the bit line composite contact 108, wherein the bit line 110 and the bit line composite contact 108 are arranged with the same width; the bit line 110 includes a metal silicide layer 1101, a metal barrier layer 1102, a metal adhesion layer 1103, and a bit line metal layer 1104 stacked from the bottom up side. Bit line metal layer 1104 may comprise Al, W, Cu, and/or other suitable metal materials; the metal adhesion layer 1103 can enhance the adhesion between the bit line metal layer 1104 and the first polysilicon contact 1082, and prevent the bit line metal layer 1104 from making poor contact with the first polysilicon contact 1082, and the material of the metal adhesion layer 1103 can be W, Ti or Ta; the metal barrier layer 1102 can prevent the metal in the bit line metal layer 1104 from diffusing into the first polysilicon contact 1082 to affect the performance of the first polysilicon contact 1082, and the material of the metal barrier layer 1102 can be TiAlN, TaCN, TaSiN, TiN, TaN or other metal nitrides; the metal silicide layer 1101 may reduce contact resistance between the first polysilicon contact 1082 and the bit line metal layer 1104, and the metal silicide layer 1101 may be a metal silicide containing at least one of metal elements of Ti, W, Co, Ni, Zr, Mo, Ta, and the like.
The semiconductor device of the embodiment further includes an interlayer dielectric layer 111, the interlayer dielectric layer 111 covers the gate isolation layer 105, the first source/drain region 1002, the second source/drain region 1003, the bit line 110 and the bit line composite contact 108, the interlayer dielectric layer 111 fills the gap on the side wall of the bit line composite contact 108, and the bit line 110 and the bit line composite contact 108 are buried therein. A conductive plug 112 is formed in the interlayer dielectric layer 111, and a bottom surface of the conductive plug 112 contacts a top surface of the second source/drain region 1003.
In an embodiment of the present invention, a plurality of active regions (not shown) are formed in the semiconductor substrate 100, two gate trenches 101 are disposed in each of the active regions side by side, an active region between two gate trenches 101 (a first source/drain region 1002 is formed therein, a second source/drain region 1003 is formed in the active region on the opposite side of the two gate trenches 101, the bit line composite contact 108 is formed above the first source/drain region 1002 and the bottom surface thereof is in contact with the top surface of the first source/drain region 1002, the conductive plug 112 is formed above the second source/drain region 1003 and the bottom surface thereof is in contact with the top surface of the second source/drain region 1003, thereby forming two BCATs in one active region and improving device integration The cell rows are arranged in an array, the gates in each cell row are connected as a whole to serve as a word line of the memory, and the bit lines 110 in each cell row are connected as a whole to serve as a bit line of the memory.
In addition, the invention also provides electronic equipment comprising the semiconductor device. The electronic equipment can be various mobile terminals such as mobile phones, wearable equipment, notebook computers and tablet computers, and the wearable equipment comprises intelligent glasses, head-wearing equipment and wrist-wearing equipment such as watches and bracelets.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
