阅读说明：本技术 集成电路时钟树综合优化方法 (Integrated circuit clock tree comprehensive optimization method ) 是由 栾志勇 闵嘉华 杨洋 于 2019-10-23 设计创作，主要内容包括：本发明涉及集成电路设计行业自动化EDA技术领域,提供了一种集成电路时钟树综合优化方法,包括以下步骤：S1.预设时钟树约束文件中的参数；S2.根据参数自动生成线路布局；S3.调整线路布局中寄存器的位置,使时钟源到每一个寄存器的布线长度之间的差值位于预设范围之内；S4.在时钟信号源处设置若干驱动单元,用于驱动时钟树的负载；S5.替换驱动单元,使每一个驱动单元的驱动能力相同。通过这种设计,对集成电路后端设计过程中最重要的时钟树综合设计环节进行了设计顺序的标准化,使其具有良好的通用性,从而降低了后端环节的设计门槛,降低了人力成本,提高设计效率,保证了设计质量。(The invention relates to the technical field of automatic EDA (electronic design automation) in the integrated circuit design industry, and provides a comprehensive optimization method of an integrated circuit clock tree, which comprises the following steps: s1, presetting parameters in a clock tree constraint file; s2, automatically generating a circuit layout according to the parameters; s3, adjusting the positions of the registers in the line layout to enable the difference value between the clock source and the wiring length of each register to be within a preset range; s4, arranging a plurality of driving units at the clock signal source for driving the load of the clock tree; and S5, replacing the driving units to enable the driving capability of each driving unit to be the same. Through the design, the most important clock tree comprehensive design link in the rear end design process of the integrated circuit is standardized in the design sequence, so that the design sequence has good universality, the design threshold of the rear end link is reduced, the labor cost is reduced, the design efficiency is improved, and the design quality is ensured.)

1. A method for comprehensively optimizing an integrated circuit clock tree is characterized by comprising the following steps:

s1, presetting parameters in a clock tree constraint file;

s2, automatically generating a circuit layout according to the parameters;

s3, adjusting the positions of the registers in the line layout to enable the difference value between the clock source and the wiring length of each register to be within a preset range;

s4, arranging a plurality of driving units at the clock signal source for driving the load of the clock tree;

and S5, replacing the driving units to enable the driving capability of each driving unit to be the same.

2. The integrated circuit clock tree synthesis optimization method of claim 1, wherein the parameters include buffer type, target value of clock offset, maximum delay, minimum delay, maximum fan-out, and clock tree routing rules.

3. The integrated circuit clock tree synthesis optimization method of claim 2, wherein the buffer is an X4 buffer.

4. The integrated circuit clock tree synthesis optimization method of claim 1, wherein in step S3, the preset range is 20 to 40 microcells.

5. The integrated circuit clock tree comprehensive optimization method according to claim 1, wherein in step S4, the driving unit is a driving unit of X6 or X8.

Technical Field

The invention relates to the technical field of automatic EDA (electronic design automation) in the integrated circuit design industry, in particular to a comprehensive optimization method of an integrated circuit clock tree.

Background

The rapid development of moore's law has now enabled the integration of hundreds of millions of transistors on a single semiconductor chip. The rapid increase in semiconductor integration density also presents significant challenges to the design architecture of digital circuits.

Clock tree structures are initially generated by Electronic Design Automation (EDA) software systems by using a clock network consisting of fan-out buffers or fan-out inverters to transmit clock signals from a clock signal source to other clock receivers. The clock tree may change the number of buffers or inverters and send clock signals to the clock receivers, typically depending on the number of clock receivers that need to receive the clock signals.

In the layout design process of the chip, a time sequence driving layout method is mostly adopted, and the layout density is limited in the process, so that the clock offset can be reduced as much as possible. However, the method for automatically generating the integrated circuit layout circuit through software is firstly obtained based on the algorithm of a computer and the experience of predecessors, and is not necessarily effective for the innovative integrated circuit; secondly, after the integrated circuit layout circuit is automatically generated, the circuit is analyzed and adjusted by a plurality of methods, which are more biased to personal experience and difficult for novices to learn the essence thereof.

Disclosure of Invention

Thus, the present application provides a method for comprehensively optimizing an integrated circuit clock tree, comprising the following steps:

s1, presetting parameters in a clock tree constraint file;

s2, automatically generating a circuit layout according to the parameters;

s3, adjusting the positions of the registers in the line layout to enable the difference value between the clock source and the wiring length of each register to be within a preset range;

s4, arranging a plurality of driving units at the clock signal source for driving the load of the clock tree;

and S5, replacing the driving units to enable the driving capability of each driving unit to be the same.

Preferably, the parameters include buffer type, target value of clock offset, maximum delay, minimum delay, maximum fan-out, and clock tree routing rules.

Preferably, the buffer is an X4 buffer.

Preferably, in step S3, the preset range is 20 to 40 microcells.

Preferably, in step S4, the driving unit is a driving unit of X6 or X8.

In the method, the design sequence of the most important clock tree comprehensive design link in the rear-end design process of the integrated circuit is standardized by designing a set of clock tree comprehensive method flow, so that the method has good universality, and the probability of pairing can be improved even by a novice hand as long as the method is carried out according to the flow, so that the design threshold of the rear-end link is reduced, the labor cost is reduced, the design efficiency is improved, and the design quality is ensured.

Drawings

FIG. 1 is a block flow diagram of a method for integrated circuit clock tree synthesis optimization.

Detailed Description