阅读说明：本技术 包括电荷存储装置和存取装置之间的选通区的集成存储器 (Integrated memory including a gated region between a charge storage device and an access device ) 是由 S·J·德尔纳 C·L·英戈尔斯 于 2019-08-08 设计创作，主要内容包括：本申请涉及包括电荷存储装置和存取装置之间的选通区的集成存储器。一些实施例包含具有存取晶体管的集成式组合件。所述存取晶体管具有以选通方式与第二源极/漏极区耦合的第一源极/漏极区。数字线与所述第一源极/漏极区耦合。电荷存储装置经由互连件与所述第二源极/漏极区耦合。所述互连件包含一定长度的半导体材料。保护晶体管选通所述半导体材料的所述长度的一部分。(The present application relates to an integrated memory including a gated region between a charge storage device and an access device. Some embodiments include an integrated assembly having an access transistor. The access transistor has a first source/drain region that is gated coupled to a second source/drain region. A digit line is coupled with the first source/drain region. A charge storage device is coupled with the second source/drain region via an interconnect. The interconnect includes a length of semiconductor material. A protection transistor gates a portion of the length of the semiconductor material.)

1. An integrated assembly, comprising:

an access transistor having a first source/drain region and a second source/drain region that are coupled to each other in a gated manner;

a digit line coupled with the first source/drain region;

a charge storage device coupled with the second source/drain region via an interconnect; the interconnect comprises a length of semiconductor material; and

a protection transistor gating a portion of the length of the semiconductor material.

2. The integrated assembly of claim 1, wherein the length of the semiconductor material is a vertically extending pillar of the semiconductor material.

3. The integrated assembly of claim 1, wherein:

the access transistor comprises a horizontally extending channel region between the first and second source/drain regions;

the protection transistor comprises third and fourth source/drain regions within the length of the semiconductor material; and

the protection transistor includes a vertically extending channel region between the third and fourth source/drain regions.

4. The integrated assembly of claim 1, wherein:

the access transistor comprises a first gate; and

the protection transistor includes a second gate electrically coupled to the first gate.

5. The integrated assembly of claim 1, wherein:

the access transistor comprises a first gate; and

the protection transistor includes a second gate that is not electrically coupled to the first gate.

6. The integrated assembly of claim 1, wherein the charge storage device is a capacitor.

7. An integrated assembly, comprising:

a first access transistor and a second access transistor; the first access transistor comprises a first gate proximate a first channel region and the second access transistor comprises a second gate proximate a second channel region; the first and second access transistors together comprise three source/drain regions, one of which is shared by the first and second access transistors; the three source/drain regions are a first source/drain region, a second source/drain region, and a third source/drain region, wherein the first and second source/drain regions are strobedly coupled to each other via the first channel region, and wherein the second and third source/drain regions are strobedly coupled to each other via the second channel region;

a digit line coupled with the second source/drain region;

a first charge storage device coupled with the first source/drain region via a first interconnect;

a second charge storage device coupled with the third source/drain region via a second interconnect;

a first switch controlling current flow along the first interconnect; and

a second switch controlling current flow along the second interconnect.

8. The integrated assembly of claim 7, wherein the first interconnect comprises a first length of a first semiconductor material, and wherein the second interconnect comprises a second length of a second semiconductor material.

9. The integrated assembly of claim 8, wherein the first switch controls current flow along the first length of the first semiconductor material; and wherein the second switch controls current flow along the second length of the second semiconductor material.

10. The integrated assembly of claim 9, wherein the first switch is a first protection transistor, and wherein the second switch is a second protection transistor.

11. The integrated assembly of claim 10, wherein:

the first protection transistor comprises a third gate electrically coupled with the first gate; and

the second protection transistor includes a fourth gate electrically coupled with the second gate.

12. The integrated assembly of claim 10, wherein:

the first protection transistor comprises a third grid;

the second protection transistor comprises a fourth gate; and

the third and fourth gates are part of a multiplexer circuit and are coupled with a multiplexer driver.

13. The integrated assembly according to claim 7, wherein the first and second charge storage devices are first and second capacitors, respectively.

14. An integrated assembly, comprising:

a first access transistor and a second access transistor; the first access transistor comprises a first gate proximate a first channel region and the second access transistor comprises a second gate proximate a second channel region; the first and second access transistors together comprise three source/drain regions, one of which is shared by the first and second access transistors; the three source/drain regions are a first source/drain region, a second source/drain region, and a third source/drain region, wherein the first and second source/drain regions are strobedly coupled to each other via the first channel region, and wherein the second and third source/drain regions are strobedly coupled to each other via the second channel region; the first channel region extends horizontally between the first and second source/drain regions; the second channel region extends horizontally between the second and third source/drain regions;

a digit line coupled with the second source/drain region;

a first capacitor coupled with the first source/drain region via a first interconnect; the first interconnect comprises a first vertically extending pillar of a first semiconductor material;

a second capacitor coupled with the third source/drain region via a second interconnect; the second interconnect comprises a second vertically extending pillar of a second semiconductor material;

a first protection transistor gating a portion of the first vertically extending pillar of the first semiconductor material; and

a second protection transistor gating a portion of the second vertically extending pillar of the second semiconductor material.

15. The integrated assembly of claim 14, wherein the first and second protection transistors comprise third and fourth gates, respectively; and wherein the third and fourth gates are over the first and second gates.

16. The integrated assembly of claim 15, wherein the digit line is above the first and second gates and below the third and fourth gates.

17. The integrated assembly of claim 15, wherein:

the third gate is electrically coupled with the first gate; and

the fourth gate is electrically coupled with the second gate.

18. The integrated assembly of claim 15, wherein the third and fourth gates are part of a multiplexer circuit and are coupled with a multiplexer driver.

Technical Field

An integrated memory including a gated region between a charge storage device and an access device.

Background

Modern computing architectures utilize memory to store data. One type of memory is Dynamic Random Access Memory (DRAM). DRAM may provide the advantages of simple structure, low cost, and fast speed compared to alternative types of memory.

DRAM may utilize memory cells, each having one capacitor in combination with one transistor (a so-called 1T-1C memory cell), where the capacitor is coupled with the source/drain region of the transistor. An example 1T-1C memory cell 2 is shown in FIG. 1, with the transistor labeled T and the capacitor labeled C. The capacitor has one node coupled to the source/drain region of the transistor and has another node coupled to the common plate CP. The common plate can be coupled with any suitable voltage, such as a voltage in the range of greater than or equal to ground to less than or equal to VCC (i.e., ground ≦ CP ≦ VCC). In some applications, the common plate is at a voltage of about one-half VCC (i.e., about VCC/2). The gate of the transistor is coupled to a word line WL (i.e., an access line) and the source/drain regions are coupled to bit lines BL (i.e., digit lines or sense lines). In operation, an electric field generated by a voltage along a word line can gate the bit line to the capacitor during read/write operations.

Another prior art 1T-1C memory cell configuration is shown in FIG. 2. The configuration of FIG. 2 shows two memory cells 2a and 2 b; wherein memory cell 2a includes transistor T1 and capacitor C1, and memory cell 2b includes transistor T2 and capacitor C2. Word lines WL0 and WL1 are electrically coupled to the gates of transistors T1 and T2, respectively. The connection to the bit line BL is shared by the memory cells 2a and 2 b.

The memory cells described above can be incorporated into a memory array, and in some applications the memory array can have an open bit line arrangement. An example integrated assembly 9 having an open bitline architecture is shown in fig. 3. The assembly 9 includes two laterally adjacent memory arrays ("array 1" and "array 2"), with each of the arrays including memory cells of the type described in figure 2 (not labeled in figure 3 in order to simplify the drawing). Word lines WL0-WL7 extend across the array and are coupled with word line drivers. The digit lines D0-D8 are associated with the first array (array 1) and digit lines D0-D8 are associated with the second array (array 2). Sense amplifiers SA0-SA8 are disposed between the first and second arrays. The digitlines at the same height are paired with each other and compared via sense amplifiers (e.g., digitlines D0 and D0 are paired with each other and compared with sense amplifier SA 0). In a read operation, one of the paired digit lines can serve as a reference in determining an electrical property (e.g., voltage) of the other of the paired digit lines.

A problem that may be encountered with conventional DRAMs is that operation of memory cells along a row may be problematic to disturb memory cells along an adjacent row, and may ultimately result in data loss from one or more of the memory cells along the adjacent row. It would be desirable to develop arrangements that avoid such data loss.

Disclosure of Invention

In one aspect, the present application provides an integrated assembly comprising: an access transistor having a first source/drain region and a second source/drain region that are coupled to each other in a gated manner; a digit line coupled with the first source/drain region; a charge storage device coupled with the second source/drain region via an interconnect; the interconnect comprises a length of semiconductor material; and a protection transistor gating a portion of the length of the semiconductor material.

In another aspect, the present application provides an integrated assembly comprising: a first access transistor and a second access transistor; the first access transistor comprises a first gate proximate a first channel region and the second access transistor comprises a second gate proximate a second channel region; the first and second access transistors together comprise three source/drain regions, one of which is shared by the first and second access transistors; the three source/drain regions are a first source/drain region, a second source/drain region, and a third source/drain region, wherein the first and second source/drain regions are strobedly coupled to each other via the first channel region, and wherein the second and third source/drain regions are strobedly coupled to each other via the second channel region; a digit line coupled with the second source/drain region; a first charge storage device coupled with the first source/drain region via a first interconnect; a second charge storage device coupled with the third source/drain region via a second interconnect; a first switch controlling current flow along the first interconnect; and a second switch controlling current flow along the second interconnect.

In another aspect, the present application provides an integrated assembly comprising: a first access transistor and a second access transistor; the first access transistor comprises a first gate proximate a first channel region and the second access transistor comprises a second gate proximate a second channel region; the first and second access transistors together comprise three source/drain regions, one of which is shared by the first and second access transistors; the three source/drain regions are a first source/drain region, a second source/drain region, and a third source/drain region, wherein the first and second source/drain regions are strobedly coupled to each other via the first channel region, and wherein the second and third source/drain regions are strobedly coupled to each other via the second channel region; the first channel region extends horizontally between the first and second source/drain regions; the second channel region extends horizontally between the second and third source/drain regions; a digit line coupled with the second source/drain region; a first capacitor coupled with the first source/drain region via a first interconnect; the first interconnect comprises a first vertically extending pillar of a first semiconductor material; a second capacitor coupled with the third source/drain region via a second interconnect; the second interconnect comprises a second vertically extending pillar of a second semiconductor material; a first protection transistor gating a portion of the first vertically extending pillar of the first semiconductor material; and a second protection transistor gating a portion of the second vertically extending pillar of the second semiconductor material.

Drawings

FIG. 1 is a schematic diagram of a prior art memory cell having 1 transistor and 1 capacitor.

FIG. 2 is a schematic diagram of a pair of prior art memory cells each having 1 transistor and 1 capacitor and sharing a bitline connection.

FIG. 3 is a schematic diagram of a prior art integrated assembly having an open bit line architecture.

FIG. 4 is a schematic diagram of an example memory array illustrating an example intercell scrambling problem.

FIG. 5 is a schematic cross-sectional side view showing regions of an example integrated assembly that may be within the memory array of FIG. 4.

Fig. 6 is a schematic cross-sectional side view showing the zones of an example integrated assembly.

FIG. 7 is a schematic diagram showing regions of an example memory array that may include the assembly of FIG. 6.

FIG. 8 is a schematic cross-sectional side view showing regions of an example integrated assembly that may be within the memory array of FIG. 7 and that may be a specific example of the more general assembly of FIG. 6.

Fig. 9 is a schematic cross-sectional side view showing regions of an example integrated assembly.

FIG. 10 is a schematic diagram showing regions of an example memory array that may include the assembly of FIG. 9.

FIG. 11 is a schematic cross-sectional side view showing regions of an example integrated assembly that may be within the memory array of FIG. 10 and that may be a specific example of the more general assembly of FIG. 9.

Detailed Description

Some embodiments include integrated assemblies having memory cells, each memory cell including an access transistor associated with a charge storage device (e.g., a capacitor). Each memory cell also includes a protection transistor (or other suitable switch) to control current flow between the charge storage device and the source/drain region of the associated transistor, which can mitigate or prevent the problematic data loss discussed above in the background section. Example embodiments are described with reference to fig. 4-11.

Referring to fig. 4, a region of memory array 10 is shown to include a plurality of digit lines (DL0, DL1, DL1, and DL3), a plurality of word lines (WL0, WL1, WL2, and WL 3). The memory cell 12 is addressed by a word line and a digit line. Each of the memory cells includes a transistor and a capacitor, and is similar to the memory cells 2a and 2b described above with reference to fig. 2. The digit lines extend to sense amplifiers (SA0, SA1, SA2, and SA3), and the word lines extend to row drivers. In some embodiments, memory array 10 is considered to correspond to one of the arrays described above with reference to FIG. 3 (i.e., array-1 or array-2).

The node of the capacitor is connected to reference structure 19. The reference structure may comprise any suitable voltage; and in some embodiments may correspond to a common plate of the type described above with reference to figures 1 and 2.

Block 14 is provided around the row addressed by word line WL0 to indicate that this word line is activated. Activation of word line WL0 accesses memory cell 12 along this word line for various operations (e.g., read/write operations, refresh operations, etc.). Often, some memory array rows will be activated much more frequently than other memory array rows. A row that is activated frequently may be referred to as "bumped" because it experiences excellent usage. As discussed above in the background section, a problem that can occur is that the operation (i.e., activation) of one row of memory cells can be problematic to disturb an adjacent row of memory cells. This problem may especially be manifested adjacent to rows that are "banged".

Fig. 5 shows a cross section along the region of the memory array 10 of fig. 4, and shows each of the memory cells 12 including the capacitor 16 and the transistor 18. Capacitor 16 may be considered an example of a charge storage device that may be utilized in memory cell 12. In other embodiments, other suitable charge storage devices may be utilized; examples of other suitable charge storage devices include phase change materials, conductive bridging materials, and the like.

The transistors and capacitors are supported by a mount 30 comprising a semiconductor material 32. Semiconductor material 32 may include any suitable composition; and may in some embodiments comprise, consist essentially of, or consist of silicon, germanium, III/V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, and the like; the term III/V semiconductor material refers to a semiconductor material that includes an element selected from groups III and V of the periodic table (where groups III and V are old nomenclature and are now referred to as groups 13 and 15). For example, semiconductor material 32 may comprise, consist essentially of, or consist of monocrystalline silicon.

The base 30 may be referred to as a semiconductor substrate. The term "semiconductor substrate" is meant to include any construction of semiconductor material, including, but not limited to, bulk semiconductor materials such as semiconductor wafers (either alone or in assemblies comprising other materials), and layers of semiconductor material (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base 30 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, and the like.

The transistor is shown having a gate 20 along word lines WL0-WL3, and having source/drain regions 22 extending into the semiconductor material 32 of the pedestal 30. The source/drain regions may comprise conductively-doped regions within semiconductor material 32.

The gate 20 is spaced apart from the semiconductor material 32 by a dielectric material (i.e., insulating material) 24. Dielectric material 24 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide. Dielectric material 24 may be referred to as a gate dielectric material.

Transistor 18 has a channel region 26 under gate 20; and the source/drain regions of each of the transistors are gate-coupled to each other via a channel region therebetween. In the illustrated embodiment, the channel region 26 extends horizontally between the source/drain regions 22.

The capacitor 16 is coupled with vertically extending interconnects 28, which in turn are coupled with some of the source/drain regions 22. The other source/drain regions 22 are coupled with digit line DL0 via vertically extending interconnects 34. Interconnects 28 and 34 may comprise any suitable conductive composition.

Transistors 18 are in a paired relationship such that two adjacent transistors share a common connection to the digit line. For example, two of the transistors are labeled 18a and 18b, and such transistors are paired with each other. Transistors 18a and 18b may be referred to as first and second transistors, respectively. Transistors 18a and 18b together include three source/drain regions (labeled 22a, 22b, and 22 c). The source/drain regions 22a, 22b, and 22c may be referred to as first, second, and third source/drain regions, respectively. The second source/drain region 22b is shared between the first and second transistors 18a and 18b and is coupled with a digit line DL 0. The first source/drain region is coupled to a first capacitor (labeled 16a) and the third source/drain region is coupled to a second capacitor (labeled 16 b).

The channel regions of the first and second transistors 18a and 18b are labeled 26a and 26b and may be referred to as first and second channel regions, respectively.

The memory cells including the first and second transistors 18a and 18b are labeled as memory cells 12a and 12b and may be referred to as first and second memory cells, respectively.

Isolation material 36 extends into base 30 and separates the paired transistor arrangements from each other. The release material 36 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silicon oxide.

Word line WL0 is surrounded by box 14 to indicate that this word line is activated. Another frame 15 is provided within the pedestal 30 near word line WL1 to indicate that this region may be interrupted during activation of word line WL 0. Such interruptions within the region of block 15 may result in junction leakage and/or other mechanisms (as schematically shown with arrow 37) that cause current to discharge from capacitor 16b into mount 30, and thus may be problematic resulting in loss of data from memory cell 12 b.

Some embodiments include providing a protection transistor between the capacitor 16 and the associated source/drain region (e.g., along interconnect 28) to mitigate problematic discharge of current from the capacitor into the base when an adjacent row is "bumped". For example, fig. 6 shows the regions of the memory array 10 modified to include the protection transistors 40 between the capacitors 16 and the source/drain regions 22, and particularly along the interconnects 28. The protection transistors coupled with the source/drain regions 22a and 22c are labeled as transistors 40a and 40b and may be referred to as first and second protection transistors, respectively.

In some embodiments, transistor 18 may be referred to as an access transistor in order to distinguish it from protection transistor 40.

The interconnects 28 are shown as posts 42 extending to include semiconductor material 44. The pillars 42 extend vertically, and may be referred to as extending the length of the semiconductor material 44 vertically. In other embodiments, the length of semiconductor material 44 may extend in a direction other than vertical.

In the embodiment shown, each of the interconnects 28 includes a first conductive material 46 underlying the semiconductor material 44. The first conductive material 46 may comprise any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, first material 46 may comprise the same composition as semiconductor material 44 and may be a conductively doped extension of semiconductor material 44.

Semiconductor material 44 may include any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon, germanium, III/V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, and the like; wherein the term III/V semiconductor material refers to a semiconductor material comprising an element selected from groups III and V of the periodic table (wherein groups III and V are old nomenclature and are now referred to as groups 13 and 15). In some example embodiments, semiconductor material 44 may comprise polysilicon.

In some embodiments, materials 44 and 46 may be considered together to form interconnect 28 extending between source/drain region 22 and capacitor 16. In the embodiment shown, the interconnect associated with capacitor 16a is labeled interconnect 28a, and the interconnect associated with capacitor 16b is labeled interconnect 28 b. Interconnects 28a and 28b may be referred to as first and second interconnects, respectively; and are coupled to the first and third source/drain regions 22a and 22 c. The pillars (i.e., lengths of semiconductor material) 42a and 42b within interconnects 28a and 28b may be referred to as first and second pillars (or as first and second lengths of semiconductor material), respectively; and the semiconductor material 44a and 44b within such pillars may be referred to as first and second semiconductor materials, respectively.

The protection transistor 40 includes a conductive gate material 48 and includes an insulating material 50 between the gate material 48 and the semiconductor material 44 of the pillar 42.

The gating material 48 may comprise any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). The gating material 48 is configured as a transistor gate 49.

Insulating material 50 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide. Insulating material 50 may be referred to as a gate dielectric material in some embodiments.

Protection transistor 40 includes source/drain regions 52 and 54, and a channel region 56 between the source/drain regions. Source/drain region 54 may be referred to as an upper source/drain region and source/drain region 52 may be referred to as a lower source/drain region. A channel region 56 extends vertically between the upper and lower source/drain regions. In some embodiments, protection transistor 40 may be referred to as a vertical transistor due to vertically extending channel region 56; and access transistor 18 may be referred to as a planar transistor due to the horizontally extending channel region 26. In some embodiments, access transistor 18a may be considered to have first and second source/drain regions 22a and 22b spaced apart from one another by a horizontally extending channel region 26 a; and protection transistor 40a may be considered to include third and fourth source/drain regions 52a and 54a spaced apart from one another by a vertically extending channel region 56 a.

Channel region 56 corresponds to a gated portion of pillar 42 (i.e., a gated portion corresponding to the length of semiconductor material 44). In some embodiments, channel region 56 may be referred to as a gated portion of interconnect 28.

In some embodiments, the protection transistor 40 may be considered an example of a switch that controls current flow along the interconnect 28. Such switches may have a "closed" operating state and an "open" operating state. The closed operating state will enable current flow between the capacitor 16 and the source/drain region 22. In the embodiment shown, "closing" of such a switch corresponds to providing an appropriate voltage to gate 49 to enable current flow between source/drain regions 52 and 54 across channel region 56. The memory cells 12 may be subjected to read/write operations, refresh operations, etc. when the switch is closed. The open operating state of the switch will impede current flow between the capacitor 16 and the source/drain region 22 and can be used to prevent unwanted leakage (and associated data loss) from the capacitor 16 of the memory cell 12 when the memory cell is in a rest mode (i.e., in a non-access mode). In the embodiment shown, the "off" of the switch corresponds to the voltage along gate 49 being insufficient to achieve coupling of source/drain regions 52 and 54 across channel region 56.

In some embodiments, the protection transistor 40 may be used to mitigate or even prevent data loss from memory cells adjacent to a "bumped" row; for example, data from memory cell 12b along word line WL1 is avoided from being lost in applications where the adjacent word line WL0 is a "bumped" word line.

In the embodiment shown, each of the protection transistors 40 has a gate 49 that is electrically coupled with the gate 20 of the access transistor 18 within the same memory cell 12 as the protection transistor 40. For example, the gate 20a of the access transistor within memory cell 12a may be referred to as a first gate and, in the embodiment of FIG. 6, is electrically coupled with a second gate corresponding to the gate 49a of the protection transistor 40a within memory cell 12 a.

In some embodiments, the first and second access transistors 18a and 18b may be considered to include first and second gates 20a and 20b, respectively; and the protection transistors 40a and 40b may be considered to include third and fourth gates 49a and 49b, respectively. In the embodiment of FIG. 6, third gate 49a is electrically coupled to first gate 20a, and fourth gate 49b is electrically coupled to second gate 20 b.

The various components of FIG. 6 may have any suitable architectural relationship with respect to one another. For example, the embodiment of fig. 6 shows third and fourth gates 49a and 49b over first and second gates 20a and 20 b; and a digit line DL0 between the elevations of the third and fourth gates and the elevations of the first and second gates is shown. In other embodiments, the digit lines may be placed in any other suitable location. Also, the various gates 20a, 20b, 49a, 49b, etc. may be placed in any suitable orientation relative to one another.

Fig. 7 schematically illustrates the memory array 10 of fig. 6. The schematic illustration of FIG. 7 shows that the gate 49a of the protection transistor 40a is coupled with the same word line (WL0) as the gate 20a of the access transistor 18 a; and the gate 49b of the protection transistor 40b is shown coupled with the same word line (WL1) as the gate 20b of the access transistor 18 b.

The capacitor 16 of fig. 6 may have any suitable configuration. FIG. 8 shows a region of memory array 10 that is similar to the region of the memory array of FIG. 6, but shows a specific example configuration of capacitor 16. Each of the capacitors 16 includes a first conductive node 58, a second conductive node 60, and an insulating material 62 between the first and second conductive nodes. The first and second conductive nodes 60 and 62 may comprise any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). The first and second conductive nodes may comprise the same composition as each other, or may comprise different compositions relative to each other. The insulating material 62 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

In the illustrated embodiment, the lower conductive node 58 is configured as an upwardly open container. In other embodiments, the lower conductive node may have other suitable shapes. The lower conductive node 58 may be referred to as a storage node and the upper node 60 may be referred to as a plate electrode. In some embodiments, the plate electrodes within the memory array 10 may all be coupled to each other and may be coupled to a reference voltage (e.g., a common plate voltage).

In some embodiments, the gate 49 of the protection transistor 40 may not be coupled with the gate 20 of the access transistor 18, but may instead be coupled with multiplexer (mux) circuitry so that the protection transistor may be controlled separately from the access transistor. For example, FIG. 9 shows a region of memory array 10 that is similar to the region of the memory array of FIG. 6, but with the gates of protection transistors 40 coupled with mux wires (mux0, mux1, mux2, and mux3) that extend to the mux drivers.

FIG. 10 shows a schematic illustration of the memory array 10 of FIG. 9 and shows mux wires coupled with mux drivers while word lines are coupled with row drivers. Utilizing a mux driver to control the protection transistor 40 may enable improved operational control of the protection transistor for some applications. However, utilization of a mux driver may increase manufacturing complexity compared to an architecture without a mux driver (e.g., the architecture of fig. 7). Accordingly, the architecture of fig. 7 may be preferred in some applications, and the architecture of fig. 10 may be preferred in other applications.

The capacitor 16 of fig. 9 may have any suitable configuration. FIG. 11 shows a region of memory array 10 that is similar to the region of the memory array of FIG. 9, but shows a specific example configuration of capacitor 16. In the shown embodiment of fig. 11, the capacitor 16 has the same configuration as described above with reference to fig. 8.

The assemblies and structures discussed above may be utilized within an integrated circuit (the term "integrated circuit" refers to an electronic circuit supported by a semiconductor substrate); and may be incorporated into an electronic system. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic system may be any of a wide range of systems: such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular telephones, personal computers, automobiles, industrial control systems, aircraft, and so forth.

Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or to be developed, including, for example, Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), etc.

The terms "dielectric" and "insulating" may be used to describe a material having insulating electrical properties. The terms are considered synonymous in this disclosure. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may be used to provide a linguistic variation within the disclosure to simplify the premise foundation within the appended claims, rather than to indicate any significant chemical or electrical difference.

The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims refer to any structure having a described relationship between various features, regardless of whether the structure is in a particular orientation in the drawings or rotated relative to such orientation.

Unless otherwise specified, the cross-sectional views of the accompanying figures show only features within the cross-sectional plane and not material behind the cross-sectional plane in order to simplify the drawings.

When a structure is referred to above as being "on," "adjacent to," or "against" another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly against" another structure, there are no intervening structures present.

Structures (e.g., layers, materials, etc.) may be referred to as extending "vertically" to indicate that the structures extend generally upward from an underlying base (e.g., substrate). The vertically extending structures may or may not extend generally orthogonally relative to the upper surface of the base.

Some embodiments include an integrated assembly having an access transistor. The access transistor has a first source/drain region that is gated coupled to a second source/drain region. The digit line is coupled to the first source/drain region. The charge storage device is coupled with the second source/drain region via an interconnect. The interconnect comprises a length of semiconductor material. The protection transistor gates a portion of the length of semiconductor material.

Some embodiments include an integrated assembly including a first access transistor and a second access transistor. The first access transistor includes a first gate proximate the first channel region and the second access transistor includes a second gate proximate the second channel region. The first and second access transistors together include three source/drain regions, one of which is shared by the first and second access transistors. The three source/drain regions are a first source/drain region, a second source/drain region, and a third source/drain region. The first and second source/drain regions are coupled to each other in a gated manner via the first channel region. The second and third source/drain regions are coupled to each other in a gated manner via the second channel region. The digit line is coupled to the second source/drain region. The first charge storage device is coupled with the first source/drain region via a first interconnect. The second charge storage device is coupled with the third source/drain region via a second interconnect. The first switch controls current flow along the first interconnect. The second switch controls current flow along the second interconnect.

Some embodiments include an integrated assembly including a first access transistor and a second access transistor. The first access transistor includes a first gate proximate the first channel region and the second access transistor includes a second gate proximate the second channel region. The first and second access transistors together include three source/drain regions, one of which is shared by the first and second access transistors. The three source/drain regions are a first source/drain region, a second source/drain region, and a third source/drain region. The first and second source/drain regions are coupled to each other in a gated manner via the first channel region. The second and third source/drain regions are coupled to each other in a gated manner via the second channel region. The first channel region extends horizontally between the first and second source/drain regions. The second channel region extends horizontally between the second and third source/drain regions. The digit line is coupled to the second source/drain region. The first capacitor is coupled with the first source/drain region via a first interconnect. The first interconnect includes a first vertically extending pillar of a first semiconductor material. The second capacitor is coupled with the third source/drain region via a second interconnect. The second interconnect includes a second vertically extending pillar of a second semiconductor material. The first protection transistor gates a portion of the first vertically extending pillar of the first semiconductor material. The second protection transistor gates a portion of the second vertically extending pillar of the second semiconductor material.

In accordance with the provisions, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are, therefore, to be accorded the full scope as literally set forth and appropriately interpreted in accordance with the doctrine of equivalents.