阅读说明：本技术 具有选择性基于页面刷新的存储器装置 (Memory device with selective page-based refresh ) 是由 A·D·阿克勒 于 2018-07-17 设计创作，主要内容包括：本文揭示具有选择性基于页面刷新的存储器装置及系统的若干实施例。在一个实施例中，一种存储器装置包含控制器，其可操作地耦合到具有包括多个存储器页面的至少一个存储器区域的主存储器。所述控制器经配置以在存储于所述存储器装置及/或主机装置上的一或多个刷新调度表中跟踪具有刷新调度的所述多个存储器页面中的存储器页面子集。在一些实施例中，所述控制器经进一步配置以根据所述刷新调度来刷新所述存储器页面子集。(Several embodiments of memory devices and systems having selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory area comprising a plurality of memory pages. The controller is configured to track a subset of memory pages of the plurality of memory pages having a refresh schedule in one or more refresh schedules stored on the memory device and/or a host device. In some embodiments, the controller is further configured to refresh the subset of memory pages according to the refresh schedule.)

1. A memory device, comprising:

a main memory including a memory area having a plurality of memory pages; and

a controller operably coupled to the main memory, wherein the controller is configured to:

tracking a first subset of the plurality of memory pages having a first refresh schedule and a second subset of the plurality of memory pages having a second refresh schedule different from the first refresh schedule,

refreshing the first subset of memory pages according to the first refresh schedule, an

Refreshing the second subset of memory pages according to the second refresh schedule.

2. The memory device of claim 1, wherein the first subset is a contiguous range of memory pages, and the controller is configured to track the first subset using an identifier of a first page of the range and an identifier of a last page of the range.

3. The memory device of claim 1, wherein the first subset is a contiguous range of memory pages, and the controller is configured to track the first subset using an identifier of a first page of the range and a length of the range.

4. The memory device of claim 1, wherein the controller is further configured to transition a first memory page from the first subset to the second subset.

5. The memory device of claim 4, wherein the controller is further configured to remove imprint from the first memory page by repeatedly refreshing the first memory page.

6. The memory device of claim 1, wherein the controller is further configured to consolidate data in memory pages corresponding to the first subset into physically contiguous memory pages within the plurality of memory pages.

7. The memory device of claim 1, wherein the controller is further configured to:

tracking a third subset of the plurality of memory pages having a third refresh schedule that is different from the first refresh schedule and the second refresh schedule.

8. The memory device of claim 7, wherein the third refresh schedule corresponds to never refreshing the third subset.

9. The memory device of claim 1, wherein at least one of the first refresh schedule and the second refresh schedule varies with elapsed time from a last refresh operation.

10. The memory device of claim 1, wherein at least one of the first refresh schedule and the second refresh schedule varies with a number of operations since a last refresh operation.

11. The memory device of claim 1, wherein the memory area is a ferroelectric memory.

12. The memory device of claim 1, wherein the memory region is a polymer memory.

13. The memory device of claim 1, wherein the controller is configured to track the first subset and the second subset in one or more refresh schedules stored in at least one of the main memory and the controller.

14. A method of managing a memory device having a plurality of memory pages, comprising:

tracking a first subset of the plurality of memory pages having a first refresh schedule and a second subset of the plurality of memory pages having a second refresh schedule different from the first refresh schedule;

refreshing the first subset of memory pages according to the first refresh schedule, an

Refreshing the second subset of memory pages according to the second refresh schedule.

15. The method of claim 14, further comprising: tracking a third subset of the plurality of memory pages having a third refresh schedule that is different from the first refresh schedule and the second refresh schedule.

16. The method of claim 14, further comprising: the first memory page is converted from the first subset to the second subset.

17. The method of claim 16, further comprising: merging data in memory pages corresponding to the first subset into physically contiguous memory pages within the plurality of memory pages.

18. The method of claim 16, wherein the first subset and the second subset are tracked in one or more refresh schedules and the method further comprises: updating the first refresh schedule corresponding to the first memory page to a third refresh schedule in the one or more refresh schedules.

19. The method of claim 18, wherein the third refresh schedule subjects the first memory page to refresh operations at least as frequently as the second refresh schedule corresponding to the second subset.

20. The method of claim 19, wherein the first refresh schedule corresponds to never refreshing the first subset.

21. The method of claim 15, wherein the third refresh schedule corresponds to repeatedly refreshing the first memory page to remove imprints in the first memory page.

22. The method of claim 14, further comprising: merging data in memory pages corresponding to the first subset into physically contiguous memory pages within the plurality of memory pages.

23. A memory system, comprising:

a host device; and

a memory device including a controller and a main memory operably coupled to the controller, the main memory having a memory area comprising a plurality of memory pages,

wherein the controller is configured to:

tracking a first subset of the plurality of memory pages having a first refresh schedule and a second subset of the plurality of memory pages having a second refresh schedule different from the first refresh schedule,

refreshing the first subset of memory pages according to the first refresh schedule, an

Refreshing the second subset of memory pages according to the second refresh schedule.

24. The memory system of claim 23, wherein the controller is configured to track the first subset and the second subset in one or more refresh schedules stored on at least one of the main memory, the controller, and the host device.

25. The memory system of claim 24, wherein the controller is further configured to switch a first memory page from the first subset to the second subset.

26. The memory system of claim 25, wherein at least one of the main memory, the controller, and the host device is configured to instruct the controller to update the first refresh schedule corresponding to the first memory page to a third refresh schedule in the one or more refresh schedules.

27. The memory system of claim 26, wherein the third refresh schedule is different from the first refresh schedule and the second refresh schedule.

28. The memory system of claim 23, wherein the first subset is a contiguous range of memory pages and the controller is configured to track the first subset using an identifier of a first page of the range and an identifier of a last page of the range.

29. The memory system of claim 23, wherein the first subset is a contiguous range of memory pages and the controller is configured to track the first subset using an identifier of a first page of the range and a length of the range.

30. The memory system of claim 23, wherein the memory area is a ferroelectric memory.

Technical Field

The disclosed embodiments relate to memory devices and systems, and in particular, to memory devices with selective page refresh.

Background

Memory devices are often provided in computers or other electronic devices as internal semiconductor integrated circuits and/or as external removable devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires an applied power source to retain its data and can be used in a variety of technologies including Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM), among others. Volatile memory stores information that is frequently accessed by a memory controller during operation, and it typically exhibits faster read and/or write times than non-volatile memory. In contrast, a nonvolatile memory can retain its stored data even if power is not externally supplied. Non-volatile memory may also be used in various technologies including flash memory (e.g., NAND and NOR), phase change memory ((PCM), Resistive Random Access Memory (RRAM), ferroelectric random access memory (FeRAM or FRAM), among others.

Disadvantages of some non-volatile memory technologies (e.g., ferroelectric memory, polymer memory, etc.) are: these techniques suffer from imprint when their memory cells retain the same data state for a long time. When a data state is impressed into a memory cell, the memory cell tends to preserve the data state even if the memory controller attempts to erase the memory cell and/or program it to a different data state. Thus, these imprint-prone memory technologies must be periodically refreshed (e.g., by changing the polarity and/or data state of the memory cells) to prevent the data state from being imprinted into the memory cells. However, the number of refreshes required for these non-volatile memory technologies can consume a significant amount of energy and significant amount of time for the memory, especially as memory technologies become more intensive.

Drawings

FIG. 1 is a block diagram of a system having a memory device configured according to an embodiment of the invention.

FIGS. 2A and 2B are tables illustrating selective page-based refresh, according to several embodiments of the invention.

Figures 3A and 3B are tables illustrating selective page-based refresh according to several embodiments of the present disclosure.

Fig. 4A-4B are flow diagrams illustrating a method of operating a memory device, according to an embodiment of the invention.

Figures 5A-5B are flow diagrams illustrating additional methods of operating a memory device according to embodiments of the invention.

FIG. 6 is a schematic diagram of a system including a memory device, according to an embodiment of the invention.

Detailed Description

As will be described in greater detail below, the present invention relates to memory devices and related systems having selective page-based refresh. However, it should be understood by those skilled in the art that the present invention may have additional embodiments and that the present invention may be practiced without several of the details of the embodiments that will be described below with reference to FIGS. 1-6. In the embodiments that will be described below, the memory device is described primarily in the context of a device incorporating a ferroelectric storage medium. However, memory devices configured according to other embodiments of the invention may include other types of storage media, such as NAND, NOR, PCM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (EROM), electrically erasable programmable ROM (EEROM), and other storage media including volatile storage media.

One embodiment of the invention is a memory device comprising a controller and a main memory. The main memory includes a memory area having a plurality of memory pages. The controller is operably coupled to the main memory and configured to track a first subset and a second subset of the plurality of memory pages in the main memory having a first impression refresh schedule and a second impression refresh schedule, respectively. The controller is further configured to refresh the first subset and the second subset of the plurality of memory pages according to the corresponding first and second impression refresh schedules.

The impression refresh schedule may be used to indicate how often a memory page is refreshed to counteract the impression effect. In this manner, the energy consumed and the effective time that a memory device spends refreshing memory pages within the memory device may be managed according to the classification and/or type of memory page (e.g., refresh, no refresh, very frequent refresh, occasional refresh, etc.).

FIG. 1 is a block diagram of a system 101 having a memory device 100 configured according to an embodiment of the invention. As shown in the figure, the memory device 100 includes a main memory 102 and a controller 106 that operably couples the main memory 102 to a host device 108, such as an upstream Central Processing Unit (CPU). The main memory 102 includes a plurality of memory areas or memory units 120, which includes a plurality of memory units 122. The memory units 120 may be individual memory dies, memory planes in a single memory die, a stack of memory dies vertically connected with through-silicon vias (TSVs), or the like. In one embodiment, each of the memory units 120 may be formed from a semiconductor die and arranged in a single device package (not shown) with other memory unit dies. In other embodiments, one or more of the memory units 120 may be co-located on a single die and/or distributed in multiple device packages. Memory cells 122 can include, for example, ferroelectric and/or other suitable storage elements (e.g., capacitors, phase changes, magnetoresistances, etc.) configured to permanently or semi-permanently store data. The main memory 102 and/or individual memory units 120 may also include other circuit components (not shown), such as memory subsystems, for accessing and/or programming (e.g., writing) the memory units 122 and other functionality, such as for processing information and/or communicating with the controller 106, such as multiplexers, decoders, buffers, read/write drivers, address registers, data out/data in registers, and so forth.

Memory cells 122 may be arranged in rows 124 (e.g., each corresponding to a word line) and columns 126 (e.g., each corresponding to a bit line). Each word line 124 may span one or more pages of memory depending on the number of data states that the memory cells 122 of the word line 124 are configured to store. For example, in the illustrated embodiment, memory cells 122 may be ferroelectric memory cells each configured to store one of two data states, and a single word line 124 may span a single memory page. In other embodiments in which the memory cells are configured to store more than two data states (e.g., 4, 8, or more data states), a single word line 124 may span two or more pages of memory. In these and other embodiments, the memory pages may be interleaved such that a word line 124 comprised of memory cells 122 configured to store one of two data states in each cell may span both memory pages. For example, the word lines 124 may be arranged in a "parity bit line architecture" in which, for example, all memory cells 122 in odd columns 126 of a single word line 124 are grouped into a first memory page, while all memory cells 122 in even columns 126 of the same word line 124 are grouped into a second memory page. When a parity bit line architecture is used to store more data states in the word lines 124 of the memory cells 122 in each cell, the number of memory pages per word line 124 may be higher (e.g., 4, 6, 8, etc.).

In other embodiments, memory cells 122 may be arranged in different groups and/or hierarchical types than shown in the illustrated embodiment. Moreover, although a particular number of memory cells, rows, columns, blocks, and memory cells are shown for illustration in the illustrated embodiments, in other embodiments the number of memory cells, rows, columns, blocks, and memory cells can vary, and can have a scale that is greater than or less than the scale shown in the illustrated embodiments. For example, in some embodiments, memory device 100 may include only 1 memory cell 120. Alternatively, memory device 100 may include 2, 3, 4, 8, 10, or more (e.g., 16, 12, 64, or more) memory cells 120. Although memory units 120 are shown in fig. 1 to each include two memory blocks 128, in other embodiments, each memory unit 120 may include 1, 3, 4, 8, or more (e.g., 16, 32, 64, 100, 128, 256, or more) memory blocks 128. In some embodiments, each memory block 128 may include, for example, 2¹⁵A memory page, and each memory page within a block may comprise, for example, 2¹²And a memory unit 122.

The controller 106 may be a microcontroller, special purpose logic circuitry (e.g., a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), etc.), or other suitable processor. The controller 106 may include a processor 130 configured to execute instructions in memory. In the illustrated example, the memory of the controller 106 includes embedded memory 132 configured to store various processes, logic flows, and routines for controlling the operation of the memory device 100, including managing the main memory 102 and handling communications between the memory device 200 and the host device 108. In some embodiments, the embedded memory 132 may include memory registers that store, for example, memory pointers, fetch data, and so forth. The embedded memory 132 may also include Read Only Memory (ROM) for storing microcode. Although the exemplary memory device 100 illustrated in FIG. 1 includes a controller 106, in another embodiment of the present invention, the memory device may not include a controller, but may instead rely on external control (e.g., provided by an external host or a processor or controller separate from the memory device).

In operation, the controller 106 may directly read, write, or otherwise program (e.g., erase) various memory areas of the main memory 102, such as by reading from and/or writing to groups of memory pages and/or memory blocks 128. In FRAM-based and other memory types, a write operation typically includes programming memory cells 122 in a selected memory page with a particular polarity that represents a data value, such as a string of data bits each having a value of logic 0 or logic 1. An erase operation is similar to a write operation, except that the erase operation reprograms the memory cells 122 to a particular polarity and data state (e.g., a logic 0).

The controller 106 communicates with the host device 108 via a host-device interface 115. In some embodiments, host device 108 and controller 106 may communicate via a serial interface (e.g., serial attached scsi (sas), serial AT attached (SATA) interface, peripheral component interconnect express (PCIe)) or other suitable interface (e.g., parallel interface). Host device 108 may send various requests (in the form of, for example, packets or packet streams) to controller 106. The request may include a command to write, erase, return information, and/or perform a particular operation, such as a TRIM operation.

As discussed above, memory cell 122 is subject to imprint when memory cell 122 remains in the same polarity and/or data state for a long period of time. To counteract this effect, the controller 106 and/or the main memory 102 may periodically refresh the memory cells 122 (e.g., by reversing their polarity or otherwise changing their data state). However, the number of refreshes required consumes a significant amount of energy and significant amount of time of the memory device 100, especially as the number of memory cells 122 within the main memory 102 increases. Furthermore, all memory cells 122 within the main memory 102 need not be refreshed at the same rate. For example, a number of memory units 122 within the main memory 102 may be broken down into memory pages that are marked as read-only pages to prevent the controller 106, the main memory 102, and/or the host device 108 from writing to memory units 122 in those memory pages. These read-only memory pages typically include code pages, cache file pages, and other memory pages that store data that is not expected to be modified during the lifetime of the memory device 100. Because there is no concern about imprinting in these memory pages (e.g., because it is not expected or difficult to change the data in these cells would not cause problems), the memory cells 122 in these pages need not be refreshed periodically or as frequently as the memory cells 122 in memory pages that contain data that is frequently read, erased, and/or programmed (or even all in some embodiments). Further and as will be described below, the controller 106, the main memory 102 (e.g., a memory subsystem of the main memory), and/or the host device 108 may also convert memory pages of one classification and/or type of memory page to memory pages of another classification and/or type. Accordingly, it is desirable to track memory pages that have different imprinted refresh schedules and that require non-aggressive refresh schedules to reduce the energy and effective time consumed by memory refresh operations.

As will be described in more detail below, system 101 utilizes table 144 to track memory pages having different imprint refresh schedules (e.g., on a per memory die, memory unit 120, and/or memory block 128 basis). In the embodiment illustrated in FIG. 1, the table 144 is stored in the embedded memory 132 of the controller 106. In other embodiments, the table 144 may be stored at other locations (e.g., in addition to or instead of storing the table 144 on the embedded memory 132), such as on the main memory 102 and/or the host device 108.

FIGS. 2A and 2B are tables illustrating selective page-based refresh according to an embodiment of the invention. Referring to FIG. 2A, the memory device 100 (FIG. 1) and/or the host device 108 (FIG. 1) track a range of memory pages that have been marked as non-refreshed memory pages in the imprinted refresh schedule 244 a. As shown in the figure, the imprinted refresh schedule 244a tracks memory pages in m memory blocks, such as memory block 128 (FIG. 1), within n memory regions, such as memory die and/or memory cells 120 (FIG. 1). In the illustrated embodiment, each memory block includes 64 memory pages. In other embodiments, the memory block may include a different number of memory pages (e.g., 10, 16, 32, 100, 128, 256, 512, 1048 memory pages).

The imprinted refresh schedule 244a stores one or more ranges of memory pages in each memory block that need not be refreshed as frequently as other memory pages. For example, the entry 251 in the imprinted refresh schedule 244a corresponds to memory block 1 of memory region 1. In entry 251, memory pages 39 through 54 have been marked as non-refreshed memory pages. Thus, the memory cells within memory pages 39-54 do not need to be refreshed as frequently as the memory cells within refresh memory pages 1-38 and 55-64 within memory block 1. Similarly, a plurality of non-refresh areas are recorded in the entry 253, the entry 253 corresponding to the memory block 3 within the memory area 1. Thus, memory pages 16-24 and memory pages 43-47 in memory block 3 have been marked as non-refreshed memory pages, and the memory cells in these non-refreshed memory pages do not require frequent refresh operations. In contrast, the entry 252 corresponding to memory block 2 within memory area 1 is illustrated as an unrecorded, non-refreshed area. Thus, all memory pages within memory block 2 are not marked as non-refreshed memory pages. Thus, memory pages 1-64 of memory block 2 are refresh memory pages and undergo frequent and periodic refresh operations.

As will be described in further detail below, the memory device 100 and/or the host device 108 may employ algorithms to place memory pages of the same classification or type (e.g., refresh and/or no refresh) in physically contiguous locations of the memory, thereby limiting the number of ranges of memory pages that need to be stored in the imprinted refresh schedule 244a and the number of memory pages in each range of memory pages. Limiting the number of non-refresh regions stored in the imprinted refresh schedule 244a may minimize the amount of memory required to store the imprinted refresh schedule 244a, which may allow the imprinted refresh schedule 244a to be stored at locations with strict memory constraints. For example, the entries 255 of the imprinted refresh schedule 244a include a non-refresh region covering the same number of memory pages (i.e., 14 memory pages total) as the entries 253 of the imprinted refresh schedule 244 a. However, the algorithm has consolidated the non-refreshed memory pages into the first 14 memory pages of memory block m-2, requiring only one non-refreshed region in entry 255 as compared to two non-refreshed regions in entry 253. Thus, the amount of memory for entry 255 is less than the amount of memory for entry 253. In other embodiments, the algorithm may consolidate non-refreshed memory pages into other physically contiguous locations of memory. For example, the algorithm may consolidate the non-refresh memory pages into physically contiguous memory pages within the memory block and/or physically contiguous memory pages at the end of the memory block that imprints the refresh schedule 244a, as illustrated in entries 256 and 257, respectively.

Referring now to FIG. 2B, the memory device 100 and/or the host device 108 tracks a range of memory pages that have been marked as non-refreshed memory pages in the imprinted refresh schedule 244B. The imprinted refresh schedule 244b is similar to the imprinted refresh schedule 244a, except that the imprinted refresh schedule 244b does not record the end page of each non-refreshed region. Instead, the impression refresh schedule 244b records the start page and length of each non-refreshed region. For example, the non-refresh region recorded in the entry 271 of the imprinted refresh schedule 244B in FIG. 2B is the same as the non-refresh region recorded in the entry 251 of the imprinted refresh schedule 244a in FIG. 2A. However, the imprinted refresh schedule 244b records the length of the non-refresh region (i.e., 16 memory pages starting from memory page 39) rather than the ending page of the memory region (i.e., memory page 54) recorded in the imprinted refresh schedule 244 a.

FIGS. 3A and 3B are tables 344a and 344B, respectively, illustrating alternative embodiments of selective page-based refresh in accordance with the present invention. In the illustrated embodiment, the memory device 100 and/or the host device 108 track the range of memory pages that are not marked as non-refreshed memory pages in the imprinted refresh schedules 344a and 344 b. Thus, the imprinted refresh schedules 344a and 344B (fig. 3A and 3B) are similar to the imprinted refresh schedules 244a and 244B (fig. 2A and 2B), respectively, except that the imprinted refresh schedules 344a and 344B track memory pages that must be frequently refreshed (e.g., refreshed memory pages) rather than memory pages that do not require frequent refreshing (e.g., non-refreshed memory pages). As shown in the entries 355-357 of FIG. 3A and the entries 375-377 of FIG. 3B, the imprinted refresh schedules 344a and 344B may also benefit from consolidating non-refreshed memory pages into physically contiguous memory locations such that the amount of memory required to store the imprinted refresh schedules 344a and 344B is minimal, which allows the imprinted refresh schedules 344a and 344B to be stored at locations with strict memory constraints.

Although not shown in the embodiment illustrated in fig. 2A-3B, in other embodiments, the imprinted refresh schedules 244a, 244B, 344a, and/or 344B may include additional columns and/or information. For example, the imprinted refresh schedules 244a, 244b, 344a, and/or 344b may include additional columns and/or information related to individual memory pages, non-refreshed regions, and/or imprinted refresh schedules and/or imprinted refresh durations for refreshed regions. In other words, depending on the classification or type of the memory page (e.g., refresh, no refresh, very frequent refresh, occasional refresh, etc.) and/or other parameters (e.g., physical location of the memory page in main memory 102, flags indicating that the memory page is free and available for real-time use, etc.), the memory device 100 (fig. 1) and/or the host device 108 (fig. 1) may assign various embossed refresh schedules and durations to the memory page and/or a region of the memory page. Examples of impression refresh schedules for non-refreshed memory pages in accordance with the present disclosure include refreshing non-refreshed memory pages at fractions of the refresh frequency of refreshing memory pages (e.g., 1/10, 1/4, 1/3, 1/2, 2/3, 3/4, 9/10) to mitigate impression effects. In other embodiments, the imprinted refresh schedule of non-refreshed memory pages does not allow for refresh operations to be performed on the corresponding non-refreshed memory pages at the same time. In contrast, examples of non-refreshed or other memory pages converted to memory pages of another classification or type according to the present disclosure include refreshing these memory pages at least as frequently as refreshing the refreshed memory pages and/or at multiples (e.g., 1.5 times, 2 times, 3 times, 5 times) of the refresh frequency of refreshing the memory pages to mitigate the effects of imprint. Further, in some embodiments, the frequency of refresh operations scheduled for a memory page may be modified (e.g., increased and/or decreased) and/or updated in the corresponding imprinted refresh schedule. For example, the frequency of refresh operations of a memory page may be increased, e.g., when unwanted imprint effects are found in the memory cells of the memory page, and/or the frequency of refresh operations of a memory page may be decreased, e.g., to accommodate system requirements (e.g., to reduce the energy and/or effective time consumed by memory refresh operations). In other embodiments, the memory device 100 and/or the host device 108 may process the impression refresh schedule exceptions stored in the impression refresh schedule without modifying or updating the impression refresh schedule stored in the impression refresh schedule.

Furthermore, although the embodiment illustrated in fig. 2A-3B shows only two classifications and types of memory pages (i.e., refreshed memory pages and non-refreshed memory pages), in other embodiments, one or more imprinted refresh schedules (e.g., imprinted refresh schedules 244a, 244B, 344a, and/or 344B) may be used to track memory pages of other classifications and/or types (e.g., very frequent refreshes, occasional refreshes, etc.) in addition to or in place of refreshed memory pages and/or non-refreshed memory pages. For example, in some embodiments, a single imprinted refresh schedule may be used to track a single class or type of memory page, such that there are as many imprinted refresh schedules as there are classes and types of memory pages tracked. In other embodiments, a single imprinted refresh schedule may be used to track all classes and types of memory pages so that there is only one imprinted refresh schedule for the memory device. In other embodiments, one or more imprinted refresh schedules may be used to track one or more classifications and/or types of memory pages in a specified memory region (e.g., memory block, die, and/or cell) of a memory device.

Figures 4-5B are flow diagrams illustrating routines 460, 470, 580a, and 580B, respectively, for operating a memory device, according to embodiments of the invention. Routines 460, 470, 580a, and 580b may be executed by, for example, controller 106 (fig. 1), main memory 102 (fig. 1) (e.g., a subset of memory of main memory 102), and/or host device 108 (fig. 1).

Referring to FIG. 4A, the routine 460 determines whether to refresh a memory page in a memory region by referencing an imprinted refresh schedule stored, for example, on the main memory 102 (FIG. 1), the controller 106 (FIG. 1), and/or the host device 108 (FIG. 1). In some embodiments, the imprinted refresh schedule may be similar to the imprinted refresh schedule described in fig. 2A, 2B, 3A, and/or 3B. In block 461, the routine 460 begins by tracking a subset of memory pages in the imprinted refresh schedule based at least on the classification and/or type (e.g., refresh, no refresh, occasional refresh, etc.) of the memory pages within the subset of memory pages within the memory region having the one or more imprinted refresh schedules. For example, in some embodiments, routine 460 may assign an embossed refresh schedule that specifies refresh operations (e.g., for refreshing memory pages) at periodic or regularly scheduled intervals, automatically specifies refresh operations after a particular event has occurred (e.g., after a specified number of read, write, erase, or other system operations have occurred) or after a predetermined amount of time has elapsed (e.g., for occasionally refreshing memory pages), and/or does not specify refresh operations at all (e.g., for non-refreshed memory pages). In block 462, routine 460 may continue to refresh the subset of memory pages according to the one or more imprinted refresh schedules for the subset of memory pages.

Referring now to fig. 4B, routine 470 may update one or more impression refresh schedules for a subset of memory pages according to instructions received from, for example, controller 106 and/or host device 108. In some embodiments, the instruction may be prompted by a user. In other embodiments, the instructions may be automatic. For example, the controller 106 and/or the host device 108 may send instructions to automatically update one or more impression refresh schedules after a particular event occurs (e.g., after a particular number of reads, writes, erases, or other system operations have been performed on a memory page), after a memory page has not been accessed for a predetermined amount of time, and/or after unwanted impression effects have been found in one or more memory cells of a memory page. In block 471, routine 470 may receive an embossed refresh instruction containing, for example, one or more logical addresses related to memory pages within the subset of memory pages.

In block 472, the routine 470 may update and/or modify one or more impression refresh schedules corresponding to the memory pages involved in the instruction, according to the received instruction. For example, the received instructions may direct the routine 470 to change one or more imprinted refresh schedules stored in the imprinted refresh schedule by increasing and/or decreasing the frequency and/or duration of refresh operations on the memory pages involved (e.g., when converting the memory pages involved into memory pages of different classifications and/or types, as refreshed with reference to fig. 5A and 5B below; when useless imprint effects are found in the memory cells of the memory pages involved; to accommodate system requirements; and/or according to power scheduling of the memory device). In these and other embodiments, the received instructions may direct routine 470 to process one or more imprinted refresh schedule exceptions stored in the imprinted refresh schedule without otherwise modifying the one or more imprinted refresh schedules. For example, the received instructions may direct the routine 470 to subject the memory page in question to a temporary aggressive refresh operation (e.g., when the routine 470 expects to convert the memory page in question to a memory page of a different classification and/or type and/or find undesirable imprint effects in the memory cells of the memory page in question).

Referring now to fig. 5A-5B, routines 580a and 580B may consolidate non-refreshed and/or other sorted or types of memory pages into physically contiguous locations of memory (e.g., to minimize the memory space required to store an imprinted refresh schedule). Routine 580a may be executed to convert the memory page to a non-refreshed memory page. In contrast, routine 580b may be executed to convert a memory page (e.g., a non-refreshed memory page) to other classifications and/or types of memory pages.

Referring now to FIG. 5A, routine 580a begins by receiving an instruction to convert one or more memory pages (e.g., refreshed and/or other sorted and/or types of memory pages) to non-refreshed memory pages (block 581 a). In block 582a, the routine 580a may retrieve a corresponding non-refresh region (e.g., of selected memory blocks, memory dies, and/or memory cells) from an imprinted refresh schedule stored on, for example, the controller 106, the main memory 102, and/or the host device 108. The routine 580a continues by determining whether one or more memory pages are located at locations that are physically connected to the corresponding non-refresh zone (decision block 583 a). If the routine 580a determines that one or more memory pages are located at locations that are physically connected to the corresponding non-refreshed region, the routine 580a may convert the one or more memory pages to non-refreshed memory pages (block 586a) and may continue with block 587 a. In some embodiments, the routine 580a may return a success message before continuing with block 587 a.

On the other hand, if the routine 580a determines that one or more memory pages are not located at a location that is physically contiguous with the corresponding non-refresh region (decision block 583a), the routine 580a may reposition, rearrange, and/or merge data stored in the one or more memory pages and/or the corresponding non-refresh region into physically contiguous memory locations (block 585 a). In some embodiments, routine 580a may convert a non-refreshed memory page in a corresponding non-refreshed region into a refreshed and/or other classification and/or type of memory page and/or vice versa when relocating data stored in a non-refreshed memory page of a non-refreshed region. After routine 580a repositions, rearranges, and/or consolidates data stored in one or more memory pages and/or non-refreshed memory pages of corresponding non-refreshed regions into physically contiguous memory locations, routine 580a may convert the one or more memory pages and/or the memory pages containing their repositioned data into non-refreshed memory pages (block 586a) and may continue with block 587 a. In some embodiments, the routine 580a may return a success message before continuing with block 587 a.

Referring now to FIG. 5B, routine 580B is similar to routine 580a of FIG. 5A, with a few exceptions. As refreshed as above, routine 580b may be executed to convert a memory page (e.g., a non-refreshed memory page) to a refreshed and/or other classification and/or type of memory page. Routine 580b begins by receiving an instruction to convert one or more non-refreshed memory pages into other classifications and/or types of memory pages (block 581 a). In block 582b, the routine 580b retrieves the corresponding non-refresh region from the imprinted refresh schedule stored, for example, on the main memory 102, the controller 106, and/or the host device 108.

In decision block 583b, routine 580b determines whether one or more non-refreshed memory pages are physically connected to a corresponding non-refreshed region. For example, in some embodiments, routine 583b may determine that one or more non-refreshed memory pages have not previously been consolidated into physically contiguous memory locations relative to a corresponding non-refreshed area and, thus, are not physically contiguous with the corresponding non-refreshed area. In other embodiments, the routine 583b may determine whether the one or more non-refreshed memory pages are physically connected with the corresponding non-refreshed region by determining whether the one or more non-refreshed memory pages span the entire length of the corresponding non-refreshed region. If the one or more memory pages do not span the entire length of the corresponding non-refreshed region, routine 580b may determine that the one or more memory pages are physically connected with the corresponding non-refreshed region. On the other hand, if the one or more memory pages span the entire length of the corresponding non-refresh region, routine 580b may determine that the one or more memory pages are not physically connected with the corresponding non-refresh region.

If routine 580b determines that one or more non-refreshed memory pages are not located at locations physically connected to the corresponding non-refreshed region, routine 580b may convert the one or more non-refreshed memory pages to memory pages of other classifications and/or types (block 586b) and may continue with block 587 b. In some embodiments, routine 580b may return a success message before continuing with block 587 b. On the other hand, if routine 580b determines that one or more non-refreshed memory pages are located at locations that are physically contiguous with the corresponding non-refreshed region (decision block 583b), routine 580b may continue to determine that one or more non-refreshed memory pages are located at the beginning (e.g., a starting memory page) or the end (e.g., an ending memory page) of the corresponding non-refreshed region (decision block 584 b). If routine 580b determines that the one or more non-refreshed memory pages are the start and/or end of corresponding non-refreshed regions, routine 580b may convert the one or more non-refreshed memory pages to memory pages of other classifications and/or types (block 586b) and may continue with block 587 b. In some embodiments, routine 580b may return a success message before continuing with block 587 b.

If routine 580b determines that one or more non-refreshed memory pages are not located at the beginning (e.g., the start page) and/or the end (e.g., the end page) of the corresponding non-refreshed region (e.g., routine 580b determines that one or more non-refreshed memory pages are located at an internal non-refreshed memory page of the corresponding non-refreshed region) (decision block 584b), routine 580b may reposition, rearrange, and/or merge data stored in the one or more non-refreshed memory pages and/or the non-refreshed memory pages of the corresponding non-refreshed region into physically contiguous memory locations (block 585 b). In some embodiments, routine 580b may convert non-refreshed memory pages in a corresponding non-refreshed region into memory pages of other classifications and/or types and/or vice versa when relocating data stored in non-refreshed memory pages of non-refreshed regions. After routine 580b repositions, rearranges, and/or merges data stored in one or more non-refreshed memory pages and/or non-refreshed memory pages of corresponding non-refreshed regions into physically contiguous memory locations, routine 580b may convert the one or more non-refreshed memory pages and/or the memory pages containing their repositioning data into other classifications and/or types of memory pages (block 586b) and may continue with block 587 b. In some embodiments, routine 580b may return a success message before continuing with block 587 b.

FIG. 6 is a schematic diagram of a system including a memory device, according to an embodiment of the invention. Any of the foregoing memory devices described above with reference to fig. 1-5B may be incorporated into any of a variety of larger and/or more complex systems, of which the system 690 shown schematically in fig. 6 is a representative example. The system 690 may include a semiconductor device assembly 600, a power supply 692, a driver 694, a processor 696, and/or other subsystems and components 698. The semiconductor device assembly 600 may include features substantially similar to those of the memory devices described above with reference to fig. 1-5B and, thus, may include various features that are selectively page refresh based. The resulting system 690 may perform any of a variety of functions, such as memory storage, data processing, and/or other suitable functions. Thus, representative systems 690 may include, but are not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of system 690 may be housed in a single unit or distributed across multiple interconnected units (e.g., over a communications network). The components of system 690 may also include remote devices and any of a variety of computer-readable media.

From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the invention. For example, although not shown in FIG. 5B, in some embodiments, routine 580B may relocate, rearrange, and/or merge data in other classifications and/or types of memory pages (e.g., refresh memory pages, occasionally refresh memory pages, etc.) into physically contiguous memory locations relative to regions of the corresponding classifications and/or types of memory pages. Thereby, routine 580b may convert the memory page to other classifications and/or types of memory pages. In addition, particular aspects of the new technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. Moreover, while advantages associated with particular embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and all embodiments that do not necessarily fall within the scope of the invention need not exhibit such advantages. Accordingly, the disclosure and associated techniques may encompass other embodiments not explicitly shown or described.