阅读说明：本技术 存储器控制器 (Memory controller ) 是由 G·布里亚 于 2019-08-16 设计创作，主要内容包括：本公开涉及存储器控制器。一种设备包括可填充有存储器位置的内容的第一缓冲器和第二缓冲器。选择电路被配置为在同时填充缓冲器与顺序填充缓冲器之间选择填充模式。在一些示例中,该设备可以是包括非易失性存储器和处理器的片上系统。(The present disclosure relates to memory controllers. An apparatus includes a first buffer and a second buffer that may be filled with contents of memory locations. The selection circuit is configured to select a filling mode between simultaneously filling the buffers and sequentially filling the buffers. In some examples, the device may be a system on a chip including a non-volatile memory and a processor.)

1. An apparatus, comprising:

two buffers that can be filled with the contents of the memory locations; and

a selection circuit configured to select a filling mode between simultaneous filling of the buffers and sequential filling of the buffers.

2. The apparatus of claim 1, wherein the contents of each memory location comprise a plurality of data bits, each of the buffers configured to be filled with the plurality of data bits simultaneously.

3. The apparatus of claim 2, comprising a driver configured to send N data bits over a bus having N parallel lines, N being a real number greater than 1.

4. The apparatus of claim 3, wherein the driver comprises a multiplexer.

5. The apparatus of claim 1, wherein the two buffers are fillable with respective contents of first and second memory locations having alternating addresses.

6. The apparatus of claim 5, further comprising two additional buffers sequentially fillable with addresses of respective contents of the first and second memory locations.

7. The apparatus of claim 1, wherein the apparatus is configured such that the sequential filling of the buffer comprises filling using contents of contiguous memory locations.

8. An apparatus, comprising:

a first buffer;

a second buffer;

a first bus having a bus width, the first bus coupled to the first buffer and the second buffer; and

a second bus having the bus width, the second bus coupled to the second buffer and not coupled to the first buffer;

wherein the device is configurable between a first transport configuration and a second transport configuration;

wherein in the first transmission configuration, data is simultaneously transmitted to or from the first buffer using the first bus and to or from the second buffer using the second bus; and

wherein in the second transmission configuration data is transmitted to or from the first buffer using the first bus and then data is transmitted to or from the second buffer using the first bus.

9. The apparatus of claim 8, further comprising a processor coupled to the first bus and the second bus.

10. The apparatus of claim 9, further comprising a non-volatile memory, wherein the first buffer and the second buffer are located between the non-volatile memory and the processor.

11. The apparatus of claim 8, further comprising a non-volatile memory coupled to the first buffer and the second buffer.

12. The device of claim 11, wherein the first buffer and the second buffer are configured to store data from memory locations of the non-volatile memory, the device further comprising an additional buffer configured to store addresses of the memory locations.

13. A method of operating a memory coupled to a bus that is configurable between a large bus size configuration and a small bus size configuration, the method comprising:

configuring the bus to the large bus size configuration;

performing a first transfer operation by transferring data simultaneously to a first buffer and a second buffer across the bus configured with a large bus size;

configuring the bus to the small bus size configuration after performing the first transfer operation; and

performing a second transfer operation by first transferring data to the first buffer across the bus configured with a small bus size and then transferring data to the second buffer across the bus configured with the small bus size.

14. The method of claim 13, wherein the large bus size is twice as large as the small bus size.

15. The method of claim 13, wherein performing the first transfer operation and performing the second transfer operation each comprise: the first buffer and the second buffer are filled with data from a first memory location and a second memory location having alternating addresses.

16. The method of claim 13, wherein performing the first transfer operation and performing the second transfer operation each comprise: transmitting data from the location of the memory, the method further comprising storing an address of the location of the memory in an additional buffer.

17. The method of claim 16, further comprising verifying that a request matches the address stored in the additional buffer.

18. The method of claim 13, further comprising:

receiving a read request from a processor, the read request comprising an address of a non-volatile memory coupled to the first buffer and the second buffer;

comparing addresses of the data stored in the first buffer and the second buffer with the address included in the read request;

transferring data from the first buffer and the second buffer using the first transfer operation or the second transfer operation when the address of the data stored in the first buffer and the second buffer matches the address included in the read request; and

when the address of the data stored in the first buffer and the second buffer does not match the address included in the read request, first transferring data from the nonvolatile memory to the first buffer and the second buffer, and then transferring data from the first buffer and the second buffer using the first transfer operation or the second transfer operation.

19. The method of claim 13, wherein performing the first transmission operation comprises: filling the first buffer and the second buffer with contents of contiguous memory locations.

20. The method of claim 13, wherein performing the second transfer operation comprises: filling the first buffer and the second buffer with contents of contiguous memory locations.

Technical Field

The present disclosure relates generally to electronic circuits, and more particularly to devices that receive the contents of memory locations, such as memory controllers.

Background

Memory controllers are commonly used between memory and circuitry that can access the memory, for example, in electronic integrated circuit chips.

Disclosure of Invention

Drawings

FIG. 1 partially and schematically illustrates a chip including one embodiment of a device that receives the contents of a memory location;

FIG. 2 schematically shows the steps of one embodiment of a method implemented by the apparatus of FIG. 1;

FIG. 3 schematically illustrates one example of an implementation of the method of FIG. 2 by a chip of the type in FIG. 1;

FIG. 4 schematically illustrates steps of the method of FIG. 2 in the example of FIG. 3;

FIG. 5 partially and schematically illustrates a chip including one embodiment of an apparatus to receive contents of a memory location;

FIG. 6 schematically illustrates a portion of the apparatus of FIG. 5; and

fig. 7 schematically shows another part of the device of fig. 5.

Embodiments may overcome all or part of the disadvantages of known devices that receive the contents of a memory location, such as a memory controller.

Accordingly, one embodiment provides an apparatus comprising two buffers that can be filled with the contents of memory locations, and a selector of a filling pattern between simultaneous filling of the buffers and sequential filling of the buffers.

According to one embodiment, the content of each location comprises a plurality of data segments, preferably 2 data segments. Each of the buffers is configured to be simultaneously filled with a plurality of data segments.

According to one embodiment, the apparatus includes circuitry for transmitting one of the data segments over a bus of the same size as the data.

According to one embodiment, both buffers may be filled with respective contents of a first location and a second location having alternating addresses (preferably logical).

According to one embodiment, the device further comprises two additional buffers sequentially fillable with addresses of respective contents of the first memory location and the second memory location.

According to one embodiment, the device is configured such that the sequential filling of the buffer is a filling using the contents of consecutive memory locations.

Another embodiment provides an electronic chip comprising the apparatus as described above.

Another embodiment provides a method comprising a first operation and a second operation to fill two buffers with memory location contents. The buffers are filled simultaneously at a first fill and sequentially at a second fill.

According to one embodiment, the content of each location comprises a plurality of data segments, preferably 2 data segments. Each of the buffers is filled using a plurality of data segments simultaneously during a first fill operation and a second fill operation.

According to one embodiment, the method includes the step of transmitting one of the data segments over a bus of the same size as the data.

According to one embodiment, the two buffers are filled with a first location and a second location, respectively, having alternating addresses (preferably logical).

According to one embodiment, the method comprises the step of storing one of the addresses of the first location and the second location in an additional buffer.

According to one embodiment, the method includes the step of verifying equality between the request address and the address stored in the storing step.

According to one embodiment, the presence of the step of reading out the content of one of the locations is a function of the result of the equality verification step.

According to one embodiment, at the first fill, the buffer is filled with the respective contents of the contiguous memory locations.

The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.