阅读说明：本技术 分布式块存储低延迟控制方法、系统及设备 (Distributed block storage low-delay control method, system and equipment ) 是由 王刚 于 2019-10-21 设计创作，主要内容包括：本发明公开了分布式块存储低延迟控制方法、系统及设备,方法包括以下步骤：获取用户设备驱动程序的应用编程接口,应用编程接口与用户设备之间发送和接收数据包,并形成数据描述符环且包括发送数据描述符环和接收数据描述符环；轮询逻辑核心通过应用编程接口轮询一个或多个用户设备端口的接收数据描述符环并通过接收数据描述符环发送数据包至处理逻辑核心；处理逻辑核心根据策略规则接收数据包并进行处理；通过应用编程接口将处理后的数据包在用户设备端口的发送数据描述符环上进行传输。通过采用轮询模式代替中断模式的技术手段,克服现有技术中存在由于中断导致IO延迟严重的技术问题,避免了中断带来的延时和开销,提高端口处理效率且降低端口的延迟。(The invention discloses a distributed block storage low-delay control method, a system and equipment, wherein the method comprises the following steps: acquiring an application programming interface of a user equipment driver, transmitting and receiving data packets between the application programming interface and user equipment, and forming a data descriptor ring and comprising a transmitting data descriptor ring and a receiving data descriptor ring; the polling logic core polls a received data descriptor ring of one or more user equipment ports through the application programming interface and sends a data packet to the processing logic core through the received data descriptor ring; the processing logic core receives and processes the data packet according to the strategy rule; and transmitting the processed data packet on a sending data descriptor ring of the user equipment port through the application programming interface. By adopting the technical means of replacing the interrupt mode with the polling mode, the technical problem of serious IO delay caused by interrupt in the prior art is solved, delay and overhead caused by interrupt are avoided, the port processing efficiency is improved, and the delay of the port is reduced.)

1. The distributed block storage low-delay control method is characterized by comprising the following steps of:

obtaining an application programming interface of a user equipment driver, sending and receiving data packets between the application programming interface and the user equipment, and forming a data descriptor ring, wherein the data descriptor ring comprises: a transmit data descriptor ring and a receive data descriptor ring;

polling logic core polling said receive data descriptor ring of one or more user equipment ports through said application programming interface and sending data packets to processing logic core through said receive data descriptor ring;

the processing logic core receives and processes the data packet according to the strategy rule;

and transmitting the processed data packet on the sending data descriptor ring of the user equipment port through the application programming interface.

2. The distributed block storage low-latency control method according to claim 1, wherein the polling process specifically includes:

the polling logic core polling a ring of received data descriptors of one or more user equipment ports through the application programming interface;

receiving data packets transmitted from the received data descriptor ring and forming a data packet queue;

and the polling logic core sends all the data packets in the data packet queue to the processing logic core.

3. The distributed block storage low latency control method of claim 1,

and the polling logic core polls the processing logic core, the processing logic core finishes processing the data packet, and the processing process is to statically repair or dynamically adjust the overall behavior of the data packet by selecting the policy rule.

4. The distributed block storage low latency control method of claim 1, wherein the policy rules comprise:

the processing logic core receives and sequentially processes the data packets in the data packet list; or the like, or, alternatively,

the processing logic core receives a first preset number of data packets, processes the received data packets and transmits the data packets in real time; or the like, or, alternatively,

and the processing logic core receives a second preset number of data packets, processes the received data packets, and performs integral transmission on the data packets after accumulated processing.

5. The distributed block storage low latency control method of claim 4, wherein the configuration information of the data packet comprises: a transfer queue description value, a memory address socket identifier, a transfer queue register value, a transfer threshold value.

6. A distributed block storage low latency control method according to any one of claims 1 to 5, adapted to a Shenwei processor.

7. A distributed block storage low latency control apparatus, comprising:

the acquisition module is used for acquiring an application programming interface of a user equipment driving program;

the polling logic core is used for polling a received data descriptor ring of one or more user equipment end buckles through the application programming interface and sending a data packet through the data descriptor ring for processing;

and the processing logic core is used for receiving and processing the data packet according to the strategy rule, and the processed data packet is transmitted to the data descriptor ring through the user equipment port for transmission.

8. The distributed block storage low latency control apparatus of claim 7, wherein the polling logic core comprises:

a polling unit for polling the received data descriptor ring of one or more user equipment ports through an application programming interface;

a sending unit, configured to send a data packet to the processing logic core through the received data descriptor ring.

9. The distributed block storage low latency control apparatus of claim 8, wherein the processing logic core comprises:

the processing unit is used for processing the data packet sent by the sending unit;

a transmission unit, configured to transmit the processed data packet to the user equipment through the received data descriptor ring of the user equipment port.

10. A distributed block storage low latency control apparatus, comprising:

at least one processor; and a memory communicatively coupled to the at least one processor;

wherein the processor is operable to perform the method of any one of claims 1 to 7 by invoking a computer program stored in the memory.

Technical Field

The invention relates to the technical field of data storage, in particular to a distributed block storage low-delay control method, a system and equipment.

Background

As server systems based on domestic processors are applied to various cloud computing environments, the application capability of the domestic processor technology in the general technology market is more and more important. At present, the domestic processor has a certain foundation on the technical support capability overall, but has a little gap with the international mainstream similar chip technology.

Compared with the perfect ecological environment of the X86 processor, the domestic processor has obvious defects in application support, and particularly, how to build a distributed storage system on a domestic chip through technical optimization can provide stable and low IO delay storage system service support for computing virtualization, and is an application ecological key means for rapidly promoting a domestic processor platform to form virtuous circle.

The Shenwei processor is developed by computers in south China, and the Shenwei Taihu optical supercomputer based on the Shenwei processor is the fastest supercomputer in China all over the world in cicada union for many years. In the traditional IO model, an application program sleeps after submitting a read-write request, once IO is completed, the interrupt awakens the application program, and frequent interrupt and awakening bring a large amount of processor loss overhead. However, in the era of solid-state devices, lower-latency persistency devices are continuously introduced, and the interrupt overhead becomes a non-negligible part of the total IO time, and the problem only becomes more and more serious on the lower-latency devices.

Disclosure of Invention

The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide a distributed block storage low latency control method, which can reduce the CPU extra loss and consumption as much as possible to improve the overall IO efficiency.

To this end, a second object of the present invention is to provide a distributed block storage low latency control system based on the Shenwei platform.

The technical scheme adopted by the invention is as follows:

in a first aspect, the present invention provides a distributed block storage low latency control method, including the steps of:

obtaining an application programming interface of a user equipment driver, sending and receiving data packets between the application programming interface and the user equipment, and forming a data descriptor ring, wherein the data descriptor ring comprises: a transmit data descriptor ring and a receive data descriptor ring;

polling logic core polling said receive data descriptor ring of one or more user equipment ports through said application programming interface and sending data packets to processing logic core through said receive data descriptor ring;

the processing logic core receives and processes the data packet according to the strategy rule;

and transmitting the processed data packet on the sending data descriptor ring of the user equipment port through the application programming interface.

Further, the polling logic core polls the processing logic core, and the processing logic core completes processing the data packet, and the processing process is to statically repair or dynamically adjust the overall behavior by selecting the policy rule.

Further, the policy rule includes:

the processing logic core receives and sequentially processes the data packets in the data packet list; or the like, or, alternatively,

the processing logic core receives a first preset number of data packets, processes the received data packets and transmits the data packets in real time; or the like, or, alternatively,

and the processing logic core receives a second preset number of data packets, processes the received data packets, and performs integral transmission on the accumulated data packets.

Further, the configuration information of the data packet includes: a transfer queue description value, a memory address socket identifier, a transfer queue register value, a transfer threshold value.

Further, the method is suitable for a Shenwei processor.

In a second aspect, the present invention provides a distributed block storage low latency control apparatus, comprising:

the acquisition module is used for acquiring an application programming interface of a user equipment driving program;

the polling logic core is used for polling a received data descriptor ring of one or more user equipment end buckles through the application programming interface and sending a data packet through the data descriptor ring for processing;

and the processing logic core is used for receiving and processing the data packet according to the strategy rule, and the processed data packet is transmitted to the data descriptor ring through the user equipment port for transmission.

Further, the polling logic core includes:

a polling unit for polling the received data descriptor ring of one or more user equipment ports through an application programming interface;

a sending unit, configured to send a data packet to the processing logic core through the received data descriptor ring.

Further, the processing logic core comprises:

the processing unit is used for processing the data packet sent by the sending unit;

a transmission unit, configured to transmit the processed data packet to the user equipment through the received data descriptor ring of the user equipment port.

In a third aspect, the present invention provides a distributed block storage low latency control device, comprising:

at least one processor; and a memory communicatively coupled to the at least one processor;

wherein the processor is operable to perform the method of any one of claims 1 to 7 by invoking a computer program stored in the memory.

The invention has the beneficial effects that:

according to the invention, by adopting a technical means of replacing the interrupt mode with the polling mode, the technical problem of serious IO delay caused by interrupt in the prior art is solved, delay and overhead brought by a terminal are avoided, the IO efficiency is improved by a program, and lower IO delay is brought.

Drawings

FIG. 1 is a block diagram of an embodiment of a distributed storage low latency control system based on a Schwegian platform;

FIG. 2 is a block diagram of polling processing modules and processing logic cores in an embodiment of a distributed storage low latency control system based on an Shenwei platform;

fig. 3 is a flow chart of an embodiment of a distributed storage low latency control method based on the Shenwei platform.

Reference numerals: 10. an acquisition module; 20. a polling logic core; 21. a polling unit; 22. a transmitting unit; 30. a processing logic core; 31. a processing unit; 32. and a transmission unit.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.