阅读说明：本技术 Ssd主控中的raid多路处理装置及数据恢复方法 (RAID multi-path processing device in SSD master control and data recovery method ) 是由 王运哲 沈力 刘大铕 朱苏雁 刘奇浩 刘尚 孙中琳 王资川 于 2019-10-31 设计创作，主要内容包括：本发明公开一种SSD主控中的RAID多路处理装置,包括总线配置接口AXI_RGF、总线Master接口、总线Slave接口、NFC通道仲裁模块、通路选择仲裁模块、DMA模块、IMA模块、N个异或计算控制模块外加N片双口SRAM。本装置能够为系统提供多通路选择,具体可支持P2S、P2M、M2M、M2S、S2M、S2S六种通路模式。数据恢复方法可以六种通路模式中的任一通路进行,具体的,正常program采用P2S通道,数据恢复采用M2M通路。本发明在SSD主控芯片内部实现RAID,并且可以根据系统情况在不同的工作模式中选用不同的通路,灵活性强。(The invention discloses a RAID multi-path processing device in SSD Master control, which comprises a bus configuration interface AXI _ RGF, a bus Master interface, a bus Slave interface, an NFC channel arbitration module, a path selection arbitration module, a DMA module, an IMA module, N exclusive OR calculation control modules and N pieces of double-port SRAMs. The device can provide multi-channel selection for the system, and particularly can support six channel modes of P2S, P2M, M2M, M2S, S2M and S2S. The data recovery method may be performed in any one of six path modes, specifically, the P2S channel is used for normal program, and the M2M path is used for data recovery. The invention realizes RAID in the SSD main control chip, and can select different paths in different working modes according to the system condition, thereby having strong flexibility.)

1. A RAID multi-path processing device in SSD master control is characterized in that: the method comprises the following steps:

the bus configuration interface AXI _ RGF is used for receiving address and control information configured from the CPU and also used for reading state information and interrupt information of the RAID acceleration module by the CPU;

the bus master interface AXI _ MST is responsible for initiating data transmission to a bus, and comprises reading source data from the bus and writing exclusive or result data to the bus;

the bus slave interface AXI _ SLV is responsible for receiving data to be operated from a bus, and the bus reads operation result data through the interface;

the NFC channel arbitration module N _ ARB is a special interface of the NFC and is responsible for realizing handshake with each channel of the NFC and receiving data of different NFC channels according to a certain priority sequence;

the path selection arbitration module X _ ARB is responsible for switching a data source from AXI _ MST, AXI _ SLV and N _ ARB and switching a data destination from AXI _ MST and AXI _ SLV according to the channel mode;

the DMA module is responsible for connecting the bus master interface and each XOR calculation control module and realizing the conversion from the bus protocol to the internal data transmission protocol;

the IMA module is responsible for connecting a bus slave interface and each XOR calculation control module and realizing the conversion from a bus protocol to an internal data transmission protocol;

the exclusive-or calculation control module is responsible for finishing the flow receiving and iterative exclusive-or operation of each block of data in the same strip;

the double-port SRAM corresponds to the XOR calculation control module one by one and is responsible for temporarily storing an intermediate result of the XOR operation and storing a final result of the XOR operation;

the device provides multi-channel selection for the system through the modules.

2. The RAID multiplexing apparatus in SSD master control of claim 1, wherein: the device supports six channel modes of P2S, P2M, M2M, M2S, S2M and S2S.

3. The RAID multiplexing apparatus in SSD master control of claim 2, wherein: under a P2S access mode, data to be calculated come from NFC, a settlement result goes to a bus slave interface, and a CPU configures an RAID mode and the size of a strip; during operation, the N _ ARB module receives and outputs data packets from each channel of NFC, the X _ ARB module starts a corresponding XOR calculation control module and transmits the data packets from the N _ ARB to the corresponding XOR calculation control module, each XOR calculation control module carries out XOR calculation on the received data and feeds back a completion signal to the X _ ARB module, the X _ ARB module counts all the XOR calculation control modules and feeds back the completion signal to the NFC, and the NFC reads an operation result from an axi _ slv port through a bus after receiving the interruption signal.

4. The RAID multiplexing apparatus in SSD master control of claim 2, wherein: under the M2M access mode, the data to be operated comes from AXI _ MST, the operation result goes to AXI _ MST, and the CPU configures RAID mode, stripe size and access data address on the bus; during operation, the DMA module analyzes configuration information to control the AXI _ MST module to initiate read data transmission to a bus designated address, the X _ ARB module starts a corresponding XOR calculation control module and transmits a data packet from the DMA to the corresponding XOR calculation control module, each XOR calculation control module performs XOR calculation on received data and feeds back a completion signal to the X _ ARB module, the X _ ARB module counts all XOR module completion signals and feeds back the completion signals to the DMA, and the DMA reads an operation result from each XOR calculation control module and initiates write data transmission to the bus designated address through an AXI _ MST interface.

5. The RAID multiplexing apparatus in SSD master control of claim 2, wherein: under a P2M access mode, data to be operated come from NFC, an operation result goes to AXI _ MST, and a CPU configures an RAID mode, a stripe size and a bus address for storing the operation result; during operation, the N _ ARB module receives and outputs data packets from each channel of NFC, the X _ ARB module starts a corresponding XOR calculation control module and transmits the data packets from the N _ ARB to the corresponding XOR calculation control module, each XOR calculation control module carries out XOR calculation on the received data and feeds back a completion signal to the X _ ARB module, the X _ ARB module counts the completion signals of all the XOR modules and starts the DMA module, and the DMA module and the X _ ARB module cooperate to read out operation results from the SRAM, write the operation results into a specified bus address through an axi _ mst port and wait for subsequent operation.

6. The RAID multiplexing apparatus in SSD master control of claim 2, wherein: under the M2S access mode, the data to be operated comes from AXI _ MST, the operation result goes to AXI _ SLV, and the CPU configures RAID mode, strip size and storage address of source data on the bus; during operation, the DMA module analyzes configuration information to control the AXI _ MST module to initiate read data transmission to a bus designated address, the X _ ARB module starts a corresponding XOR calculation control module and transmits a data packet from the DMA to the corresponding XOR calculation control module, the XOR calculation control module performs XOR calculation on received data and feeds back a completion signal to the X _ ARB module, the X _ ARB module counts all XOR module completion signals and sends an interrupt signal to a CPU, an NFC or other host on the bus reads an XOR result through an AXI _ slv port, and in the process, the IMA module and the X _ ARB module cooperate to read and feed back an operation result from the SRAM.

7. The RAID multiplexing apparatus in SSD master control of claim 2, wherein: in the S2M access mode, the data to be operated comes from AXI _ SLV, the operation result goes to AXI _ MST, and the CPU configures RAID mode, stripe size and bus address for storing the operation result; during operation, the AXI _ SLV module receives a data packet from a bus, the IMA module converts the data packet into an internal data packet format, the X _ ARB module starts a corresponding XOR calculation control module and transmits the data packet from the IMA to the corresponding XOR calculation control module, the XOR calculation control module carries out XOR calculation on the received data and feeds back a completion signal to the X _ ARB module, the X _ ARB module counts all XOR module completion signals and starts the DMA module, and the DMA module and the X _ ARB module cooperate to read out an operation result from the SRAM, write a specified bus address through an AXI _ mst port and wait for subsequent operation.

8. The RAID multiplexing apparatus in SSD master control of claim 2, wherein: in the S2S channel mode, the data to be operated comes from AXI _ SLV, the operation result goes to AXI _ SLV, and in addition, the CPU configures RAID mode and stripe size; during operation, the AXI _ SLV module receives data packets from a bus, the IMA module converts the data packets into an internal data packet format, the X _ ARB module sequentially starts a corresponding XOR calculation control module and transmits the data packets from the IMA to the corresponding XOR calculation control module, the XOR calculation control module carries out XOR calculation on the received data and feeds back a completion signal to the X _ ARB module, the X _ ARB module counts all the completion signals of the XOR module and feeds back a terminal signal to a CPU, an NFC or other host on the bus can read an XOR result through an AXI _ SLV port, and the IMA module and the X _ ARB module cooperate to read and feed back the calculation result from the SRAM in the process.

9. A method of data recovery, characterized by: the method is based on the RAID multi-path processing device of claim 2, wherein the normal program and data recovery adopt one of six paths of P2S, P2M, M2M, M2S, S2M and S2S.

10. The data recovery method of claim 9, wherein: the normal program adopts a P2S channel, and the data recovery adopts an M2M channel.

Technical Field

The invention relates to an RAID accelerating device, in particular to an RAID multipath processing device in SSD master control and a data recovery method.

Background

In reading and writing the SSD, when data is read from the Flash granule, if ECC error correction fails and the read re-try operation fails to read correct data, how to recover the data needs to be considered. RAID technology can fully exploit the array advantages of storage chips, provide fault tolerance to ensure data security, and continue to operate when a problem occurs in a storage unit. I.e. data recovery can be achieved by RAID techniques. The existing RAID is generally realized outside an SSD master control chip, although the patent 'an RAID active accelerating device in SSD master control' and 'an RAID passive accelerating device in SSD master control' disclose a method for realizing the RAID inside the SSD master control chip, the two are single hardware path designs, corresponding paths cannot be selected according to application requirements, and the flexibility is poor.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a RAID multi-path processing device in SSD master control and a data recovery method, wherein the RAID is realized in an SSD master control chip, and different paths can be selected in different working modes according to the system condition, so that the flexibility is strong.

In order to solve the technical problem, the technical scheme adopted by the invention is as follows: a RAID multiplexing device in an SSD master, comprising:

the bus configuration interface AXI _ RGF is used for receiving address and control information configured from the CPU and also used for reading state information and interrupt information of the RAID acceleration module by the CPU;

the bus master interface AXI _ MST is responsible for initiating data transmission to a bus, and comprises reading source data from the bus and writing exclusive or result data to the bus;

the bus slave interface AXI _ SLV is responsible for receiving data to be operated from a bus, and the bus reads operation result data through the interface;

the NFC channel arbitration module N _ ARB is a special interface of the NFC and is responsible for realizing handshake with each channel of the NFC and receiving data of different NFC channels according to a certain priority sequence;

the path selection arbitration module X _ ARB is responsible for switching a data source from AXI _ MST, AXI _ SLV and N _ ARB and switching a data destination from AXI _ MST and AXI _ SLV according to the channel mode;

the DMA module is responsible for connecting the bus master interface and each XOR calculation control module and realizing the conversion from the bus protocol to the internal data transmission protocol;

the IMA module is responsible for connecting a bus slave interface and each XOR calculation control module and realizing the conversion from a bus protocol to an internal data transmission protocol;

the exclusive-or calculation control module is responsible for finishing the flow receiving and iterative exclusive-or operation of each block of data in the same strip;

the double-port SRAM corresponds to the XOR calculation control module one by one and is responsible for temporarily storing an intermediate result of the XOR operation and storing a final result of the XOR operation;

the device provides multi-channel selection for the system through the modules.

Further, the device supports six channel modes of P2S, P2M, M2M, M2S, S2M and S2S.

Further, under a P2S access mode, data to be calculated come from NFC, a settlement result goes to a bus slave interface, and a CPU configures an RAID mode and a stripe size; during operation, the N _ ARB module receives and outputs data packets from each channel of NFC, the X _ ARB module starts a corresponding XOR calculation control module and transmits the data packets from the N _ ARB to the corresponding XOR calculation control module, each XOR calculation control module carries out XOR calculation on the received data and feeds back a completion signal to the X _ ARB module, the X _ ARB module counts all the XOR calculation control modules and feeds back the completion signal to the NFC, and the NFC reads an operation result from an axi _ slv port through a bus after receiving the interruption signal.

Under the M2M access mode, the data to be operated comes from AXI _ MST, the operation result goes to AXI _ MST, and the CPU configures RAID mode, stripe size and access data address on the bus; during operation, the DMA module analyzes configuration information to control the AXI _ MST module to initiate read data transmission to a bus designated address, the X _ ARB module starts a corresponding XOR calculation control module and transmits a data packet from the DMA to the corresponding XOR calculation control module, each XOR calculation control module performs XOR calculation on received data and feeds back a completion signal to the X _ ARB module, the X _ ARB module counts all XOR module completion signals and feeds back the completion signals to the DMA, and the DMA reads an operation result from each XOR calculation control module and initiates write data transmission to the bus designated address through an AXI _ MST interface.

Further, under a P2M access mode, data to be operated come from NFC, an operation result goes to AXI _ MST, and a CPU configures an RAID mode, a stripe size and a bus address for storing the operation result; during operation, the N _ ARB module receives and outputs data packets from each channel of NFC, the X _ ARB module starts a corresponding XOR calculation control module and transmits the data packets from the N _ ARB to the corresponding XOR calculation control module, each XOR calculation control module carries out XOR calculation on the received data and feeds back a completion signal to the X _ ARB module, the X _ ARB module counts the completion signals of all the XOR modules and starts the DMA module, and the DMA module and the X _ ARB module cooperate to read out operation results from the SRAM, write the operation results into a specified bus address through an axi _ mst port and wait for subsequent operation.

Furthermore, under the M2S channel mode, the data to be operated comes from AXI _ MST, the operation result goes to AXI _ SLV, and the CPU configures RAID mode, strip size and storage address of source data on the bus; during operation, the DMA module analyzes configuration information to control the AXI _ MST module to initiate read data transmission to a bus designated address, the X _ ARB module starts a corresponding XOR calculation control module and transmits a data packet from the DMA to the corresponding XOR calculation control module, the XOR calculation control module performs XOR calculation on received data and feeds back a completion signal to the X _ ARB module, the X _ ARB module counts all XOR module completion signals and sends an interrupt signal to a CPU, an NFC or other host on the bus reads an XOR result through an AXI _ slv port, and in the process, the IMA module and the X _ ARB module cooperate to read and feed back an operation result from the SRAM.

Further, in the S2M access mode, the data to be operated comes from AXI _ SLV, the operation result goes to AXI _ MST, and the CPU configures RAID mode, stripe size and bus address for storing the operation result; during operation, the AXI _ SLV module receives a data packet from a bus, the IMA module converts the data packet into an internal data packet format, the X _ ARB module starts a corresponding XOR calculation control module and transmits the data packet from the IMA to the corresponding XOR calculation control module, the XOR calculation control module carries out XOR calculation on the received data and feeds back a completion signal to the X _ ARB module, the X _ ARB module counts all XOR module completion signals and starts the DMA module, and the DMA module and the X _ ARB module cooperate to read out an operation result from the SRAM, write a specified bus address through an AXI _ mst port and wait for subsequent operation.

Further, in the S2S channel mode, the data to be operated comes from AXI _ SLV, the operation result goes to AXI _ SLV, and in addition, the CPU configures RAID mode and stripe size; during operation, the AXI _ SLV module receives data packets from a bus, the IMA module converts the data packets into an internal data packet format, the X _ ARB module sequentially starts a corresponding XOR calculation control module and transmits the data packets from the IMA to the corresponding XOR calculation control module, the XOR calculation control module carries out XOR calculation on the received data and feeds back a completion signal to the X _ ARB module, the X _ ARB module counts all the completion signals of the XOR module and feeds back a terminal signal to a CPU, an NFC or other host on the bus can read an XOR result through an AXI _ SLV port, and the IMA module and the X _ ARB module cooperate to read and feed back the calculation result from the SRAM in the process.

The method also discloses a data recovery method, based on the RAID multi-path processing device of claim 2, wherein one of six paths of P2S, P2M, M2M, M2S, S2M and S2S is adopted for normal program and data recovery.

Further, the normal program adopts a P2S channel, and the data recovery adopts an M2M channel.

The invention has the beneficial effects that: the invention comprises AXI _ MST and AXI _ SLV interfaces, adds two modules of NFC channel selection and internal channel arbitration, and provides multi-channel selection for the system by embedding the array SRAM, thereby realizing that the corresponding channel can be selected according to the application requirement when in program or recovery, and the flexibility is strong. When the system is in a normal program, RAID operation can be parallel to other operations of NFC on data, and efficiency is improved to the maximum extent. The system starts DMA operation when recovering data, can uniformly schedule the whole data and improves the stability to the maximum extent.

Drawings

FIG. 1 is a schematic block diagram of a RAID multiplexing apparatus according to an embodiment.

Detailed Description

The invention is further described with reference to the following figures and specific embodiments.