阅读说明：本技术 一种基于FPGA的FlexRay-CPCIe通信模块 (FlexRay-CPCIe communication module based on FPGA ) 是由 董虓霄 马云峰 李泉 于 2019-11-13 设计创作，主要内容包括：本发明公开了一种基于FPGA的FlexRay-CPCIe通信模块,FPGA最小系统作为通信模块的处理核心,通过对FPGA芯片内部IP核和集成硬核设计,实现对通信模块的时钟管理和逻辑控制,完成PCIe系统总线与FlexRay高速外部总线之间的数据交换,CPCIe通信单元执行PCIe总线标准,实现计算机与通信模块之间数据交换；FlexRay总线通信单元执行FlexRay通信协议,实现通信模块与外部高速总线网络之间数据传输；CPCIe通信单元采用PCIe系统总线标准接口与计算机机箱内CPCIe接口连接,实现通信模块与计算机之间数据传输。本发明实现对FlexRay总线网络进行开发、仿真和测试,增加FlexRay总线应用的便利性。(The invention discloses a FlexRay-CPCIe communication module based on an FPGA, wherein a minimum FPGA system is used as a processing core of the communication module, clock management and logic control of the communication module are realized by designing an IP core and an integrated hard core inside an FPGA chip, data exchange between a PCIe system bus and a FlexRay high-speed external bus is completed, and a CPCIe communication unit executes a PCIe bus standard to realize data exchange between a computer and the communication module; the FlexRay bus communication unit executes a FlexRay communication protocol to realize data transmission between the communication module and an external high-speed bus network; the CPCIe communication unit is connected with a CPCIe interface in the computer case by adopting a PCIe system bus standard interface to realize data transmission between the communication module and the computer. The invention realizes the development, simulation and test of the FlexRay bus network and increases the convenience of the application of the FlexRay bus.)

1. An FPGA-based FlexRay-CPCIe communication module, comprising: the system comprises an FPGA minimum system, a FlexRay bus communication unit and a power circuit unit, wherein the FPGA minimum system is internally provided with a CPCIe communication unit and is used as a processing core of a communication module, clock management and logic control of the communication module are realized by designing an IP core and an integrated hard core inside an FPGA chip, data exchange between a PCIe system bus and a FlexRay high-speed external bus is completed, the CPCIe communication unit executes PCIe bus standard, and data exchange between a computer and the communication module is realized; the FlexRay bus communication unit executes a FlexRay communication protocol to realize data transmission between the communication module and an external high-speed bus network; the CPCIe communication unit is connected with a CPCIe interface in the computer case by adopting a PCIe system bus standard interface to realize data transmission between the communication module and the computer; and the power circuit unit supplies power to each unit of the communication module.

2. The FPGA-based FlexRay-CPCIe communication module according to claim 1, wherein the communication module is installed on a CPCIe back plate in a computer case to realize the functions of developing and testing a FlexRay high-speed bus by using a computer operating system.

3. The FPGA-based FlexRay-CPCIe communications module of claim 2, wherein the FPGA minimal system comprises an FPGA chip, clock circuitry, configuration interfaces, and program storage circuitry; the FPGA chip adopts an XC5VLX110T chip of Virtex-5 series of Xilinx company, and the chip is provided with 680 user-defined I/O pin interfaces and a plurality of configuration modes; the clock circuit adopts an external crystal oscillator; the configuration interface meets a debugging mode and a bit peripheral interface mode; the program storage chip adopts a StrataFlash chip.

4. The FPGA-based FlexRay-CPCIe communication module according to claim 3, wherein the CPCIe communication unit realizes PCIe communication of the communication module by utilizing a PCIe hard core and a high-speed data input output interface IP core which are integrated inside the FPGA; the sending/receiving control and the configuration state check are written by verilog language, wherein the sending/receiving control is responsible for extracting and storing data of the data cache module, and the configuration state check is responsible for checking the state of the PCIe hard core configuration space.

5. The FPGA-based FlexRay-CPCIe communication module according to claim 4, wherein the FlexRay bus communication unit adopts a FlexRay bus node framework scheme of a communication controller and bus drivers, and comprises a communication controller and two bus drivers respectively; the communication controller chip is connected with the FPGA and adopts MFR 4310; the two bus driver chips are respectively connected with the communication control chip, and the bus driver chips adopt TJA 1080.

6. The FPGA-based FlexRay-CPCIe communication module according to claim 5, wherein the FPGA is connected with the MFR4310 by means of an asynchronous memory interface, and comprises a clock signal, a data signal, an address signal, a read/write enable signal, an interrupt signal and a reset signal, and the MFR4310 and TJA1080 are connected with a receiving/transmitting enable signal by means of a data signal.

7. The FPGA-based FlexRay-CPCIe communication module of claim 6, wherein the FPGA comprises a clock management module, a FlexRay data transceiver module and a CPCIe data transceiver module; in the clock management module, a clock signal generated by an external crystal oscillator is input into the FPGA through a special global clock pin; the FlexRay data transceiver module comprises a FlexRay protocol control module, a channel control module, an interrupt interface module and a data cache module which are written by verilog language; the CPCIe data transceiver module comprises a PCIe communication unit, an interrupt interface module and a data cache module which are written by verilog language.

8. The FPGA-based FlexRay-CPCIe communication module according to claim 7, wherein the FlexRay protocol control module completes initialization configuration and protocol operation configuration, the initialization configuration comprises the setting of FlexRay global parameters and communication modes, and the protocol operation configuration comprises the conversion and control of each state in the communication process of the FlexRay; the channel control module realizes control over the communication state and the enabling of the two-channel FlexRay; the interrupt interface module realizes the monitoring and elimination of interrupt signals; the data cache module consists of asynchronous FIFO and realizes the transmission and reception of FlexRay data.

9. The FPGA-based FlexRay-CPCIe communications module of claim 8, wherein the PCIe communications unit performs initialization configuration and data transmission and protection; the interrupt interface module realizes the monitoring and elimination of interrupt signals; the data cache module consists of asynchronous FIFO and realizes the sending and receiving of PCIe data.

10. The FPGA-based FlexRay-CPCIe communication module of claim 9, wherein the power module employs a multi-output DC/DC chip to provide power requirements for a FlexRay bus communication unit and a minimum system of the FPGA; the FPGA is powered by 1.2V, 1.5V and 3.3V, MFR4310 is powered by 3.3V, and TJA1080 is powered by 5V.

Technical Field

The invention belongs to the technical field of network communication, and relates to a FlexRay-CPCIe communication module based on an FPGA (field programmable gate array), which is used for realizing data communication between a computer and a FlexRay high-speed external bus through a PCIe (peripheral component interface express) system bus.

Background

Bus communication is widely applied to various industrial control networks, mainly aims to solve the problem of communication among different electronic devices, and is particularly embodied in the fields of aerospace, automobile manufacturing, navigation, automatic control, process industry and the like. At present, the external bus communication technology with long application time and mature technical development comprises a CAN bus, a 1553B bus and the like, and has the characteristics of high reliability, high certainty, high fault tolerance and the like. However, with the continuous development of scientific technology, the increasing data volume and the higher real-time communication requirement have gradually challenged the conventional external bus communication technology, and a new generation of high-speed external bus technology FlexRay bus is beginning to be applied in the related field.

As a new generation high-speed serial external bus protocol, FlexRay has obvious advantages in the aspects of communication speed/reliability, flexibility and the like compared with the traditional bus. The FlexRay bus is only applied to vehicle-mounted bus communication networks of a few brands at present, and has a great application prospect. Compared with the data transmission rate of 1Mbps highest for the CAN bus and the 1553B bus, the data transmission rate of a single channel of the FlexRay bus supports 10Mbps highest, and the total transmission rate of the two channels CAN reach 20Mbps highest, so that the communication requirements of large data volume and high real-time performance CAN be met; the two channels can realize three working modes of single-channel working, double-channel working and redundant working. In addition, the FlexRay bus network has flexible topological structure and supports various structures such as point-to-point, bus type, active star type and the like. In the aspect of a communication mechanism, a FlexRay bus adopts cycle communication, a data frame is supported to 254 frames at most, and a receiving node can be ensured to predict the arrival time of a message in advance by reasonably configuring a communication cycle and the message length.

In a system bus communication network, a third generation I/O bus-PCIe bus gradually replaces a second generation I/O bus-PCI bus technology due to its characteristics of supporting serial differential transmission, flexible bandwidth, high transmission rate, and the like, and is widely applied to a computer backplane interface to implement data communication among a CPU, a memory, and other board cards. Compared with the common PCIe interface, the CPCIe interface is more widely applied to the fields of military industry, measurement and control, aerospace and the like due to the characteristics of strong electromagnetic compatibility, good oxidation resistance and the like. Because computers have the advantages of human-computer interactivity, strong system operability and the like, the computers are generally used as upper computers or network nodes to take charge of receiving and sending commands and collecting and monitoring data. The communication between the board cards or the board cards and the computer is realized by installing the board cards with different functions on a computer backboard with a CPCIe interface. When the computer needs to communicate with an external bus, a bus communication module based on a CPCIe interface is added in the case aiming at a specific external communication bus protocol.

However, the two communication protocols of the PCIe system bus and the FlexRay high-speed external bus are not compatible with each other, which restricts the application range of the FlexRay high-speed bus while the computer functions in the FlexRay bus communication network.

Disclosure of Invention

Objects of the invention

The purpose of the invention is: aiming at the problem that two communication protocols of a PCIe system bus and a FlexRay high-speed external bus are incompatible with each other, an FPGA-based FlexRay-CPCIe communication module is provided, and the functions of taking a computer as an upper computer or a network node, communicating with the FlexRay bus, receiving and sending commands to the FlexRay high-speed bus, and collecting and monitoring data are realized.

(II) technical scheme

In order to solve the above technical problem, the present invention provides an FPGA-based FlexRay-CPCIe communication module, which includes: the system comprises an FPGA minimum system, a FlexRay bus communication unit and a power circuit unit, wherein the FPGA minimum system is internally provided with a CPCIe communication unit and is used as a processing core of a communication module, clock management and logic control of the communication module are realized by designing an IP core and an integrated hard core inside an FPGA chip, data exchange between a PCIe system bus and a FlexRay high-speed external bus is completed, the CPCIe communication unit executes PCIe bus standard, and data exchange between a computer and the communication module is realized; the FlexRay bus communication unit executes a FlexRay communication protocol to realize data transmission between the communication module and an external high-speed bus network; the CPCIe communication unit is connected with a CPCIe interface in the computer case by adopting a PCIe system bus standard interface to realize data transmission between the communication module and the computer; and the power circuit unit supplies power to each unit of the communication module.

The communication module is arranged on a CPCIe back plate in a computer case, and the functions of developing and testing a FlexRay high-speed bus by using a computer operating system are realized.

The FPGA minimum system comprises an FPGA chip, a clock circuit, a configuration interface and a program storage circuit; the FPGA chip adopts an XC5VLX110T chip of Virtex-5 series of Xilinx company, and the chip is provided with 680 user-defined I/O pin interfaces and a plurality of configuration modes; the clock circuit adopts an external crystal oscillator; the configuration interface meets a debugging mode and a bit peripheral interface mode; the program storage chip adopts a StrataFlash chip.

The CPCIe communication unit realizes the PCIe communication of the communication module by utilizing a PCIe hard core and a high-speed data input and output interface IP core which are integrated in the FPGA; the sending/receiving control and the configuration state check are written by verilog language, wherein the sending/receiving control is responsible for extracting and storing data of the data cache module, and the configuration state check is responsible for checking the state of the PCIe hard core configuration space.

The FlexRay bus communication unit adopts a FlexRay bus node framework scheme of a communication controller and bus drivers, and comprises the communication controller and the two bus drivers respectively; the communication controller chip is connected with the FPGA and adopts MFR 4310; the two bus driver chips are respectively connected with the communication control chip, and the bus driver chips adopt TJA 1080.

The FPGA and the MFR4310 are connected in an asynchronous memory interface mode and comprise clock signals, data signals, address signals, read/write enable signals, interrupt signals and reset signals, and the MFR4310 and TJA1080 are connected with receiving/transmitting enable signals through data signals.

The FPGA comprises a clock management module, a FlexRay data transceiver module and a CPCIe data transceiver module; in the clock management module, a clock signal generated by an external crystal oscillator is input into the FPGA through a special global clock pin; the FlexRay data transceiver module comprises a FlexRay protocol control module, a channel control module, an interrupt interface module and a data cache module which are written by verilog language; the CPCIe data transceiver module comprises a PCIe communication unit, an interrupt interface module and a data cache module which are written by verilog language.

The FlexRay protocol control module completes initialization configuration and protocol operation configuration, the initialization configuration comprises FlexRay global parameters and communication mode setting, and the protocol operation configuration comprises conversion and control of each state in the FlexRay communication process; the channel control module realizes control over the communication state and the enabling of the two-channel FlexRay; the interrupt interface module realizes the monitoring and elimination of interrupt signals; the data cache module consists of asynchronous FIFO and realizes the transmission and reception of FlexRay data.

The PCIe communication unit completes initialization configuration and data transmission and protection; the interrupt interface module realizes the monitoring and elimination of interrupt signals; the data cache module consists of asynchronous FIFO and realizes the sending and receiving of PCIe data.

The power supply module adopts a multi-output DC/DC chip to provide power supply requirements for a FlexRay bus communication unit and an FPGA minimum system; the FPGA is powered by 1.2V, 1.5V and 3.3V, MFR4310 is powered by 3.3V, and TJA1080 is powered by 5V.

(III) advantageous effects

The FlexRay-CPCIe communication module based on the FPGA can be freely installed in a CPCIe standard interface on a backboard of a computer case, the FPGA is used as a core processor of the module to realize the transceiving control of two buses, the data communication between a computer and a FlexRay high-speed external bus through a PCIe system bus is realized, the development, simulation and test of a FlexRay bus network are further realized through an operating system based on the computer, and the convenience of the application of the FlexRay bus is improved.

Drawings

FIG. 1 is a schematic diagram of an FPGA-based FlexRay-CPCIe communication module of the present invention;

FIG. 2 is a schematic diagram of the FPGA minimal system of the present invention;

FIG. 3 is a schematic diagram of a CPCIe communication unit of the present invention;

fig. 4 a schematic diagram of a FlexRay bus communication unit according to the invention;

FIG. 5 is a functional diagram of the interior of the FPGA of the present invention;

FIG. 6 is a functional diagram of the asynchronous FIFO logic of the present invention;

fig. 7 is a schematic diagram of a power module of the present invention.

Detailed Description

In order to make the objects, contents and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.

Fig. 1 is a schematic diagram of an FPGA-based FlexRay-CPCIe communication module according to the present invention, where the communication module includes an FPGA minimal system (including a CPCIe communication unit), a FlexRay bus communication unit, and a power circuit unit, the FPGA minimal system includes an FPGA chip and a CPCIe communication unit, the FPGA minimal system serves as a processing core of the communication module, and implements clock management and logic control on the communication module by designing an IP core and an integrated hardmac inside the FPGA chip, so as to complete data exchange between a PCIe system bus and a FlexRay high-speed external bus, and the CPCIe communication unit implements a PCIe bus standard, so as to implement data exchange between a computer and the communication module; the FlexRay bus communication unit executes a FlexRay communication protocol to realize data transmission between the communication module and an external high-speed bus network; the CPCIe communication unit is connected with a CPCIe interface in the computer case by adopting a PCIe system bus standard interface to realize data transmission between the communication module and the computer; and the power circuit unit supplies power to each unit of the communication module. The communication module is arranged on a CPCIe back plate in a computer case, so that functions of developing and testing a FlexRay high-speed bus by using a computer operating system are realized.

FIG. 2 is a schematic diagram of the minimum system of the FPGA of the present invention. The FPGA minimum system comprises an FPGA chip, a clock circuit, a configuration interface and a program storage circuit. The FPGA chip adopts an XC5VLX110T chip of Virtex-5 series of Xilinx company, and the chip has up to 680 user-defined I/O pin interfaces and a plurality of configuration modes, so that the design flexibility is improved; the 16 high-speed serial transceivers (GTP) and the PCIe module of the hard core endpoint can be directly used for receiving and transmitting PCIe data; the clock adopts a high-precision external crystal oscillator; in order to enhance the configuration efficiency of the FPGA chip, the configuration interface can simultaneously meet a debugging action group (JTAG) mode and a Bit Peripheral Interface (BPI) mode; the program storage chip adopts a StrataFlash chip.

Fig. 3 is a schematic diagram of a CPCIe communication unit of the present invention. The CPCIe communication unit realizes the PCIe communication of the communication module by utilizing a PCIe hard core and a high-speed data input/output interface (socket I/O) IP core which are integrated in the FPGA. The sending/receiving control and the configuration state check are written by verilog language, wherein the sending/receiving control is responsible for extracting and storing data of the data cache module, and the configuration state check is responsible for checking the state of the PCIe hard core configuration space. The PCIe integrated hard core is completely compatible with PCIe 1.1 version, and realizes the functions of a bus transaction layer, a data link layer and a physical layer protocol. After the data passes through the PCIe integrated hardmac, a high-speed serial transceiver (GTP) of a high-speed data input/output interface (socket I/O) is directly connected to the CPCIe standard connector, so that the PCIe data is transmitted and received.

Fig. 4 is a schematic diagram of a FlexRay bus communication unit according to the invention. The FlexRay bus communication unit adopts a FlexRay bus node framework scheme of a communication controller and bus drivers, and comprises the communication controller and the two bus drivers respectively. The communication controller chip is connected with the FPGA and adopts MFR 4310; the two bus driver chips are respectively connected with the communication control chip, and the bus driver chips adopt TJA 1080.

The FPGA and the MFR4310 are connected in an Asynchronous Memory Interface (AMI) mode, and comprise a clock signal, a data signal, an address signal, a read/write enable signal, an interrupt signal and a reset signal, and the MFR4310 and TJA1080 are connected with a receiving/transmitting enable signal through data signals.

Fig. 5 is a functional diagram of the internal logic of the FPGA of the present invention, which is composed of a clock management module, a FlexRay data transceiver module, and a CPCIe data transceiver module.

In the clock management module, a clock signal generated by an external crystal oscillator is input into the FPGA from a special global clock pin (GCLK). In order to improve the driving capability of the clock signal, a global clock buffer (IBUFG) is needed first. In order to ensure clock precision, a clock management module (DCM) is used for adjusting the frequency of a clock signal output by the IBUFG, the output of the DCM is connected to a global Buffer (BUFG), and a stable single-ended clock signal is obtained and is used for being called by a FlexRay data transceiver module and a CPCIe data transceiver module.

The FlexRay data transceiver module comprises a FlexRay protocol control module, a channel control module, an interrupt interface module and a data cache module which are written by verilog language. The FlexRay protocol control module completes initialization configuration and protocol operation configuration, the initialization configuration comprises the setting of FlexRay global parameters and a communication mode, and the protocol operation configuration comprises the conversion and control of each state in the FlexRay communication process; the channel control module realizes control over the communication state and the enabling of the two-channel FlexRay; the interrupt interface module realizes the monitoring and elimination of interrupt signals; the data cache module consists of asynchronous FIFO and realizes the transmission and reception of FlexRay data.

The CPCIe data transceiver module comprises a PCIe communication unit, an interrupt interface module and a data cache module which are written by verilog language. The PCIe communication unit completes initialization configuration and data transmission and protection; the interrupt interface module realizes the monitoring and elimination of interrupt signals; the data cache module consists of asynchronous FIFO and realizes the sending and receiving of PCIe data.

FIG. 6 is a functional diagram of the asynchronous FIFO logic of the present invention. Due to the fact that clock rates of the FlexRay data transceiver module and the CPCIe data transceiver module are different, in order to avoid data loss, an asynchronous FIFO is adopted in the FPGA for caching data. The asynchronous FIFO mainly comprises a double-port RAM, a read/write address generator and an empty/full signal generator. And for the FlexRay data transceiver module and the CPCIe data transceiver module, the working modes of asynchronous FIFO are consistent. The transmission of the signal is controlled by a write clock and write enable (transmission enable), and when the non-full signal is valid, transmission data and an address are written into the RAM; the data and address are then sent to the corresponding communication protocol, controlled by the read clock and read enable (communication protocol receive enable). The receiving of the signal is controlled by a write clock and a write enable (communication protocol transmission enable), and when the non-full signal is effective, the received data and the address are written into the RAM; then controlled by the read clock and read enable (receive enable), extracts the data and address, and performs the subsequent operations.

Fig. 7 is a schematic diagram of a power module of the present invention. The power module adopts a multi-output DC/DC chip to provide power supply requirements for the FlexRay bus communication unit and the FPGA minimum system. The FPGA is powered by 1.2V, 1.5V and 3.3V, MFR4310 is powered by 3.3V, and TJA1080 is powered by 5V.

According to the technical scheme, the FPGA minimum system serves as a core processor of a communication module to respectively control a CPCIe communication unit and a FlexRay communication controller chip, data of a FlexRay bus are processed by the FPGA and then sent to a computer through the CPCIe communication unit, meanwhile, commands issued by the computer are sent to a designated terminal on the bus through the CPCIe communication unit and the FlexRay bus after being processed by the FPGA, and the functions of taking the computer as an upper computer or a network node, receiving and sending commands to the FlexRay high-speed bus, and collecting and monitoring data are achieved.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.