Floating boost precharge scheme for sense amplifiers
阅读说明:本技术 用于读出放大器的浮置升压预充电方案 (Floating boost precharge scheme for sense amplifiers ) 是由 A·康特 L·基亚拉蒙特 A·R·M·里帕尼 于 2019-08-15 设计创作,主要内容包括:本公开的实施例涉及用于读出放大器的浮置升压预充电方案。一种感测结构包括:读出放大器核,其被配置为将测量电流与参考电流进行比较;共源共栅晶体管,其耦合到读出放大器核并且被配置为耦合到负载;开关,其耦合在共源共栅晶体管的偏置电压节点和控制端子之间;本地电容器,其具有耦合到共源共栅晶体管的控制端子的第一端子;第一晶体管,其耦合在本地电容器的第二端子和参考端子之间;以及控制电路,其耦合到第一晶体管的控制端子,该控制电路被配置为将本地电容器与参考端子断开以在共源共栅晶体管的控制端子中产生电压过冲,并且在将本地电容器与参考端子断开之后,通过调整第一晶体管的控制端子的电压来限制或减少电压过冲。(Embodiments of the present disclosure relate to a floating boost precharge scheme for a sense amplifier. A sensing structure comprising: a sense amplifier core configured to compare the measurement current to a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between the second terminal of the local capacitor and a reference terminal; and a control circuit coupled to the control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and to limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor after disconnecting the local capacitor from the reference terminal.)
1. A sensing structure, comprising:
a sense amplifier core configured to compare the measurement current to a reference current;
a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load;
a switch coupled between a bias voltage node and a control terminal of the cascode transistor;
a local capacitor having a first terminal coupled to the control terminal of the cascode transistor;
a first transistor coupled between the second terminal of the local capacitor and a reference terminal; and
a control circuit coupled to a control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and to limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor after disconnecting the local capacitor from the reference terminal.
2. The sensing architecture of claim 1, wherein the control circuit is configured to adjust the voltage of the control terminal of the first transistor based on a voltage across the switch.
3. The sensing structure of claim 1, wherein the control circuit comprises:
a second transistor coupled between the second terminal of the local capacitor and the reference terminal;
a third transistor coupled between the control terminal of the first transistor and the reference terminal; and
a first terminal configured to receive a first voltage, wherein the first terminal is coupled to a control terminal of the second transistor and to a control terminal of the third transistor.
4. The sensing structure of claim 3, wherein the control circuit further comprises:
a fourth transistor having a control terminal coupled to the control terminal of the first transistor;
a fifth transistor coupled between a power supply terminal of the control circuit and the fourth transistor, the fifth transistor having a control terminal coupled to the bias voltage node; and
a sixth transistor coupled between the power supply terminal of the control circuit and the fourth transistor, the sixth transistor having a control terminal coupled to the control terminal of the cascode transistor.
5. The sensing structure of claim 4, wherein the control circuit further comprises:
a seventh transistor coupled between the power supply terminal of the control circuit and the fifth transistor, the seventh transistor having a control terminal coupled to the first terminal; and
an eighth transistor coupled between the power supply terminal of the control circuit and the sixth transistor, the eighth transistor having a control terminal coupled to the first terminal.
6. The sensing architecture of claim 5, wherein the first, second, third, fourth, fifth, and sixth transistors are NMOS transistors, and wherein the seventh and eighth transistors are PMOS transistors.
7. The sensing architecture of claim 5, wherein the control circuit further comprises a ninth transistor coupled between the power supply terminal of the control circuit and the fifth transistor, the ninth transistor having a control terminal configured to receive a second bias voltage, and wherein the sense amplifier core is configured to receive the second bias voltage.
8. The sensing structure of claim 5, wherein the control terminal of the fourth transistor is coupled to a drain terminal of the fifth transistor.
9. The sensing structure of claim 1, further comprising:
a second switch coupled between a power supply terminal of the sensing structure and the cascode transistor; and
a third switch coupled between the second switch and the sense amplifier core.
10. The sensing architecture of claim 1, further comprising a bias stage configured to generate a bias voltage at the bias voltage node, wherein the bias stage comprises:
an amplifier having an output coupled to the output of the bias stage;
a common capacitor coupled to the output of the biasing stage; and
a tenth transistor having a control terminal coupled to the output of the biasing stage.
11. The sensing architecture of claim 1, wherein the cascode transistor is configured to be coupled to a memory cell as the load.
12. A non-volatile memory, comprising:
a plurality of memory cells arranged in rows and columns;
a row decoder coupled to the plurality of memory cells via a plurality of word lines;
a column decoder coupled to the plurality of memory cells via a plurality of bit lines;
a bias stage configured to generate a bias voltage; and
a plurality of sense amplifiers, wherein each sense amplifier comprises:
a sense amplifier core configured to compare the measurement current to a reference current;
a cascode transistor coupled between the sense amplifier core and one of the plurality of bit lines;
a switch coupled between an output of the biasing stage and a control terminal of the cascode transistor;
a local capacitor having a first terminal coupled to the control terminal of the cascode transistor;
a first transistor coupled between the second terminal of the local capacitor and a reference terminal; and
a control circuit coupled to a control terminal of the first transistor, the control circuit configured to: disconnecting the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor; and limiting or reducing the voltage overshoot by adjusting a voltage of the control terminal of the first transistor after disconnecting the local capacitor from the reference terminal.
13. The non-volatile memory of claim 12, further comprising a controller configured to:
receiving a read request;
opening the switch in response to the read request; and
causing the control circuit to disconnect the local capacitor from the reference terminal in response to the read request.
14. The non-volatile memory of claim 13, wherein the controller causes the control circuit to disconnect the local capacitor from the reference terminal while opening the switch.
15. The non-volatile memory of claim 13, wherein each sense amplifier further comprises:
a second switch coupled between a power supply terminal of the sense amplifier and the cascode transistor; and
a third switch coupled between the second switch and the sense amplifier core, and wherein the controller is further configured to close the second switch when the switch is opened.
16. The non-volatile memory as in claim 12, wherein the bias stage comprises:
an amplifier having an output coupled to the output of the bias stage;
a common capacitor coupled to the output of the biasing stage; and
a tenth transistor having a control terminal coupled to the output of the biasing stage.
17. The non-volatile memory of claim 12, wherein each memory cell of the plurality of memory cells comprises a floating gate transistor.
18. A method of reading non-volatile memory, the method comprising:
generating a bias voltage at a bias terminal;
during the pre-charge phase, the first phase is,
disconnecting a control terminal of a cascode transistor from the bias terminal, the cascode transistor coupled between a sense amplifier core and a bit line of the non-volatile memory;
disconnecting a local capacitor coupled to the control terminal of the cascode transistor from a reference terminal; and
limiting or reducing voltage overshoot at the control terminal of the cascode transistor by adjusting a voltage of a control terminal of a first transistor coupled between the local capacitor and the reference terminal after disconnecting the local capacitor from the reference terminal.
19. The method of claim 18, wherein disconnecting the control terminal of the cascode transistor from the bias terminal comprises: opening a first switch coupled between the bias terminal and a control terminal of the cascode transistor, the method further comprising:
receiving a read request; and
in response to the read request, the read request is transmitted,
opening the first switch;
closing a second switch coupled between a power supply terminal and the cascode transistor; and
closing a third switch coupled between the cascode transistor and the bit line.
20. The method of claim 19, wherein adjusting the voltage of the control terminal of the first transistor comprises: adjusting the voltage of the control terminal of the first transistor based on a voltage across the first switch.
Technical Field
The present invention relates generally to an electronic system and method, and in particular embodiments, to a floating boost precharge scheme for a sense amplifier.
Background
In memory devices, such as non-volatile memory (NVM) devices, sense amplifiers are typically used to determine (read) the state (e.g., 0 or 1) of a cell by measuring the current associated with the memory cell. Typically, a sense amplifier compares a current associated with a memory cell to a reference current. Such a current may be of the order of a few pA. Typically, a memory device reads (in parallel) words formed of logic values stored in a selected page of memory cells (e.g., containing 64 to 256 memory cells) simultaneously by using multiple sense amplifiers. Typically, a memory device includes sense amplifiers for each memory cell (e.g., word or page) to be read simultaneously.
During a read operation, the sense amplifier typically has its terminals held to receive the measurement current and the reference current at a predetermined read voltage. For example, in a non-volatile memory device including memory cells implemented with their floating gate Metal Oxide Semiconductor (MOS) transistors, a read voltage is used to bias selected memory cells for reading so that their MOS transistors are conductive or non-conductive according to a stored logic value.
In many applications of sense amplifiers precise control of the sense voltage is required. For example, in a non-volatile memory device, the sense voltage should be maintained at a certain value in order to be able to correctly distinguish the logic value stored in the selected memory cell without altering the state of the memory cell (i.e., without overwriting the memory cell). This may be particularly important when the value of the sense voltage is relatively low (e.g., < 1-2V).
To this end, the sense amplifier is typically equipped with a voltage regulator for regulating the sense voltage to limit possible variations from its desired value. A typical implementation of such a voltage regulator is to have transistors (for example, MOS type transistors) in a cascode configuration. Since the cascode driver is a low impedance driver, this structure allows the terminals of the sense amplifier to be preloaded to the sense voltage in a relatively fast manner during the precharge phase. The cascode structure also allows for efficient separation of the bit lines from the core of the sense amplifier, which allows for proper operation even when the sense amplifier is coupled to a load having a high capacitance, such as a column of memory cells in a non-volatile memory device. In particular, in a cascode configuration with fixed control (e.g., a gate-type cascode configuration), the sense voltage is regulated by controlling the transistors of the voltage regulator with a bias voltage of a constant value (provided by a bias stage common to all sense amplifiers).
Disclosure of Invention
According to an embodiment, a sensing structure includes: a sense amplifier core configured to compare the measurement current to a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between the second terminal of the local capacitor and a reference terminal;
and a control circuit coupled to the control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and to limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor after disconnecting the local capacitor from the reference terminal.
According to an embodiment, a non-volatile memory includes a plurality of memory cells arranged in rows and columns; a row decoder coupled to a plurality of memory cells via a plurality of word lines; a column decoder coupled to a plurality of memory cells via a plurality of bit lines; a bias stage configured to generate a bias voltage; and a plurality of sense amplifiers, wherein each sense amplifier includes a sense amplifier core configured to compare the measured current to a reference current; a cascode transistor coupled between the sense amplifier core and one of the plurality of bit lines; a switch coupled between an output of the biasing stage and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between the second terminal of the local capacitor and a reference terminal; and a control circuit coupled to the control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor; and limiting or reducing the voltage overshoot by adjusting the voltage of the control terminal of the first transistor after disconnecting the local capacitor from the reference terminal.
According to an embodiment, a method of reading a non-volatile memory includes: generating a bias voltage at a bias terminal; disconnecting a control terminal of a cascode transistor from a bias terminal during a precharge phase, the cascode transistor coupled between a sense amplifier core and a bit line of a non-volatile memory; disconnecting a local capacitor coupled to a control terminal of the cascode transistor from the reference terminal; and after disconnecting the local capacitor from the reference terminal, limiting or reducing a voltage overshoot at the control terminal of the cascode transistor by adjusting a voltage of the control terminal of the first transistor coupled between the local capacitor and the reference terminal.
Drawings
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates an NVM according to an embodiment of the present invention;
FIG. 2 illustrates a sensing structure of the NVM of FIG. 1, according to an embodiment of the present invention;
FIG. 3 shows a detail of the sensing structure of FIG. 2, in accordance with an embodiment of the present invention;
FIG. 4 shows a timing diagram illustrating signals associated with the sense structures of FIGS. 2 and 3 during a read operation in accordance with an embodiment of the present invention;
FIG. 5 shows details of the sense control circuit of FIG. 3 according to an embodiment of the invention;
FIG. 6 shows a timing diagram illustrating signals associated with the sense control circuit of FIG. 5 during a read operation in accordance with an embodiment of the present invention;
FIG. 7 illustrates waveforms of the NVM of FIG. 1 according to an embodiment of the present invention; and
FIG. 8 illustrates an embodiment method of reading a memory cell according to an embodiment of the invention.
Corresponding numerals and symbols in the various drawings generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate certain embodiments, letters indicating changes in the same structure, material, or process steps may be followed by reference numerals.
Detailed Description
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
The following description illustrates various specific details to provide a thorough understanding of several example embodiments according to the present description. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments. Reference in the specification to "an embodiment" means that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in one embodiment" that may be present at various points in the specification do not necessarily refer to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The invention is described in conjunction with embodiments in the specific context of an NVM device having one or more sense amplifiers. Embodiments of the present invention may be used in other types of memory. Some embodiments may be used in devices other than memory devices, which benefit from the use of sense amplifiers.
Embedded non-volatile memory (eNVM) technology is shrinking. The reduced cell size is generally associated with a reduction in the reference current used to sense the state (e.g., 0 or 1) of the NVM cell. Reduced cell size is also associated with low gain. The low measurement current and low cell gain make it difficult to distinguish the state (e.g., 0 or 1) of the NVM cell. Increasing the accuracy of the reference current helps the sense amplifier determine the state (e.g., 0 or 1) of the NVM cell.
For example, reduced cell size is also associated with increased cell degradation due to cell cycling (i.e., programming and erasing of the cells). For example, the voltage at the control terminal of the memory device transistor should be limited to a predetermined level to avoid transistor damage or degradation.
Meanwhile, demands for low read current consumption and high read speed (low access time) are increasing.
Read speed can be increased by controlling the cascode transistors using a closed loop scheme, where the feedback loop includes an inverter operating in the linear region. Operating the inverter in the linear region causes the inverter to dissipate current (e.g., from Vdd, through the high-side transistor, through the low-side transistor, to ground) that is not used to precharge the bit line.
Current consumption may be reduced by operating the cascode transistors in an open loop, such as described in U.S. patent No. 9,679,618, which is incorporated by reference herein in its entirety. However, known closed loop systems tend to be faster than known open loop systems because the closed loop system can cause a controlled overshoot at the gates of the cascode transistors coupled to the bit lines to be precharged.
In embodiments of the present invention, the NVM increases read speed by reducing the precharge phase time while maintaining low power consumption. The precharge phase time is reduced by causing an overshoot in the gate of the cascode transistor, which increases the charging speed of the bit line to be precharged. In some embodiments, the overshoot is controlled in a closed loop without using an inverter operating in the linear region.
FIG. 1 illustrates an NVM100 according to an embodiment of the present invention. The NVM100 may be embedded in, for example, a microcontroller or processor, a security device or other secure element, an Application Specific Integrated Circuit (ASIC), a Radio Frequency Identification (RFID) circuit, a memory device, or any other device or apparatus having integrated memory.
NVM100 includes a
During normal operation,
For a write operation, the data to be written is received by the I/O buffer and transferred to R/
For a read operation,
The
R/
The
Read operations typically involve a precharge phase and a read (sense) phase. With reference to fig. 2-7, details of the structures and methods associated with performing a read operation on the NVM100 are described.
FIG. 2 shows a
During a read operation, the word line WL is usediA group of
After the precharge phase, and after the voltage of the bit line BL associated with the selected
The biasing
As shown in fig. 2, the
The precharge phase typically takes a significant amount of time of the total access time. Therefore, reducing the time to precharge the bit line BL associated with the selected
In an embodiment, the pre-charge time is reduced by causing a controlled overshoot in the gate of the cascode transistor. The overshoot is controlled by using a sensing control circuit that adjusts the voltage of the gate of the first transistor coupled between a local capacitor and ground, wherein the local capacitor is connected to the gate of the cascode transistor. In some embodiments, the sensing control circuit controls the voltage of the first transistor based on a difference between the voltage at the gate of the cascode transistor and the bias voltage.
FIG. 3 shows details of a
As shown in fig. 3, the
When the NVM100 is not performing a read or write operation, the
At the beginning of the precharge phase,
If no overshoot limiting mechanism is used, the voltage VcascodeCan reach a value equal to Vdd ═ VbiasThe voltage of (c). During the precharge phase, the
At the beginning of the read phase, and on the bit line BLjAfter the read voltage VBL is reached, switch 318 is opened and switch 320 is closed, as shown in FIG. 4. At this time, the sense amplifier core 328 is connected to the
As shown in FIG. 3, signal S controls
The
As shown in fig. 3, the
Sense amplifier core 328 may be implemented in any manner known in the art. For example, some embodiments may use a differential amplifier to compare the measurement current Im with the reference current Iref and generate the output Vout. In some embodiments, the sense amplifier core 328 includes one or more latches. Other implementations are also possible.
The
It should be understood that the voltage V shown in FIG. 4324Are non-limiting examples of possible waveforms. Voltage V324Different waveform shapes may be exhibited, such as, for example, a linear ramp.
FIG. 5 shows details of the
As shown in fig. 5, the
During normal operation, the voltage VBIASPIs held at the bias voltage. In some embodiments, the voltage VBIASPAnd also to bias one or more transistors within the sense amplifier core 328.
Before the precharge phase begins, the voltage VNEQIs high as shown in fig. 6. When the voltage V isNEQWhen high,
At the beginning of the precharge phase,
Low voltage VNEQTransistors 504 and 506 are also turned on. With voltage VcascodeIncrease to above voltage VbiasTransistor 512 becomes more conductive and
With voltage V324Increasingly,
As shown in FIG. 6, in some embodiments, VcascodeAbove V during the read phasebias. During the read phase, V is due to charge sharing between the
Advantages of some embodiments include increasing read speed while maintaining low power consumption. Additional advantages include not propagating noise associated with precharging the bit lines to voltage V by disconnecting the gates of the cascode transistors from the bias stage during the precharge phasebias。
Fig. 7 shows waveforms of the NVM100 according to an embodiment of the present invention. Fig. 7 also shows the waveforms of the open loop implementation described in U.S. patent No. 9,679,618, which does not use
The voltage V of the NVM100 is shown by the
FIG. 8 illustrates an
During
During
During
Step 808 includes
During
During
During
Example embodiments of the present invention are summarized herein. Other embodiments may also be understood from the entire specification and claims submitted herein.
Example 1 a sensing structure includes a sense amplifier core configured to compare a measurement current to a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between the second terminal of the local capacitor and a reference terminal; and a control circuit coupled to the control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and to limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor after disconnecting the local capacitor from the reference terminal.
Example 2 the sensing structure of example 1, wherein the control circuit is configured to adjust a voltage of the control terminal of the first transistor based on a voltage across the switch.
Example 3 the sensing architecture of one of examples 1 or 2, wherein the control circuit includes a second transistor coupled between the second terminal of the local capacitor and the reference terminal; a third transistor coupled between the control terminal and the reference terminal of the first transistor; and a first terminal configured to receive a first voltage, wherein the first terminal is coupled to a control terminal of the second transistor and to a control terminal of the third transistor.
Example 4 the sensing structure of one of examples 1 to 3, wherein the control circuit further includes a fourth transistor having a control terminal coupled to the control terminal of the first transistor; a fifth transistor coupled between the power supply terminal of the control circuit and the fourth transistor, the fifth transistor having a control terminal coupled to the bias voltage node; and a sixth transistor coupled between the power supply terminal of the control circuit and the fourth transistor, the sixth transistor having a control terminal coupled to the control terminal of the cascode transistor.
Example 5 the sensing structure of one of examples 1 to 4, wherein the control circuit further includes a seventh transistor coupled between the power supply terminal of the control circuit and the fifth transistor, the seventh transistor having a control terminal coupled to the first terminal; and an eighth transistor coupled between the power supply terminal of the control circuit and the sixth transistor, the eighth transistor having a control terminal coupled to the first terminal.
Example 6 the sensing structure of one of examples 1 to 5, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NMOS transistors, and wherein the seventh transistor and the eighth transistor are PMOS transistors.
Example 7 the sensing architecture of one of examples 1 to 6, wherein the control circuit further includes a ninth transistor coupled between the power supply terminal of the control circuit and the fifth transistor, the ninth transistor having a control terminal configured to receive the second bias voltage and wherein the sense amplifier core is configured to receive the second bias voltage.
Example 8 the sensing structure of one of examples 1 to 7, wherein the control terminal of the fourth transistor is coupled to the drain terminal of the fifth transistor.
Example 9 the sensing structure of one of examples 1 to 8, further comprising a second switch coupled between the power supply terminal of the sensing structure and the cascode transistor; and a third switch coupled between the second switch and the sense amplifier core.
Example 10 the sensing architecture of one of examples 1 to 9, further comprising a bias stage configured to generate a bias voltage at a bias voltage node, wherein the bias stage comprises an amplifier having an output coupled to an output of the bias stage; a common capacitor coupled to an output of the bias stage; and a tenth transistor having a control terminal coupled to the output of the biasing stage.
Example 11 the sensing architecture of one of examples 1 to 10, wherein the cascode transistor is configured to be coupled to the memory cell as a load.
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