阅读说明：本技术 一种碳化硅肖特基钳位晶体管及其制备方法 (Silicon carbide Schottky clamp transistor and preparation method thereof ) 是由 温正欣 叶怀宇 张新河 陈施施 张国旗 于 2019-10-22 设计创作，主要内容包括：本发明涉及半导体器件领域,公开了一种碳化硅肖特基钳位晶体管,包括一N+型衬底集电区(1),位于所述N+型衬底集电区的一N型集电区(2)和一P型基区(3)；位于所述P型基区的一N+型发射区(4),所述N+型发射区(4)内设置一P+型基区接触区(5)；氧化隔离层(6),所述氧化隔离层(6)位于N+发射区(4)的侧壁和P型基区(3)以及N型集电区(2)的侧壁；本发明还提供了肖特基钳位晶体管的制备方法,利用碳化硅不同晶面的氧化速率不同,Ni金属和N型P型碳化硅形成接触现象不同的特性,大幅降低了器件制备工艺难度和成本。(The invention relates to the field of semiconductor devices, and discloses a silicon carbide Schottky clamp transistor which comprises an N + type substrate collecting region (1), an N type collecting region (2) and a P type base region (3), wherein the N type collecting region and the P type base region are positioned in the N + type substrate collecting region; an N + type emitter region (4) positioned on the P type base region, wherein a P + type base region contact region (5) is arranged in the N + type emitter region (4); the oxide isolation layer (6) is positioned on the side wall of the N + emitter region (4), the side wall of the P-type base region (3) and the side wall of the N-type collector region (2); the invention also provides a preparation method of the Schottky clamp transistor, and the difficulty and the cost of the device preparation process are greatly reduced by utilizing the characteristics that different crystal faces of silicon carbide have different oxidation rates and the contact phenomena of Ni metal and N-type P-type silicon carbide are different.)

1. A silicon carbide schottky clamp transistor device, characterized by: comprises that

The N + type substrate collector region (1), an N type collector region (2) and a P type base region (3) are positioned in the N + type substrate collector region; an N + type emitter region (4) positioned on the P type base region, wherein a P + type base region contact region (5) is arranged in the N + type emitter region (4); the oxide isolation layer (6) is positioned on the side wall of the N + emitter region (4), the side wall of the P-type base region (3) and the side wall of the N-type collector region (2); an emitter (7), wherein the emitter (7) is positioned above an N + type emitter region (4), a base (8) is positioned above a P + type base region contact region (5), a collector (9) covers the oxidation isolation layer (6) and the N + type substrate collector region (1), and the collector (9) partially covers the P type base region (3); the collector electrode (9) and the P-type base region (3) form Schottky contact, and the collector electrode (9) and the N + substrate collector region (1) form ohmic contact.

2. The silicon carbide schottky clamp transistor of claim 1, wherein: the N + type substrate collector region (1) is a silicon carbide N type highly doped substrate with the doping concentration of 1 multiplied by 10¹⁸cm^-3-1×10²¹cm^-3(ii) a The doping concentration of the N-type collector region (2) is 1 multiplied by 10¹⁵cm^-3-1×10¹⁸cm^-3And the thickness is 1-20 μm.

3. The silicon carbide schottky clamp transistor of claim 1, wherein: the doping concentration of the P-type base region (3) is 1 multiplied by 10¹⁵cm^-3-5×10¹⁷cm^-3The thickness is 0.5-3 μm; the N + emitting region (4) is a heavily doped region with the doping concentration of 1 × 10¹⁸cm^-3-1×10²¹cm^-3The thickness is 0.2-1 μm.

4. The silicon carbide schottky clamp transistor of claim 1, wherein: the depth of the P + contact region (5) is 0.1-0.5 μm, and the doping concentration is 5 × 10¹⁷cm^-3To 1X 10¹⁸cm^-3。

5. The silicon carbide schottky clamp transistor of claim 1, wherein: the thickness of the oxidation isolation layer (6) is 50nm-300 nm.

6. The silicon carbide schottky clamp transistor device of claim 1, wherein: the emitter (7) and the emitter region (4) form ohmic contact, and the emitter (7) is made of metal Ni; the base electrode (8) and the P + type base region contact region (5) form ohmic contact, and the base electrode (8) is made of Ti/Al; the material of the collector (9) is Ni.

7. A preparation method of a silicon carbide Schottky clamping device is characterized by comprising the following steps: comprises that

S1: growing an N/P/N + epitaxial layer on an N + type substrate current collecting region (1) of a 0001 surface;

s2: etching the epitaxial layer to the P-type base region (3), and forming an N + type emitter region (4) at one end of the P-type base region (3);

s3: etching the epitaxial layer to an N + type substrate current collection region (1);

s4: forming a P + type base region contact region (5) in the P type base region (3);

s5: forming an oxide layer isolation layer on the side wall of the N + emitter region (4), the side wall of the P-type base region (3) and the side wall of the N-type collector region (2) by a thermal oxidation method;

s6: sputtering metal and stripping to form an emitter (7), a base (8) and a collector (9).

8. The method of claim 7, wherein the schottky clamp device further comprises: the S5 is specifically S5.1, an oxide layer with {11-20} plane thickness higher than {0001} plane thickness is formed through different wet oxidation rates of the {0001} plane and the {11-20} plane of the epitaxial layer;

and S5.2, etching the oxide layer by using a BOE solution, removing the oxide layer on the {0001} surface, and reserving part of the oxide layer on the {11-20} surface to form an oxidation isolation layer (6).

9. The method of claim 7, wherein the method comprises: said S6 includes

S6.1, coating glue, photoetching and developing, sputtering metal Ni with the thickness of 200nm, and stripping to form an emitter and a collector;

s6.2, coating glue, photoetching and developing, sputtering metal Ti/Al with the thickness of 20nm/80nm respectively, and stripping to form a base electrode;

s6.3, performing rapid thermal annealing at 975 ℃ for 1 minute and 30 seconds to realize ohmic contact between the emitter and the N + emitter region, ohmic contact between the base and the P + base region contact region, ohmic contact between the collector and the N + substrate collector region, and Schottky contact between the collector and the P type base region.

10. The method of claim 7, wherein the method comprises: the mode for forming the P + type base region contact region (5) is an ion implantation method.

Technical Field

The invention belongs to the technical field of semiconductor power devices, and particularly relates to a silicon carbide Schottky clamp transistor and a preparation method thereof.

Background

TTL is an abbreviation of Transistor-Transistor Logic, and is mainly composed of BJT (Bipolar junction Transistor) and resistor, and the TTL circuit is a large class of digital integrated circuits. It is manufactured by adopting a bipolar process and has the characteristic of high speed. However, compared with the CMOS circuit, the TTL circuit has a larger power consumption and a relatively lower integration level.

STTL, schottky clamp transistor-transistor logic, is an improved TTL circuit. The schottky clamp transistor integrates a schottky diode between the base and collector regions of the bipolar junction transistor. When the transistor operates in the forward active region, the base/collector junction of the transistor is reverse biased and the integrated schottky diode is reverse biased and does not function in the circuit. When the transistor works in a saturation region, the junction of the base region/collector region is forward biased, and most of the excessive base current is shunted from the base region by the Schottky diode because the turn-on voltage of the Schottky diode is smaller than the built-in potential of the base region/collector region. Therefore, the number of the surplus minority carriers stored in the base region and the collector region is greatly reduced, the storage time is reduced, the switching speed of the device is improved, the working energy consumption of the device is reduced, and the total power consumption of the integrated circuit is further reduced.

With the progress of silicon carbide materials and semiconductor processing techniques, silicon carbide integrated circuits have been increasingly manufactured by utilizing the excellent material characteristics of silicon carbide. The TTL circuit is considered to be an ideal sic digital integrated circuit because the internal device structure of the TTL circuit is not a MOS structure with low yield and low high temperature reliability. By means of some characteristics of silicon carbide half-contact, a silicon carbide Schottky clamping diode with a simple structure and high performance can be developed and further applied to a silicon carbide STTL circuit.

Disclosure of Invention

Technical problem to be solved

The invention aims to provide a silicon carbide Schottky clamp transistor device which has lower turn-off power consumption, is simple in manufacturing process and is convenient for manufacturing a high-performance silicon carbide STTL integrated circuit.

(II) technical scheme

The technical scheme of the invention comprehensively considers the aspects of material characteristics, process difficulty, device performance, cost and the like, and provides a silicon carbide Schottky clamp transistor which comprises an N + type substrate current collecting region (1), an N type current collecting region (2) and a P type base region (3) which are positioned in the N + type substrate current collecting region; an N + type emitter region (4) positioned on the P type base region, wherein a P + type base region contact region (5) is arranged in the N + type emitter region (4); the oxide isolation layer (6) is positioned on the side wall of the N + emitter region (4), the side wall of the P-type base region (3) and the side wall of the N-type collector region (2); an emitter (7), wherein the emitter (7) is positioned above an N + type emitter region (4), a base (8) is positioned above a P + type base region contact region (5), a collector (9) covers the oxidation isolation layer (6) and the N + type substrate collector region (1), and the collector (9) partially covers the P type base region (3); the collector electrode (9) and the P-type base region (3) form Schottky contact, and the collector electrode (9) and the N + substrate collector region (1) form ohmic contact.

Preferably, the N + type substrate current collecting region (1) is a silicon carbide N type highly doped substrate with the doping concentration of 1 x 10¹⁸cm^-3-1×10²¹cm^-3(ii) a The doping concentration of the N-type collector region (2) is 1 multiplied by 10¹⁵cm^-3-1×10¹⁸cm^-3And the thickness is 1-20 μm.

Preferably, the doping concentration of the P-type base region (3) is 1 multiplied by 10¹⁵cm^-3-5×10¹⁷cm^-3The thickness is 0.5-3 μm; the N + emitting region (4) is a heavily doped region with the doping concentration of 1 × 10¹⁸cm^-3-1×10²¹cm^-3The thickness is 0.2-1 μm.

Preferably, the depth of the P + contact region (5) is 0.1 μm to 0.5 μm, and the doping concentration is 5 x 10¹⁷cm^-3To 1X 10¹⁸cm^-3。

Preferably, the thickness of the oxidation isolation layer (6) is 50nm-300 nm.

Preferably, the emitter (7) and the emitter region (4) form ohmic contact, and the material of the emitter (7) is metal Ni; the base electrode (8) and the P + type base region contact region (5) form ohmic contact, and the base electrode (8) is made of Ti/Al; the material of the collector (9) is Ni.

In another aspect of the invention, there is provided a method of fabricating a silicon carbide schottky clamp transistor, comprising the steps of:

s1: growing an N/P/N + epitaxial layer on the N + type substrate current collecting region (1) of the (0001) surface;

s2: etching the epitaxial layer to the P-type base region (3), and forming an N + type emitter region (4) at one end of the P-type base region (3);

s3: etching the epitaxial layer to an N + type substrate current collection region (1);

s4: forming a P + type base region contact region (5) in the P type base region (3);

s5: forming an oxide layer isolation layer on the side wall of the N + emitter region (4), the side wall of the P-type base region (3) and the side wall of the N-type collector region (2) by a thermal oxidation method;

s6: sputtering metal and stripping to form an emitter (7), a base (8) and a collector (9).

Preferably, S5 is specifically

S5.1, forming an oxide layer with thickness of {11-20} plane higher than thickness of {0001} plane through different wet oxidation rates of {0001} plane and {11-20} plane of the epitaxial layer;

and S5.2, etching the oxide layer by using a BOE solution, removing the oxide layer on the {0001} surface, and reserving part of the oxide layer on the {11-20} surface to form an oxidation isolation layer (6).

Since the oxidation rate of the {11-20} plane of silicon carbide is about three times that of the {0001} plane, after the oxide layer on the {0001} plane is completely removed, the oxide layer on the {11-20} plane remains, forming an oxide isolation layer (6).

Preferably, said S6 comprises

S6.1, coating glue, photoetching and developing, sputtering metal Ni with the thickness of 200nm, and stripping to form an emitter and a collector;

s6.2, coating glue, photoetching and developing, sputtering metal Ti/Al with the thickness of 20nm/80nm respectively, and stripping to form a base electrode;

s6.3, performing rapid thermal annealing at 975 ℃ for 1 minute and 30 seconds to realize ohmic contact between the emitter and the N + emitter region, ohmic contact between the base and the P + base region contact region, ohmic contact between the collector and the N + substrate collector region, and Schottky contact between the collector and the P type base region.

Preferably, the mode for forming the P + type base contact region (5) is an ion implantation method.

(III) advantageous effects

The invention designs a silicon carbide Schottky clamp transistor, wherein collector metal extends to the upper part of a base region and forms Schottky contact with the base region. When the transistor works in a saturation region, the junction of the base region/collector region is forward biased, and because the starting voltage of the Schottky diode formed by the collector metal and the base region is smaller than the built-in potential of the base region/collector region, most of the excessive base current is shunted from the base region by the Schottky diode. In the turn-off process, the number of the surplus minority carriers stored in the base region and the collector region is greatly reduced, the storage time is reduced, the switching speed of the device is improved, the working energy consumption of the device is reduced, and the total power consumption of the integrated circuit is further reduced.

The manufacturing process of the silicon carbide Schottky diode provided by the invention utilizes the different characteristics of the oxidation rates of the silicon carbide material on the {0001} plane and the {11-20} plane. Since the oxidation rate of silicon carbide on the {11-20} plane is about three times that of the {0001} plane, in the isotropic wet etching process, by accurately grasping the etching rate, it can be ensured that the oxide layer formed by thermal oxidation on the {0001} plane is etched and removed, while the oxide layer on the {11-20} plane is partially retained. The characteristic of the medium can conveniently manufacture the oxidation isolation layer of the device. The process reliability of the device is improved, and the process difficulty and the manufacturing cost are reduced.

The invention also utilizes the characteristic that Ni and N-type doped SiC are easy to form ohmic contact and form Schottky contact with P-type doped SiC, uses single collector metal, realizes the base region Schottky contact and collector ohmic contact of the Schottky clamp transistor, and reduces the process difficulty and the manufacturing cost.

Drawings

FIG. 1 is a schematic diagram of a silicon carbide Schottky clamp transistor according to the present invention;

FIG. 2 is a flow chart of a process for fabricating a silicon carbide Schottky clamp transistor according to the present invention;

FIG. 3 is a schematic diagram of silicon carbide Schottky clamp transistor processing step S1 according to the present invention;

FIG. 4 is a schematic diagram of silicon carbide Schottky clamp transistor processing step S2 according to the present invention;

FIG. 5 is a schematic diagram of silicon carbide Schottky clamp transistor processing step S3 according to the present invention;

FIG. 6 is a schematic diagram of silicon carbide Schottky clamp transistor processing step S4 according to the present invention;

FIG. 7 is a schematic diagram of silicon carbide Schottky clamp transistor processing step S5 according to the present invention;

FIG. 8 is a schematic diagram of silicon carbide Schottky clamp transistor processing step S6 according to the present invention;

the solar cell comprises an N + type substrate collector region 1, an N type collector region 2, a P type base region 3, an N + type emitter region 4, a P + type base region contact region 5, an oxidation isolation layer 6, an emitter 7, a base 8 and a collector 9.

Detailed Description

In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.