阅读说明：本技术 一种存储装置的控制方法 (Control method of storage device ) 是由 吴雯雯 于 2018-07-27 设计创作，主要内容包括：本发明公开了一种存储装置的控制方法,所述存储装置设置第一接口和第二接口并在两个接口上通过总线实现级联扩容,其内执行以下步骤：步骤S1：监控并获取总线上的数据信息；步骤S2：判断数据信息是否为本存储装置的存储任务,如果是所述存储装置执行该存储任务,否则将该存储任务通过总线转发。采用本发明的技术方案,通过在存储装置中内置级联控制算法从而能够通过标准接口级联,理论上能够无限扩展存储容量以满足各种应用的需求；同时采用标准接口级联也进一步降低了电路实现的复杂度。(The invention discloses a control method of a storage device, wherein the storage device is provided with a first interface and a second interface, and realizes cascade capacity expansion on the two interfaces through a bus, and the following steps are executed: step S1: monitoring and acquiring data information on a bus; step S2: and judging whether the data information is a storage task of the storage device, if so, executing the storage task by the storage device, and otherwise, forwarding the storage task through a bus. By adopting the technical scheme of the invention, the cascade control algorithm is built in the storage device, so that cascade can be realized through a standard interface, and theoretically, the storage capacity can be infinitely expanded to meet the requirements of various applications; meanwhile, the standard interface cascade is adopted, so that the complexity of circuit implementation is further reduced.)

1. A control method of a storage device is characterized in that the storage device is provided with a first interface and a second interface, and realizes cascade capacity expansion on the two interfaces through a bus, wherein the following steps are executed:

step S1: monitoring and acquiring data information on a bus;

step S2: and judging whether the data information is a storage task of the storage device, if so, executing the storage task by the storage device, and otherwise, forwarding the storage task through a bus.

2. The method of claim 1, wherein in step S2, when sending data via the bus, the memory device actively sends an instruction to preempt the control right of the bus and to perform chip selection via the instruction.

3. The method according to claim 1 or 2, wherein in step S1, before the storage device receives the data information, the ID information acquired first determines whether the storage device is a storage task of the storage device or a cascade link node thereof; if not, the data message is discarded from being received.

4. The method of controlling a memory device according to claim 3, wherein the signal transmitted on the bus includes at least command information and data information, the command information including at least ID information;

the ID information acquired from the bus is matched with the ID of the storage device to judge whether the storage device is a storage task of the storage device or the cascade link node of the storage device, and if the acquired ID information belongs to the cascade link node of the storage device, the storage device receives the data information and forwards the data information to the cascade node of the storage device through the bus.

5. The method for controlling the storage device according to claim 3, wherein the storage task is a data read-write operation or a parameter configuration;

when data is written in, the storage device stores the data information acquired by the bus in the corresponding storage unit; in the data reading operation, the storage device reads the data information of the storage unit of the corresponding address and sends the data information back through the bus.

6. The method for controlling a storage apparatus according to claim 5, further comprising the step of configuring the storage apparatus ID according to a parameter configuration instruction.

7. The method of claim 2, wherein implementing the chip selection by the instruction further comprises:

the storage device monitors ID information on the bus, and when receiving an instruction of a matched ID, the state of the data interface is converted from a high-impedance input state into a transmission state.

8. The method of claim 2, wherein the bus arbitration mechanism is used to implement bus control contention and release the bus after the memory device completes data transmission or reception.

9. The method according to claim 1 or 2, wherein the storage device includes at least a first interface, a second interface, a storage management unit, and at least one storage unit, wherein the storage unit is used for storing data; the first interface is used for accessing a front-stage main device or a storage device through a bus, the second interface is used for cascading a rear-stage storage device through the bus, and the storage management unit is connected with the first interface and the second interface and used for executing a storage task distributed to the storage device on the bus or sending data through the bus.

10. The method according to claim 9, wherein the first interface or the second interface is any one of PCIe, SATA, USB, SAS, IEEE1394, SD, eMMC, or SPI interface.