阅读说明：本技术 一种ssd主控中的raid核心计算装置及方法 (RAID core computing device and method in SSD master control ) 是由 王运哲 刘大铕 朱苏雁 刘奇浩 刘尚 孙中琳 王资川 于 2019-10-31 设计创作，主要内容包括：本发明公开一种SSD主控中的RAID核心计算装置及方法,所述装置包括状态机、计数器、写地址累加器、读地址累加器、异或运算单元、寄存器D1至D6、双口SRAM,利用状态机、双口SRAM、异或运算单元以及地址累加器电路单元实现RAID核心计算。工作时状态机根据内部状态输出读使能信号和写使能信号至双口SRAM,计数器根据数据处理轮数对循环次数进行递减操作递至状态机；写地址累加器和读地址累加器将实时写地址、读地址发送至双口SRAM,根据状态机状态实现对双口SRAM的读写。本发明在SSD主控芯片内部实现RAID计算,从而实现SSD读写数据恢复。(The invention discloses a RAID core calculation device and method in SSD master control, wherein the device comprises a state machine, a counter, a write address accumulator, a read address accumulator, an exclusive OR operation unit, registers D1-D6 and a double-port SRAM, and the RAID core calculation is realized by utilizing the state machine, the double-port SRAM, the exclusive OR operation unit and an address accumulator circuit unit. When the double-port SRAM works, the state machine outputs a read enabling signal and a write enabling signal to the double-port SRAM according to the internal state, and the counter performs descending operation on the cycle number according to the number of data processing rounds and transfers the cycle number to the state machine; the write address accumulator and the read address accumulator send real-time write addresses and read addresses to the double-port SRAM, and the double-port SRAM is read and written according to the state of the state machine. The invention realizes RAID calculation inside the SSD master control chip, thereby realizing SSD read-write data recovery.)

1. A RAID core computing apparatus in SSD master control, characterized in that: the system comprises a state machine, a counter, a write address accumulator, a read address accumulator, an exclusive OR operation unit, registers D1-D6 and a double-port SRAM;

the state of the state machine comprises IDLE, HDSHK, LDEN, DELAY, LOAD, RDEN, CALC and PIPE, wherein IDLE is an IDLE state, HDSHK is a handshake state of the module and an external module, LDEN is a state of waiting for data to start entering, DELY is a delayed one-beat state, LOAD is a state of continuously writing data to SRAM, RDEN is a read enabling state, CALC is a first stroke exclusive-or calculation state, PIPE is a state of continuously reading and writing SRAM and continuously exclusive-or calculation;

the input of the state machine is connected with clk, rst, start, req, ack and first signals, wherein the start signal is a control signal in an IDLE state, the req signal is a control signal in an HDSHK state, the first signal is a control signal in an LDEN state, and the clk and the rst are clock and reset signals; the state machine outputs a read enable signal and a write enable signal to the double-port SRAM according to the internal state, the counter is connected with the cycle number and performs decrement operation on the cycle number according to the number of data processing rounds, and the count value after decrement is transmitted to the state machine; the write address accumulator is connected with the write initial address, accumulates according to the beat number of the write data to obtain a real-time write address, and sends the real-time write address to the double-port SRAM; the read address accumulator is connected with the read initial address, accumulates the read initial address according to the read data beat number to obtain a real-time read address, and sends the real-time read address to the double-port SRAM; the double-port SRAM is provided with a data reading-in and reading-out interface; two paths for reading external data into the double-port SRAM are provided, wherein one path is written into the double-port SRAM after two-beat registration of the registers D1 and D2, and the other path is written into the double-port SRAM after one-beat registration of the register D1 and XOR calculation of data read out by the upper wheel and one-beat registration of the register D2; the effective signal of the input data passes through two-stage register of registers D3, D4 and draws down the write enable signal when the value is low, the last signal enters registers D5, D6 in turn to carry out two-stage register;

the counter records the cycle times, and after the specified times are finished, the cycle times are fed back to the state machine to enable the state machine to return to an IDLE state;

the write address accumulator accumulates write addresses in the LOAD and PIPE states and sends the accumulated write addresses to a write address port of the SRAM;

the read address accumulator accumulates read addresses in CALE and PIPE states and sends the read addresses to a read address port of the SRAM;

the XOR operation unit is responsible for XOR operation, namely XOR is carried out on the XOR result of the previous round read back from the SRAM and the data newly entering from the input port to obtain a new intermediate XOR result;

d1 registers one beat of input data, D2 registers one beat of result obtained by the XOR operation unit, D3 and D4 register two beats of effective signal of input data, D5 and D6 register two beats of last signal, and the double-port SRAM is responsible for temporarily storing the intermediate result of the XOR operation.

2. The RAID core computing apparatus in an SSD master of claim 1, wherein: during the first round of read-write operation, external data are written into the double-port SRAM after being registered by two beats of the registers D1 and D2, and during the second round of read-write operation to the last round of read-write operation, the external data are written into the double-port SRAM after being registered by one beat of the register D1, and after being subjected to XOR calculation with data read out by the previous round of read-write operation, the external data are written into the double-port SRAM by one beat of the register D2.

3. A RAID core calculation method in SSD master control is characterized in that: the method is based on the device of claim 1 and comprises the following steps:

s01), when the state machine is in IDLE state, if detecting that the external start signal is pulled high, transmitting the cycle number to the counter, and the state machine enters HDSHK state;

s02), when the state machine detects that the external req signal is pulled up in the HDSHK state, pulling up the ack feedback signal to complete handshaking; then judging whether the count value transmitted from the counter is the initial value of the circulation times or not, if so, executing the steps S03 to S05, starting the first round of circulation and only writing data to the double-port SRAM; if not, executing the steps S06 to S09, starting the second round to the last round of the cycle, and simultaneously performing read-write operation on the double-port SRAM;

s03), when detecting that the external first signal is pulled high in the LDEN state, the state machine indicates that effective data starts to enter, and the state machine enters a DELY state;

s04), loading the write initial address into the write address accumulator when the state machine is in a DELY state, and enabling the state machine to enter a LOAD state;

s05), when the state machine is in the LOAD state, the write enable signal output to the SRAM is pulled high, the input data is read into the address pointed by the write address accumulator in the SRAM after two-beat delay of D1 and D2, the write address accumulator continuously accumulates when normal flowing, the external data continuously enters, and the write enable signal is continuously high; when the pipeline is interrupted, the input data effective signal is low, the input data effective signal is delayed for two beats through D3 and D4, so that the write address accumulator stops accumulating, the write enable signal is pulled down, and the SRAM stops writing; when the running water continues, the write enable signal is pulled high again, the write address accumulator continues to accumulate until the last signal which is delayed by two beats through D5 and D6 is detected to be pulled high, which indicates that the first round of data is completely transmitted to the double-port SRAM, the counter is decremented by 1 to indicate that the 1 round of data processing is completed, and the state machine returns to the HDSHK state;

s06), when the state machine is in an RDEN state, pulling up a read enable signal of the SRAM, loading a read initial address to a read address accumulator, waiting for the pull-up of an external first signal, indicating that effective data starts to enter, and entering a CALC state by the state machine;

s07), when the state machine is in a CALC state, the read data in the SRAM and the external data delayed by one beat through the diner D1 enter an XOR operation unit to obtain an XOR result, the XOR result is stored in D2, the write initial address is loaded to a write address accumulator, the rd _ en signal of the SRAM is still pulled high, the read address accumulator is added with 1, and the state machine enters a PIPE state;

s08), pulling up a write enable signal of the SRAM by the state machine in a PIPE state, writing an exclusive OR result in a register D2 into an address pointed by a write address accumulator in the SRAM, adding 1 to the write address accumulator, pulling up an rd _ en signal of the SRAM, adding 1 to the read address accumulator, continuously accumulating the read and write address accumulator during normal running, continuously entering external data, and continuously keeping the read enable signal and the write enable signal high; when the pipeline is interrupted, the effective signal of the input data is low, the read address accumulator stops accumulating after D3 delays for one beat, the write address accumulator stops accumulating after D4 delays for one beat, the write signal is pulled down, and the SRAM is stopped being written; when the pipeline continues, the writing signal is pulled high again, the reading and writing address accumulator continues to accumulate until the last signal which is delayed by two beats through D5 and D6 is detected to be pulled high, the data in the round is completely XOR-finished with the data in the previous round, the result is loaded into the SRAM, and the counter is reduced by 1 to finish the data processing in the round 1;

s09), determining whether the counter count value is 0, if yes, the state machine returns to the IDLE state, if no, repeating steps S06 to S08 until the IDLE state is returned.

Technical Field

The invention relates to a RAID core computing device and method in SSD master control, belonging to the field of SSD data processing.

Background

In reading and writing the SSD, when data is read from the Flash granule, if ECC error correction fails and the read re-try operation fails to read correct data, how to recover the data needs to be considered. RAID technology can fully exploit the array advantages of storage chips, provide fault tolerance to ensure data security, and continue to operate when a problem occurs in a storage unit. That is, recovery of read and write data by the SSD of RAID data. The existing RAID is outside the SSD master control chip, and a RAID core computing device and a method which are inside the SSD master control chip are not available.

Disclosure of Invention

The invention aims to provide a device and a method for calculating a RAID core in SSD master control, which realize RAID calculation inside an SSD master control chip so as to realize SSD read-write data recovery.

In order to solve the technical problem, the technical scheme adopted by the invention is as follows: a RAID core computing device in SSD master control comprises a state machine, a counter, a write address accumulator, a read address accumulator, an exclusive OR operation unit, registers D1-D6 and a double-port SRAM;

the state of the state machine comprises IDLE, HDSHK, LDEN, DELAY, LOAD, RDEN, CALC and PIPE, wherein IDLE is an IDLE state, HDSHK is a handshake state of the module and an external module, LDEN is a state of waiting for data to start entering, DELY is a delayed one-beat state, LOAD is a state of continuously writing data to SRAM, RDEN is a read enabling state, CALC is a first stroke exclusive-or calculation state, PIPE is a state of continuously reading and writing SRAM and continuously exclusive-or calculation;

the input of the state machine is connected with clk, rst, start, req, ack and first signals, wherein the start signal is a control signal in an IDLE state, the req signal is a control signal in an HDSHK state, the first signal is a control signal in an LDEN state, and the clk and the rst are clock and reset signals; the state machine outputs a read enable signal and a write enable signal to the double-port SRAM according to the internal state, the counter is connected with the cycle number and performs decrement operation on the cycle number according to the number of data processing rounds, and the count value after decrement is transmitted to the state machine; the write address accumulator is connected with the write initial address, accumulates according to the beat number of the write data to obtain a real-time write address, and sends the real-time write address to the double-port SRAM; the read address accumulator is connected with the read initial address, accumulates the read initial address according to the read data beat number to obtain a real-time read address, and sends the real-time read address to the double-port SRAM; the double-port SRAM is provided with a data reading-in and reading-out interface; two paths for reading external data into the double-port SRAM are provided, wherein one path is written into the double-port SRAM after two-beat registration of the registers D1 and D2, and the other path is written into the double-port SRAM after one-beat registration of the register D1 and XOR calculation of data read out by the upper wheel and one-beat registration of the register D2; the effective signal of the input data passes through two-stage register of registers D3, D4 and draws down the write enable signal when the value is low, the last signal enters registers D5, D6 in turn to carry out two-stage register;

the counter records the cycle times, and after the specified times are finished, the cycle times are fed back to the state machine to enable the state machine to return to an IDLE state;

the write address accumulator accumulates write addresses in the LOAD and PIPE states and sends the accumulated write addresses to a write address port of the SRAM;

the read address accumulator accumulates read addresses in CALE and PIPE states and sends the read addresses to a read address port of the SRAM;

the XOR operation unit is responsible for XOR operation, namely XOR is carried out on the XOR result of the previous round read back from the SRAM and the data newly entering from the input port to obtain a new intermediate XOR result;

d1 registers one beat of input data, D2 registers one beat of result obtained by the XOR operation unit, D3 and D4 register two beats of effective signal of input data, D5 and D6 register two beats of last signal, and the double-port SRAM is responsible for temporarily storing the intermediate result of the XOR operation.

Further, during the first round of read-write operation, the external data is written into the dual-port SRAM after being registered by two beats in the registers D1 and D2, and during the second round of read-write operation to the last round of read-write operation, the external data is written into the dual-port SRAM after being registered by one beat in the register D1 and being subjected to xor calculation with the data read out in the previous round of read-write operation, and then being registered by one beat in the register D2.

The method also discloses a RAID core calculation method in the SSD master control, and the method is based on the device and comprises the following steps:

s01), when the state machine is in IDLE state, if detecting that the external start signal is pulled high, transmitting the cycle number to the counter, and the state machine enters HDSHK state;

s02), when the state machine detects that the external req signal is pulled up in the HDSHK state, pulling up the ack feedback signal to complete handshaking; then judging whether the count value transmitted from the counter is the initial value of the circulation times or not, if so, executing the steps S03 to S05, starting the first round of circulation and only writing data to the double-port SRAM; if not, executing the steps S06 to S09, starting the second round to the last round of the cycle, and simultaneously performing read-write operation on the double-port SRAM;

s03), when detecting that the external first signal is pulled high in the LDEN state, the state machine indicates that effective data starts to enter, and the state machine enters a DELY state;

s04), loading the write initial address into the write address accumulator when the state machine is in a DELY state, and enabling the state machine to enter a LOAD state;

s05), when the state machine is in the LOAD state, the write enable signal output to the SRAM is pulled high, the input data is read into the address pointed by the write address accumulator in the SRAM after two-beat delay of D1 and D2, the write address accumulator continuously accumulates when normal flowing, the external data continuously enters, and the write enable signal is continuously high; when the pipeline is interrupted, the input data effective signal is low, the input data effective signal is delayed for two beats through D3 and D4, so that the write address accumulator stops accumulating, the write enable signal is pulled down, and the SRAM stops writing; when the running water continues, the write enable signal is pulled high again, the write address accumulator continues to accumulate until the last signal which is delayed by two beats through D5 and D6 is detected to be pulled high, which indicates that the first round of data is completely transmitted to the double-port SRAM, the counter is decremented by 1 to indicate that the 1 round of data processing is completed, and the state machine returns to the HDSHK state;

s06), when the state machine is in an RDEN state, pulling up a read enable signal of the SRAM, loading a read initial address to a read address accumulator, waiting for the pull-up of an external first signal, indicating that effective data starts to enter, and entering a CALC state by the state machine;

s07), when the state machine is in a CALC state, the read data in the SRAM and the external data delayed by one beat through the diner D1 enter an XOR operation unit to obtain an XOR result, the XOR result is stored in D2, the write initial address is loaded to a write address accumulator, the rd _ en signal of the SRAM is still pulled high, the read address accumulator is added with 1, and the state machine enters a PIPE state;

s08), pulling up a write enable signal of the SRAM by the state machine in a PIPE state, writing an exclusive OR result in a register D2 into an address pointed by a write address accumulator in the SRAM, adding 1 to the write address accumulator, pulling up an rd _ en signal of the SRAM, adding 1 to the read address accumulator, continuously accumulating the read and write address accumulator during normal running, continuously entering external data, and continuously keeping the read enable signal and the write enable signal high; when the pipeline is interrupted, the effective signal of the input data is low, the read address accumulator stops accumulating after D3 delays for one beat, the write address accumulator stops accumulating after D4 delays for one beat, the write signal is pulled down, and the SRAM is stopped being written; when the pipeline continues, the writing signal is pulled high again, the reading and writing address accumulator continues to accumulate until the last signal which is delayed by two beats through D5 and D6 is detected to be pulled high, the data in the round is completely XOR-finished with the data in the previous round, the result is loaded into the SRAM, and the counter is reduced by 1 to finish the data processing in the round 1;

s09), determining whether the counter count value is 0, if yes, the state machine returns to the IDLE state, if no, repeating steps S06 to S08 until the IDLE state is returned.

The invention has the beneficial effects that: the method has the advantages that: when the SRAM is operated, the data of the address corresponding to the current clock cycle is read out, and the XOR calculation result of the address corresponding to the previous clock cycle is written in, so that each clock cycle has the read-write operation on the SRAM and the XOR operation on the data (respectively, the data from the outside and the data read out from the SRAM). The method realizes the flow operation of batch data, and ensures that the output of the exclusive or result is only delayed by two clock periods compared with the input of the original data.

The method has the advantages that: the XOR operation unit is preceded and succeeded by two groups of registers D1 and D2, and enough timing margin is left, so that the whole device can run to a faster clock frequency.

The method has the advantages that: due to the data _ in _ vld signal and the relevant logic thereof, the read-write operation of the internal SRAM can be suspended, i.e. the externally entered data is allowed to be interrupted for continuous transmission, and the data correctness under the condition is ensured.

Drawings

FIG. 1 is a functional block diagram of a RAID core computing device.

Detailed Description

The invention is further described with reference to the following figures and specific embodiments.