阅读说明：本技术 数据包传输装置及系统 (Data packet transmission device and system ) 是由 吴志伟 陈远珍 王俊杰 于 2018-07-26 设计创作，主要内容包括：一种数据包传输装置及系统,数据包传输装置包括：CPU；数据包传输加速器,适于提供输入接口和输出接口,所述输入接口接收发送设备发送的数据包的数据包描述符,所述输出接口输出所述数据包描述符至接收设备,以供所述接收设备根据所述数据包描述符获取所述数据包,所述发送设备和所述接收设备选自输入输出设备和所述CPU。本发明技术方案可以降低CPU的负载,提升CPU的性能。(A data packet transmission device and system, the data packet transmission device includes: a CPU; the data packet transmission accelerator is suitable for providing an input interface and an output interface, the input interface receives a data packet descriptor of a data packet sent by a sending device, the output interface outputs the data packet descriptor to a receiving device, the receiving device obtains the data packet according to the data packet descriptor, and the sending device and the receiving device are selected from an input/output device and the CPU. The technical scheme of the invention can reduce the load of the CPU and improve the performance of the CPU.)

1. A packet transmission apparatus, comprising:

CPU；

the data packet transmission accelerator is suitable for providing an input interface and an output interface, the input interface receives a data packet descriptor of a data packet sent by a sending device, the output interface outputs the data packet descriptor to a receiving device, the receiving device obtains the data packet according to the data packet descriptor, and the sending device and the receiving device are selected from an input/output device and the CPU.

2. The packet transfer device according to claim 1, further comprising a peripheral access manager;

and when the input and output equipment can not directly access the input interface and the output interface of the data packet transmission accelerator, the peripheral access manager is suitable for adapting the interface of the input and output equipment and the input interface and the output interface of the data packet transmission accelerator.

3. The packet transfer device of claim 1, wherein the input interface comprises a first FIFO and a second FIFO; the first FIFO receives the descriptor of the data packet sent by the sending equipment, and the sender updates the write pointer of the first FIFO; after the receiving device uses the data packet descriptor, the data packet transmission accelerator writes the data packet descriptor into the second FIFO and updates a write pointer of the second FIFO.

4. The packet transfer device according to claim 3, wherein the output interface comprises a third FIFO and a fourth FIFO; the packet transfer accelerator reads the packet descriptor from the first FIFO, updates a read pointer of the first FIFO, writes the packet descriptor into the third FIFO, and updates a write pointer of the third FIFO; and after the use of the data packet descriptor is finished, the receiver writes the data packet descriptor into the fourth FIFO and updates a write pointer of the fourth FIFO.

5. The apparatus according to claim 4, wherein the packet descriptor use completion indicates that a use completion signal fed back by the receiving device is received.

6. The apparatus of claim 4, wherein when the packet accelerator writes the packet descriptor into the third FIFO, if the third FIFO is full, the packet accelerator updates an error code in the packet descriptor to a predetermined value to indicate a transmission failure, writes the updated packet descriptor into the second FIFO, and updates a write pointer of the second FIFO.

7. The apparatus according to claim 4, wherein the packet transfer accelerator notifies the sending device to generate an interrupt when the depth of the third FIFO reaches a preset entry threshold.

8. The apparatus according to claim 4, wherein the packet transmission accelerator notifies the receiving device to generate an interrupt after the depth of the first FIFO reaches a preset interrupt threshold; or notifying the receiving device to generate an interrupt after a preset time period from empty to non-empty of the third FIFO.

9. The packet transfer device according to claim 3, wherein the output interface comprises a third FIFO and a fourth FIFO; when the receiving party is an embedded device or a CPU, the output mode of the data packet transmission accelerator is a DMA mode; in the DMA mode, the packet transfer accelerator reads a receive descriptor and a memory address in the fourth FIFO, where the memory address is an effective address of an embedded device or a CPU, copies the packet descriptor to the receive descriptor and copies effective data pointed by the packet descriptor to a memory pointed by the memory address, writes the receive descriptor in the third FIFO, and writes the packet descriptor in the second FIFO.

10. The apparatus according to claim 1, wherein the receiving device generates an interrupt immediately after receiving the data packet if an interrupt in the data descriptor of the data packet is a predetermined value.

11. The apparatus according to claim 1, wherein the packet transmission accelerator determines the identifier of the receiving device according to the identifier of the sending device, and the identifiers of the sending device and the receiving device correspond one to one; or, the data packet transmission accelerator determines the receiving device according to a data packet descriptor of the data packet, where the data packet descriptor includes an identifier of a sending device and an identifier of a receiving device; or, the packet transmission accelerator matches the content of the packet with a preset packet rule table to determine the receiving device.

12. The apparatus according to claim 1, wherein the packet descriptor includes a start address of a memory block in which the packet is located, an offset of a valid data address of the packet from the start address, a valid length of the packet, an identifier of a transmitting device that transmits the packet, an identifier of a receiving device that receives the packet, and/or a multiplexing identifier for stream multiplexing.

13. A data packet transmission system, comprising:

a transmitting device adapted to transmit the packet descriptor;

a receiving device adapted to receive the packet descriptor;

a data packet transmission device as claimed in any one of claims 1 to 12.

14. The data packet transmission system of claim 13, wherein the sending device and the receiving device are selected from the group consisting of: the CPU, the USB, the SDIO, the PCIE and the modem.

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a data packet transmission apparatus and system.

Background

Some packet Input/Output devices such as Universal Serial Bus (USB), Secure Digital Input/Output (SDIO), high speed serial computer expansion Bus (PCIE), etc. are usually stored in the computer apparatus, and the computer apparatus may further include a MODEM (MODEM) if necessary. The data packets interact with a Central Processing Unit (CPU) through these devices. In some scenarios, data packets need to be transmitted from some of the devices to another device.

Disclosure of Invention

The technical problem solved by the invention is how to reduce the load of the CPU and improve the performance of the CPU.

To solve the above technical problem, an embodiment of the present invention provides a data packet transmission device, including: a CPU; the data packet transmission accelerator is suitable for providing an input interface and an output interface, the input interface receives a data packet descriptor of a data packet sent by a sending device, the output interface outputs the data packet descriptor to a receiving device, the receiving device obtains the data packet according to the data packet descriptor, and the sending device and the receiving device are selected from an input/output device and the CPU.

Optionally, the data packet transmission apparatus further includes a peripheral access manager; and when the input and output equipment can not directly access the input interface and the output interface of the data packet transmission accelerator, the peripheral access manager is suitable for adapting the interface of the input and output equipment and the input interface and the output interface of the data packet transmission accelerator.

Optionally, the input interface includes a first FIFO and a second FIFO; the first FIFO receives the descriptor of the data packet sent by the sending equipment, and the sender updates the write pointer of the first FIFO; and after the receiver uses the data packet descriptor, the data packet transmission accelerator writes the data packet descriptor into the second FIFO and updates a write pointer of the second FIFO.

Optionally, the output interface includes a third FIFO and a fourth FIFO; the packet transfer accelerator reads the packet descriptor from the first FIFO, updates a read pointer of the first FIFO, writes the packet descriptor into the third FIFO, and updates a write pointer of the third FIFO; and after the use of the data packet descriptor is finished, the receiver writes the data packet descriptor into the fourth FIFO and updates a write pointer of the fourth FIFO.

Optionally, the completion of the use of the packet descriptor means that a use completion signal fed back by the receiving device is received.

Optionally, when the packet transmission accelerator writes the packet descriptor into the third FIFO, if the third FIFO is full, the packet transmission accelerator updates an error code in the packet descriptor to a preset value to indicate a transmission failure, writes the updated packet descriptor into the second FIFO, and updates a write pointer of the second FIFO.

Optionally, when the depth of the third FIFO reaches a preset entry threshold, the packet transmission accelerator notifies the sending device of generating an interrupt.

Optionally, the output interface includes a third FIFO and a fourth FIFO; when the receiving party is an embedded device or a CPU, the output mode of the data packet transmission accelerator is a DMA mode; in the DMA mode, the packet transfer accelerator reads a receive descriptor and a memory address in the fourth FIFO, where the memory address is an effective address of an embedded device or a CPU, copies the packet descriptor to the receive descriptor and copies effective data pointed by the packet descriptor to a memory pointed by the memory address, writes the receive descriptor in the third FIFO, and writes the packet descriptor in the second FIFO.

Optionally, the packet transmission accelerator notifies the receiving device to generate an interrupt after the depth of the first FIFO reaches a preset interrupt threshold; or notifying the receiving device to generate an interrupt after a preset time period from empty to non-empty of the third FIFO.

Optionally, after the receiving device receives the data packet, if an interrupt symbol in the data descriptor of the data packet is a preset value, the receiving device immediately generates an interrupt.

Optionally, the data packet transmission accelerator determines the identifier of the receiving device according to the identifier of the sending device, where the identifier of the sending device corresponds to the identifier of the receiving device one to one; or, the data packet transmission accelerator determines the receiving device according to a data packet descriptor of the data packet, where the data packet descriptor includes an identifier of a sending device and an identifier of a receiving device; or, the packet transmission accelerator matches the content of the packet with a preset packet rule table to determine the receiving device.

Optionally, the packet descriptor includes a start address of the memory block where the packet is located, an offset of an effective data address of the packet with respect to the start address, an effective length of the packet, an identifier of a sending device sending the packet, an identifier of a receiving device receiving the packet, and/or a multiplexing identifier for multiplexing data streams.

In order to solve the above technical problem, an embodiment of the present invention further discloses a data packet transmission system, where the data packet transmission system includes: a transmitting device adapted to transmit the packet descriptor; a receiving device adapted to receive the packet descriptor; the data packet transmission device.

Optionally, the sending device and the receiving device are selected from: the CPU, the USB, the SDIO, the PCIE and the modem.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

the data packet transmission device of the technical scheme of the invention comprises a CPU; the data packet transmission accelerator is suitable for providing an input interface and an output interface, the input interface receives a data packet descriptor of a data packet sent by a sending device, the output interface outputs the data packet descriptor to a receiving device, the receiving device obtains the data packet according to the data packet descriptor, and the sending device and the receiving device are selected from an input/output device and the CPU. In the technical scheme of the invention, the data transmission between the input and output devices can be realized without the participation of a CPU by arranging the data packet transmission accelerator; therefore, when the data flow is large, the load of the CPU is not increased, higher data flow can be supported under the same CPU resource, and the performance of the CPU is improved. In addition, by setting the data packet transmission accelerator, the data packet transmission between the input/output device and the CPU needs to be performed via the data packet transmission accelerator, and compared with the case where the data transmission is directly performed between the input/output device and the CPU, the number of CPU interrupts can be reduced, the service processing capability of the CPU can be improved, and the CPU performance can be further improved.

Furthermore, the data packet transmission device of the technical scheme of the invention comprises a peripheral access manager; and when the input and output equipment can not directly access the input interface and the output interface of the data packet transmission accelerator, the peripheral access manager is suitable for adapting the interface of the input and output equipment and the input interface and the output interface of the data packet transmission accelerator. In the technical scheme of the invention, the peripheral access manager is connected with the data packet transmission accelerator, and can read data from an output interface of the data packet transmission accelerator and write data from an input interface of the data packet transmission accelerator; the access manager is connected with the input and output equipment, can receive and send description information of the data packet, and can encapsulate and analyze transmission data according to a transport layer protocol so as to adapt to an interface of the input and output equipment and an input interface and an output interface of the data packet transmission accelerator, thereby realizing data transmission between the input and output equipment and the data packet transmission accelerator.

Further, the input interface comprises a first FIFO and a second FIFO; the output interface includes a third FIFO and a fourth FIFO. Because the data in the FIFO are written in and read out in sequence, the technical scheme of the invention can ensure that the reading and writing sequence of the second FIFO cannot be influenced by the reading and writing sequence of the first FIFO and the reading and writing sequence of the fourth FIFO cannot be influenced by the third FIFO by respectively setting the input interface and the output interface as the two FIFOs, thereby reducing the number of interrupt services in the data transmission process and improving the data transmission efficiency.

Further, the output interface comprises a third FIFO and a fourth FIFO; and when the receiving party is an embedded device or a CPU, the output mode of the data packet transmission accelerator is a DMA mode. Because the embedded device and the CPU have own data memory, in the technical scheme of the invention, the effective data can be copied to the memory pointed by the memory address by the data packet transmission accelerator in the DMA mode, and the memory address is the effective address of the embedded device or the CPU, thereby being beneficial to the embedded device or the CPU to manage the data; meanwhile, in the DMA mode, the data copying of the CPU is avoided, and the expense of the CPU is saved.

Drawings

Fig. 1 is a schematic structural diagram of a data packet transmission apparatus according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another data packet transmission apparatus according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of an input interface according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of an output interface according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a data packet transmission system according to an embodiment of the present invention.

Detailed Description

As described in the background art, if the method in the prior art is used to transmit the data packet, under the condition of a particularly large data traffic, the CPU may need a large amount of time to process the interrupt of the input/output device and other related transactions, and on one hand, the processing capability of the CPU may become a bottleneck of the data traffic processing capability of the computer device; on the other hand, to meet the requirement of high-speed data packet transmission, a CPU requiring high performance may bring more overhead of power consumption.

In the technical scheme of the invention, the data transmission between the input and output devices can be realized without the participation of a CPU by arranging the data packet transmission accelerator; therefore, when the data flow is large, the load of the CPU is not increased, higher data flow can be supported under the same CPU resource, and the performance of the CPU is improved. In addition, by setting the data packet transmission accelerator, the data packet transmission between the input/output device and the CPU needs to be performed via the data packet transmission accelerator, and compared with the case where the data transmission is directly performed between the input/output device and the CPU, the number of CPU interrupts can be reduced, the service processing capability of the CPU can be improved, and the CPU performance can be further improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 1 is a schematic structural diagram of a data packet transmission apparatus according to an embodiment of the present invention.

The data packet transmission device 10 in this embodiment may be embedded in any implementable intelligent terminal device, such as a mobile phone, a computer device, a tablet computer, a router, and the like. Specifically, the packet transmission device 10 may be a System On Chip (SOC) and may be used in any practicable operating System.

The packet forwarding device 10 shown in fig. 1 may include a CPU101 and a packet forwarding accelerator 102.

The packet transport accelerator 102 is adapted to provide an input interface and an output interface, the input interface receives a packet descriptor of a packet sent by the sending device 103, the output interface outputs the packet descriptor to the receiving device 104, so that the receiving device can obtain the packet according to the packet descriptor, and the sending device and the receiving device are selected from an input/output device and the CPU 101. Generally, the transmitting device and the receiving device are different devices. For example, one of them is an input-output device, and the other is the CPU 101; or, the sending device and the receiving device are different input and output devices.

In this embodiment, an input interface of a Packet Transfer Accelerator (PTA) 102 may be connected to the sending device 103, and an output interface may be connected to the receiving device 104. The sending device 103 may send the packet descriptor to the packet transport accelerator 102 via the input interface; the packet transport accelerator 102 sends the packet descriptor to the receiving device 104 through the output interface.

The packet descriptor may be related information of the packet, for example, the packet descriptor may point to an actual storage address of the packet, the packet descriptor may also be a packet size, and the packet descriptor may also indicate information of a source device that transmits the packet and information of a destination device that receives the packet, that is, information of the transmitting device 103 and information of the receiving device 104.

In contrast to the prior art in which data between two input/output devices needs to be forwarded via the CPU, in the present embodiment, data between two input/output devices is forwarded through the packet transport accelerator 102.

Compared with the prior art in which the input/output device and the CPU directly transmit data and the CPU generates an interrupt each time the CPU receives data, in this embodiment, the input/output device and the CPU forward data through the packet transmission accelerator 102, and if the rate at which the CPU reads data is equivalent to the rate at which the input/output device inputs data, the data can be transmitted without generating an interrupt.

Specifically, the packet transport accelerator 102 may be implemented by an application-Specific integrated Specific Circuit (AISC).

By arranging the data packet transmission accelerator 102, data transmission between input and output devices can be realized without the participation of a CPU; therefore, when the data flow is large, the load of the CPU is not increased, higher data flow can be supported under the same CPU resource, and the performance of the CPU is improved. In addition, by setting the data packet transmission accelerator, the data packet transmission between the input/output device and the CPU needs to be performed via the data packet transmission accelerator, and compared with the case where the data transmission is directly performed between the input/output device and the CPU, the number of CPU interrupts can be reduced, the service processing capability of the CPU can be improved, and the CPU performance can be further improved.

Referring to fig. 2, the packet transmission device 10 may further include a Peripheral Access Manager (PAM) 105.

Wherein the peripheral access manager 105 is adapted to adapt the interface of the input/output device to the input interface and the output interface of the packet transport accelerator when the input/output device cannot directly access the input interface and the output interface of the packet transport accelerator 102.

In the embodiment of the present invention, the peripheral access manager 105 is connected to the packet transfer accelerator, and can read data from the output interface of the packet transfer accelerator and write data from the input interface of the packet transfer accelerator; the access manager is connected with the input and output equipment, can receive and send description information of the data packet, and can encapsulate and analyze transmission data according to a transport layer protocol so as to adapt to an interface of the input and output equipment and an input interface and an output interface of the data packet transmission accelerator, thereby realizing data transmission between the input and output equipment and the data packet transmission accelerator.