阅读说明：本技术 一种基于fpga的中断延时计数系统及方法 (FPGA-based interrupt delay counting system and method ) 是由 王峰 于 2019-09-19 设计创作，主要内容包括：本发明提出的一种基于FPGA的中断延时计数系统及方法,从外设中断触发,一直到主机处理完中断服务程序,中断延时计数器能准确计算出主机处理中断的时长。计算的结果也不需要通过主机告知对应中断模块,中断模块直接就可以从该延时计数器获得对应的时长。(The interrupt delay counting system and method based on the FPGA can accurately calculate the interrupt time length of the host from the triggering of peripheral interrupt until the host processes the interrupt service program. The calculated result does not need to inform the corresponding interrupt module through the host, and the interrupt module can directly obtain the corresponding duration from the delay counter.)

1. An interrupt delay counting system based on FPGA comprises a host and a plurality of peripherals, wherein the peripherals respectively send interrupt request signals to the host;

the interrupt latency counter includes: the system comprises a configuration module, a control module and a counting module, wherein the configuration module and the control module are respectively connected with the counting module, the configuration module, the control module and the counting module are respectively connected with a host, and the counting module is connected with an external device;

the configuration module is used for receiving configuration information of a host, wherein the configuration information comprises clock frequency and interrupt types of peripheral equipment;

the control module is used for controlling the counting action of the counting module;

and the counting module counts the interrupt requests of each peripheral according to the configuration information of the configuration module and the control information of the control module, and calculates the time for the host to process the interrupt service program according to the count value.

2. The FPGA-based interrupt latency counter system of claim 1, wherein the interrupt types of the peripheral device comprise: level interrupts and edge interrupts.

3. The FPGA-based interrupt delay counting system of claim 1, wherein the counting module comprises a plurality of counting units, each counting unit is connected with a peripheral device respectively and is used for receiving an interrupt request signal of the peripheral device.

4. The FPGA-based interrupt latency counting system of claim 3, wherein the control module controls the counting action of the counting module to comprise: the control module controls the counting unit in the counting module to start and stop counting corresponding to the interruption.

5. The FPGA-based interrupt delay counting system of claim 1, wherein the counting module starts counting when receiving the interrupt request signal, and stops counting when the host processes the interrupt service routine and receives the configuration information sent by the configuration module; the time for the host to process the interrupt service routine is obtained by multiplying the value by the clock frequency.

6. An interrupt delay counting method based on FPGA is characterized by comprising the following steps:

the host writes configuration information into a configuration module, wherein the configuration information comprises clock frequency and interrupt type of each peripheral;

the host writes control information into the control module, wherein the control information comprises interruption start-stop information and shielding information;

the configuration module sends the configuration information to the counting module, and the control module sends the control information to the counting module;

a counting unit in the counting module starts counting after detecting that the interrupt request signal is valid;

after the interrupt request stops, the counting unit stops counting;

the counting unit calculates the time of the host for processing the interrupt service program according to the counting value and writes the time data into the storage unit of the counting module.

7. The FPGA-based interrupt latency counting method of claim 6, wherein the interrupt type of the peripheral device comprises: level interrupts and edge interrupts.

8. The FPGA-based interrupt latency counting method of claim 7, wherein the stopping counting by the counting unit after the interrupt request is stopped comprises: and if the interrupt type is level interrupt, stopping the terminal immediately after the terminal request signal is invalid.

9. The FPGA-based interrupt latency counting method of claim 7, wherein the stopping counting by the counting unit after the interrupt request is stopped comprises: if the interrupt type is edge interrupt, after the host computer processes the interrupt service program, the completion information is written into the control module, and the control module controls the counting module to stop counting.

10. The FPGA-based interrupt latency counting method of claim 6, wherein the calculating, by the counting unit, the time for the host to process the interrupt service routine according to the count value comprises: the counting unit multiplies the clock frequency by the value to obtain the time for the host to process the interrupt service program.

Technical Field

The invention relates to the technical field of computers, in particular to an interrupt delay counting system and method based on an FPGA.

Background

With the increasingly widespread application of heterogeneous acceleration, the accelerator cards based on the FPGA are also rapidly developed. The accelerator card FPGA is connected with the server host through the PCIE interface, the server host sends data needing to be accelerated to the accelerator card FPGA through the PCIE interface, and the accelerator card FPGA returns related data through the PCIE interface after processing is completed.

In the whole system, a plurality of peripheral devices need to send interrupts to the host computer, and the host computer executes an interrupt service program to process the interrupts. While some devices are delay sensitive, in some specific applications, it is necessary to know the length of time that the host processes the interrupt, which requires calculating the length of time that the host processes the interrupt.

For this problem, the main processing method at present is to calculate the interrupt handling time by software on the host application side. And there is no general processing method in terms of hardware logic.

However, the result calculated by software is not accurate as the result calculated by hardware logic, and the module sending the interrupt cannot directly know the interrupt duration processed by the host, so that host is required to inform the module of the calculated result by writing a register, and the configuration register also requires time, which again causes new delay.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide an interrupt delay counting system and method based on FPGA, which implement accurate calculation of interrupt processing time.

In order to achieve the purpose, the invention is realized by the following technical scheme: an interrupt delay counting system based on FPGA comprises a host and a plurality of peripherals, wherein the peripherals respectively send interrupt request signals to the host and also comprises an interrupt delay counter which is respectively connected with the host and the peripherals;

the interrupt latency counter includes: the system comprises a configuration module, a control module and a counting module, wherein the configuration module and the control module are respectively connected with the counting module, the configuration module, the control module and the counting module are respectively connected with a host, and the counting module is connected with an external device;

the configuration module is used for receiving configuration information of a host, wherein the configuration information comprises clock frequency and interrupt types of peripheral equipment;

the control module is used for controlling the counting action of the counting module;

and the counting module counts the interrupt requests of each peripheral according to the configuration information of the configuration module and the control information of the control module, and calculates the time for the host to process the interrupt service program according to the count value.

Further, the interrupt types of the peripheral include: level interrupts and edge interrupts.

Furthermore, the counting module comprises a plurality of counting units, and each counting unit is respectively connected with one peripheral and used for receiving the interrupt request signal of the peripheral.

Further, the control module controls the counting action of the counting module to include: the control module controls the counting unit in the counting module to start and stop counting corresponding to the interruption.

Furthermore, the counting module starts counting when receiving the interrupt request signal, and after the host processes the interrupt service program, the counting module receives the configuration information sent by the configuration module and stops counting; the time for the host to process the interrupt service routine is obtained by multiplying the value by the clock frequency.

Correspondingly, the invention also discloses an interrupt delay counting method based on the FPGA, which comprises the following steps:

the host writes configuration information into a configuration module, wherein the configuration information comprises clock frequency and interrupt type of each peripheral;

the host writes control information into the control module, wherein the control information comprises interruption start-stop information and shielding information;

the configuration module sends the configuration information to the counting module, and the control module sends the control information to the counting module; a counting unit in the counting module starts counting after detecting that the interrupt request signal is valid;

after the interrupt request stops, the counting unit stops counting;

the counting unit calculates the time of the host for processing the interrupt service program according to the counting value and writes the time data into the storage unit of the counting module.

Further, the interrupt types of the peripheral include: level interrupts and edge interrupts.

Further, after the interruption request is stopped, the counting unit stops counting, including: and if the interrupt type is level interrupt, stopping the terminal immediately after the terminal request signal is invalid.

Further, after the interruption request is stopped, the counting unit stops counting, including: if the interrupt type is edge interrupt, after the host computer processes the interrupt service program, the completion information is written into the control module, and the control module controls the counting module to stop counting.

Further, the calculating, by the counting unit, the time for the host to process the interrupt service routine according to the count value includes: the counting unit multiplies the clock frequency by the value to obtain the time for the host to process the interrupt service program.

Compared with the prior art, the invention has the beneficial effects that: the invention provides an interrupt delay counting system and method based on FPGA, wherein the interrupt delay counter can accurately calculate the interrupt time of a host from the triggering of peripheral interrupt until the host processes an interrupt service program. The calculated result does not need to inform the corresponding interrupt module through the host, and the interrupt module can directly obtain the corresponding duration from the delay counter.

The interrupt delay counter can be packaged into IP for independent use, so that the portability and the reusability are greatly enhanced. The interrupt delay counter can be used for application development of various accelerator cards, can expand configuration information to meet various counting requirements of a host on interrupts, can also expand the number of terminal requests from 32 to more, and has strong applicability.

Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a system block diagram of the present invention.

FIG. 2 is a flow chart of the method of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made with reference to the accompanying drawings.

As shown in fig. 1, the present invention provides an interrupt delay counting system based on FPGA, which includes a host and 32 peripherals, wherein the peripherals respectively send interrupt request signals to the host, and further includes an interrupt delay counter, and the interrupt delay counter is respectively connected with the host and the peripherals. The interrupt latency counter includes: the system comprises a configuration module, a control module and a counting module, wherein the configuration module and the control module are respectively connected with the counting module, the configuration module, the control module and the counting module are respectively connected with a host, and the counting module is connected with an external device. The counting module comprises 32 counting units, and each counting unit is connected with one peripheral and used for receiving an interrupt request signal of the peripheral.

The configuration module is used for receiving configuration information of the host, wherein the configuration information comprises clock frequency and interrupt type of the peripheral. The interrupt types of the peripheral include: level interrupts and edge interrupts.

The control module is used for controlling the counting action of the counting module; the control module controls whether the count corresponding to each interrupt in the counting module is valid or not and when the count stops.

The counting module starts counting when receiving the interrupt request signal, and stops counting when the host processes the interrupt service program and receives the configuration information sent by the configuration module; the time for the host to process the interrupt service routine is obtained by multiplying the value by the clock frequency.

In the FPGA-based interrupt delay counting system, 32 peripheral devices are provided with interrupt interfaces to a host, and the host receives interrupts from the devices and processes corresponding interrupt service programs. The interrupt delay calculator is used for calculating the time length of the interrupt service program processed by the host.

Correspondingly, as shown in fig. 2, the invention also discloses an interrupt delay counting method based on the FPGA, which comprises the following steps:

the host writes configuration information to the configuration module, the configuration information including the clock frequency and the interrupt type for each peripheral. The interrupt types of the peripheral include: level interrupts and edge interrupts.

And the host writes control information into the control module, wherein the control information comprises interruption start-stop information and shielding information.

The configuration module sends the configuration information to the counting module, and the control module sends the control information to the counting module.

And the counting unit in the counting module starts counting after detecting that the interrupt request signal is valid.

After the interrupt request is stopped, the counting unit stops counting. And if the interrupt type is level interrupt, stopping the terminal immediately after the terminal request signal is invalid. If the interrupt type is edge interrupt, after the host computer processes the interrupt service program, the completion information is written into the control module, and the control module controls the counting module to stop counting.

The counting unit calculates the time of the host for processing the interrupt service program according to the counting value and writes the time data into the storage unit of the counting module. The counting unit multiplies the clock frequency by the value to obtain the time for the host to process the interrupt service program.

The invention introduces an interrupt delay counting method based on an FPGA, and describes an implemented functional framework and a related execution method. The interrupt delay counter can be independently applied to application development of various accelerator cards, can expand configuration information to meet various counting requirements of a host on interrupts, and can also expand the number of interrupt requests from 32 to more, so that the interrupt delay counter has strong applicability.

In the embodiments provided by the present invention, it should be understood that the disclosed system, system and method may be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional modules in the embodiments of the present invention may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one unit.

Similarly, each functional unit in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one unit.

The invention is further described with reference to the accompanying drawings and specific embodiments. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and these equivalents also fall within the scope of the present application.