阅读说明：本技术 具有自散热功能的惠斯通电桥结构及制造方法 (Wheatstone bridge structure with self-heat dissipation function and manufacturing method thereof ) 是由 朱平 李睿康 李涛 于 2019-11-06 设计创作，主要内容包括：本发明涉及一种具有自散热功能的惠斯通电桥结构及制造方法,在具有SOI晶圆上的惠斯通电桥结构的桥臂电阻和金属引线层上层压两层或多层Si<Sub>3</Sub>N<Sub>4</Sub>/FG、AlN/FG膜,形成层压膜图案,层压膜材料的热导率尽量与Si的标准热导率一致；去除惠斯通电桥中心区域的顶部硅层和埋氧层材料,形成一个挖空区域。去除惠斯通电桥下部的硅衬底层材料,形成一个挖空区域。分两步,分别在挖空区域沉积散热层,散热层材料的热导率大于Si的标准热导率。通过自散热,实现惠斯通电桥的物理降温,以解决现有技术中惠斯通电桥输出电压失调的问题。(The invention relates to a Wheatstone bridge structure with self-heat dissipation function and a manufacturing method thereof.A bridge arm resistor and a metal lead layer of the Wheatstone bridge structure on an SOI wafer are laminated with two or more layers of Si 3 N 4 Forming a/FG film and an AlN/FG film to form a laminated film pattern, wherein the thermal conductivity of the laminated film material is consistent with the standard thermal conductivity of Si as much as possible; and removing the top silicon layer and the buried oxide layer material in the central area of the Wheatstone bridge to form a hollow area. The silicon substrate material under the wheatstone bridge is removed to form a hollow region. And respectively depositing heat dissipation layers in the hollowed areas in two steps, wherein the heat dissipation layers are made of materials with the thermal conductivity larger than the standard thermal conductivity of Si. Through self-heat dissipation, realize the physics cooling of Wheatstone bridge to solve among the prior art Wheatstone bridge output voltage maladjustment's problem.)

1. The utility model provides a wheatstone bridge configuration with from heat dissipation function which characterized in that: the chip comprises an SOI wafer (N +/P +, type), a resistor, a metal lead, a laminated film, a first hollow area, a second hollow area, a first heat dissipation layer and a second heat dissipation layer;

the SOI wafer is internally provided with a buried oxide layer, and the upper side and the lower side of the buried oxide layer are respectively provided with a top silicon layer and a silicon substrate layer;

4 or 8 (N +/P + type) resistors are prepared in the top silicon layer of the SOI wafer, and the bottom of each resistor reaches the buried oxide layer; the metal lead is connected with a resistor; laminating the resistor and the metal lead layer to form a laminated film pattern;

removing the top silicon layer and the buried oxide layer material in the central region of the Wheatstone bridge to form a first hollowed-out region; removing the material of the silicon substrate layer at the lower part of the Wheatstone bridge to form a second hollowed-out area; the first heat dissipation layer is deposited in a first hollow area in the center of the Wheatstone bridge and all areas of the SOI top silicon layer to form a coplanar surface; and the second heat dissipation layer is deposited on the surface of the second hollow area of the silicon substrate layer of the SOI wafer.

2. The method of claim 1, wherein: the laminated film material is Si₃N₄/FG or AlN/FG.

3. The method of claim 2, wherein: the thickness of the single-layer laminated film is 50 to 100 nm.

4. A method according to claim 1 or 2 or 3, characterized in that: the first heat dissipation layer is made of one of BeO-SiC, BeN-SiC or BeO-SiC-F.

5. The method of claim 4, wherein: the second heat dissipation layer is made of one of oxidized polyvinylidene fluoride/graphene or AlSiC.

6. A method for preparing a Wheatstone bridge with self-heat dissipation function according to any one of claims 1 to 5, characterized by comprising the steps of:

double-sided oxidation is carried out on an SOI wafer (N +/P + type), and a silicon dioxide thin layer is respectively generated at the top and the bottom of the SOI wafer; patterning the top silicon dioxide thin layer to form an ion implantation area of a bridge arm resistor of the Wheatstone bridge; preparing 4 or 8 (N +/P + -type) resistors in a top silicon layer of the SOI wafer by adopting an ion implantation process, wherein the ion implantation depth reaches a buried oxide layer of the SOI wafer;

preparing a metal lead wire and connecting a resistor by adopting a metal sputtering process; removing the exposed redundant silicon dioxide thin layer on the silicon layer on the top of the SOI wafer by adopting high-energy Ar ion beam bombardment;

laminating two or more layers of laminated films on the resistor and the metal lead layer by a molecular beam epitaxy method to form a laminated film pattern;

removing the top silicon layer and the buried oxide layer material in the central area of the Wheatstone bridge by adopting a plasma etching process to form a first hollowed area; removing the material of the silicon substrate layer at the lower part of the Wheatstone bridge to form a second hollowed-out area;

depositing a first heat dissipation layer which is coplanar on the first hollow area at the center of the Wheatstone bridge and all areas of the SOI silicon dome silicon layer;

and depositing a second heat dissipation layer on the surface of the second hollow area of the SOI silicon substrate layer.

7. The method of claim 6, wherein: for resistors perpendicular to the edges of the film, the laminated film forms a striped pattern along both sides of the resistor strip broadside.

8. The method of claim 6, wherein: for resistors parallel to the edges of the film, the laminated film forms a striped pattern along both sides of the long sides of the resistor strip.

9. The method of claim 6, 7 or 8, wherein: after the laminated film is prepared, low-temperature annealing is performed.

Technical Field

The invention relates to a Wheatstone bridge, in particular to a Wheatstone bridge structure with a self-heat-dissipation function and a preparation method thereof.

Background

The Wheatstone bridge is a detection circuit composed of four resistors, which are called bridge arms of the bridge respectively, the Wheatstone bridge measures the change of physical quantity by using the change of the resistors, acquires the voltage at two ends of the variable resistor and processes the voltage to calculate the corresponding change of the physical quantity, and the method can measure strain, tension, torque, vibration frequency and the like, and is widely applied to medical diagnosis and detection instruments.

The substrate material of the wheatstone bridge is generally a Si wafer, an SOI wafer, a SiC wafer, a ceramic, or the like. Among them, the SOI is named Silicon On Insulator and is the most common substrate material for new generation integrated circuits, and the commercialized SOI process technology is already very mature. The SOI structure means that elements such as a silicon transistor, a resistor and a capacitor are structurally arranged on an insulator, and the principle is that an insulating medium SiO is added between the elements₂So that the capacitor has excellent electrical insulation capability and the parasitic capacitance between the two is twice less than that of the original capacitor. However, due to the isolation of the insulating medium in the SOI wafer, depletion layers of front and back interfaces of elements manufactured on the SOI structure do not affect each other, a neutral body region exists between the depletion layers, the existence of the neutral body region enables the silicon body to be in an electrically floating state, and two obvious parasitic effects are generated, namely a 'warping effect' of output characteristics, namely a Kink effect, and a parasitic transistor effect. Due to the insulating medium SiO₂Has a standard thermal conductivity of 1.4W/mK and a standard thermal conductivity of 130W/mK for Si. If in a high-temperature environment for a long time, the insulating medium SiO₂The low heat dissipation efficiency can cause self-heating effect, and aggravate the failure problems of warping effect or parasitic transistor effect of the output characteristics of the elements on the SOI structure.

Therefore, when the temperature of the working environment rises to about 200 ℃, the Wheatstone bridge using SOI as the substrate material still has the phenomenon of bridge output voltage offset caused by zero offset of output voltage, sensitivity change, temperature coefficient drift of a bridge arm and the like. The reason for this is that the output characteristics of the four resistors in the Wheatstone bridge are warped and the thermal expansion coefficient is not matched with each other to cause SiO₂Residual stress in the/Si laminated film structure, etc. causes the bridge output voltage to be offset. Therefore, temperature compensation is still required for SOI devices or circuit structures that are sensitive to temperature. At present, the output voltage offset compensation of the Wheatstone bridge is mainly to make the output voltage around the Wheatstone bridge insensitive to physical quantityThe compensation structure of the inductor, the series-parallel resistor, the diode or the triode and the like perform temperature compensation, and the output voltage is subjected to software compensation and the like. These temperature compensation techniques are passive in nature and if the external operating environment varies beyond a predetermined value, the effect of these temperature compensation measures is reduced.

Disclosure of Invention

The invention aims to solve the technical problem of providing a Wheatstone bridge structure with a self-heat-dissipation function and a preparation method thereof, so that the physical temperature reduction of the Wheatstone bridge is realized.

To solve the above technical problem, according to an aspect of the present invention, there is provided a wheatstone bridge structure with self-heat dissipation function, comprising an SOI wafer (N +/P + -type), a resistor, a metal lead, a laminated film, a first hollowed-out region, a second hollowed-out region, a first heat dissipation layer, and a second heat dissipation layer;

the SOI wafer is internally provided with a buried oxide layer, and the upper side and the lower side of the buried oxide layer are respectively provided with a top silicon layer and a silicon substrate layer;

4 or 8 (N +/P + type) resistors are prepared in the top silicon layer of the SOI wafer, and the bottom of each resistor reaches the buried oxide layer; the resistor is connected with the metal lead; laminating the resistor and the metal lead layer to form a laminated film pattern;

removing the top silicon layer and the buried oxide layer material in the central region of the Wheatstone bridge to form a first hollowed-out region; removing the material of the silicon substrate layer at the lower part of the Wheatstone bridge to form a second hollowed-out area; the first heat dissipation layer is deposited in a first hollow area in the center of the Wheatstone bridge and all areas of the SOI top silicon layer to form a coplanar surface; and the second heat dissipation layer is deposited on the surface of the second hollow area of the silicon substrate layer of the SOI wafer.

Preferably, the laminated film material is Si₃N₄/FG or AlN/FG.

Preferably, the thickness of the single-layer laminated film is 50 to 100 nm.

Preferably, the first heat dissipation layer is made of one of BeO-SiC, BeN-SiC or BeO-SiC-F.

Preferably, the material of the second heat dissipation layer is one of oxidized polyvinylidene fluoride/graphene or AlSiC.

According to another aspect of the present invention, there is provided a method for preparing a wheatstone bridge with a self-heat dissipation function, including the steps of:

double-sided oxidation is carried out on an SOI wafer (N +/P + type), and a silicon dioxide thin layer is respectively generated at the top and the bottom of the SOI wafer; patterning the top silicon dioxide thin layer to form an ion implantation area of a bridge arm resistor of the Wheatstone bridge; preparing 4 or 8 (N +/P + -type) resistors in a top silicon layer of the SOI wafer by adopting an ion implantation process, wherein the ion implantation depth reaches a buried oxide layer of the SOI wafer;

forming a metal lead wire on the periphery of the resistor by adopting a metal sputtering process; removing the exposed redundant silicon dioxide thin layer on the silicon layer on the top of the SOI wafer by adopting high-energy Ar ion beam bombardment;

laminating two or more layers of laminated films on the resistor and the metal lead layer by a molecular beam epitaxy method to form a laminated film pattern;

removing the top silicon layer and the buried oxide layer material in the central area of the Wheatstone bridge by adopting a plasma etching process to form a first hollowed area; removing the material of the silicon substrate layer at the lower part of the Wheatstone bridge to form a second hollowed-out area;

depositing a first heat dissipation layer which is coplanar on the first hollow area at the center of the Wheatstone bridge and all areas of the SOI silicon dome silicon layer;

and depositing a second heat dissipation layer on the surface of the second hollow area of the SOI silicon substrate layer.

Preferably, for resistors perpendicular to the edges of the film, the laminated film forms a striped pattern along both sides of the resistor strip broadside.

Preferably, for resistors parallel to the edges of the film, the laminated film forms a striped pattern along both sides of the long sides of the resistor track.

Preferably, after the laminate film is produced, low temperature annealing is performed.

The invention is compatible with a mature SOI process, avoids the development of a new process, and has the advantages of simple process flow, low production cost and the like.

According to the invention, the metal lead is formed by adopting a metal sputtering process, so that a high-efficiency heat conduction channel is formed, the equivalent resistance of the lead and the heat generated by the bridge arm resistance can be reduced, and the physical cooling is promoted; the first heat dissipation layer is formed in the hollowed area of the central area of the Wheatstone bridge and all areas of the silicon layer at the top of the SOI silicon dome part through deposition, the second heat dissipation layer is formed on the surface of the hollowed area of the silicon substrate layer of the SOI wafer, self-heat dissipation is carried out through the heat dissipation layers, physical cooling of the Wheatstone bridge is achieved, and the defect that the output voltage of the Wheatstone bridge is out of order in the prior art is overcome.

Drawings

Fig. 1 is a flow chart of manufacturing a wheatstone bridge with a self-heat dissipation function according to the present invention.

FIG. 2 shows a laminated film formed in a striped pattern along both sides of the resistor strip width.

Fig. 3 is a diagram in which the laminated film is formed in a striped pattern along both sides of the long sides of the resistor strip.

In the figure, 1-buried oxide layer, 2-top silicon layer, 3-silicon substrate layer, 4-resistor, 5-metal lead, 6-laminated film, 7-first hollowed-out region, 8-second hollowed-out region, 9-first heat dissipation layer, 10-second heat dissipation layer, and 11-silicon dioxide thin layer.

Detailed Description

An exemplary embodiment of the present invention provides a wheatstone bridge structure with self-heat dissipation function, as shown in fig. 1 (10), comprising an SOI wafer (N +/P + -type), a resistor 4, a metal lead 5, a laminated film 6, a first hollowed-out region 7, a second hollowed-out region 8, a first heat dissipation layer 9, and a second heat dissipation layer 10.

The SOI wafer is internally provided with a buried oxide layer 1, and the upper side and the lower side of the buried oxide layer 1 are a top silicon layer 2 and a silicon substrate layer 3 respectively.

The SOI wafer has 4 or 8 (N +/P + -type) resistors 4 fabricated in the top silicon layer 3, the resistors 4 reaching at the bottom the buried oxide layer 1. The metal lead 5 is connected with the resistor 4 to form a high-efficiency heat conduction channel, so that the equivalent resistance of the lead can be reduced, heat generated by the bridge arm resistor can be dissipated, and physical cooling is promoted; the metal contacts can be attached to LTCC substrates, integrated circuits, and any metal connectors. The metal leads 5 are more than twice as wide as standard processes.

The resistor 4 and the metal lead 5 are laminated to form a laminated film 6 pattern. The laminated film material is Si₃N₄/FG or AlN/FG. The thermal conductivity of the laminated film is consistent with the standard thermal conductivity of Si as much as possible, and the laminated film is electrically insulated within the range of 100-150W/m.K; two laminated films with a single laminated film thickness of 50-100nm and resistances perpendicular/parallel to the edges were prepared coplanar. The Wheatstone bridge arm resistance is limited to induce the change of physical quantities such as strain, tension, torque, vibration frequency and the like from the top silicon layer of the SOI wafer, the laminated film can enhance the capacity of the arm resistance to induce the change of the physical quantities, and the laminated film can enable the arm resistance to present less parasitic capacitance and reduce the change of resistivity under a high-temperature environment.

Removing the materials of the top silicon layer 2 and the buried oxide layer 1 in the central region of the Wheatstone bridge to form a first hollow region 7; removing the material of the silicon substrate layer 3 at the lower part of the Wheatstone bridge to form a second hollow area 8; and respectively generating a silicon dioxide thin layer on the top and the bottom of the SOI wafer, removing the top silicon dioxide thin layer in the preparation process, and only remaining the silicon dioxide thin layer on the lower part of the silicon substrate layer after forming the second hollowed area.

A first heat dissipation layer 9 is deposited on the first hollowed-out region 7 at the center of the Wheatstone bridge and all regions of the SOI top silicon layer to form a coplanar surface; a second heat dissipation layer 10 is deposited on the surface of the second hollowed-out area of the silicon substrate layer 3 of the SOI wafer.

The heat dissipation layer material is selected to have more excellent heat conductivity and mechanical property, and has the advantages of high melting point, high hardness, high wear resistance, oxidation resistance and the like, wherein ① has good insulation and electric breakdown resistance, ② has high heat conductivity, the heat conductivity directly influences the operation condition and the service life of a semiconductor device, the noise of an electronic device is greatly increased due to uneven temperature field distribution caused by poor heat dissipation, ③ has a thermal expansion coefficient matched with other materials used in a package, ④ has good high-frequency characteristics, namely low dielectric constant and low dielectric loss, ⑤ has a smooth surface and consistent thickness, the first heat dissipation layer material is selected from one of BeO-SiC, BeN-SiC or BeO-SiC-F, and the second heat dissipation layer material is selected from one of oxidized polyvinylidene fluoride/graphene or AlSiC.

Another exemplary embodiment of the present invention provides a method for preparing a wheatstone bridge with a self-heat dissipation function, as shown in fig. 1, including the steps of:

double-sided oxidation is carried out on an SOI wafer (N +/P + type), and a silicon dioxide thin layer is respectively generated at the top and the bottom of the SOI wafer; patterning the top silicon dioxide thin layer to form an ion implantation area of a bridge arm resistor of the Wheatstone bridge; preparing 4 or 8 (N +/P + -type) resistors in a top silicon layer of the SOI wafer by adopting an ion implantation process, wherein the ion implantation depth reaches a buried oxide layer of the SOI wafer;

preparing a metal lead wire and connecting a resistor by adopting a metal sputtering process; and (3) removing the exposed redundant silicon dioxide thin layer on the silicon layer on the top of the SOI wafer by adopting high-energy Ar ion beam bombardment, so that a heat dissipation channel is formed.

Two or more laminated films are laminated on the resistor and the metal lead layer by a molecular beam epitaxy method to form a laminated film pattern.

Referring to fig. 2, for resistors perpendicular to the edges of the film, the laminated film forms a striped pattern along both sides of the resistor strip broadside.

Referring to fig. 3, for resistors parallel to the edges of the film, the laminated film forms a striped pattern along both sides of the long sides of the resistor strip.

After the laminated film is prepared, low-temperature annealing is carried out to prevent the wafer from warping.

Removing the top silicon layer and the buried oxide layer material in the central area of the Wheatstone bridge by adopting a plasma etching process to form a first hollowed area; and removing the material of the silicon substrate layer at the lower part of the Wheatstone bridge to form a second hollowed-out region.

Depositing heat dissipation layers in the hollowed-out areas respectively in two steps, and in the first step, forming a coplanar surface in the hollowed-out area in the center of the Wheatstone bridge and all areas of the silicon layer at the silicon dome part of the SOI silicon by adopting a physical vapor deposition process or other processes to form a first heat dissipation layer; the thickness of the heat dissipation layer of the first deposition in all regions of the SOI top silicon layer is 500-600nm, the material can be BeO-SiC, BeN-SiC or BeO-SiC-F, the thermal conductivity is 140-350W/m.K, and the heat dissipation layer is electrically insulated. Secondly, depositing a second heat dissipation layer in the hollowed area of the SOI substrate layer, wherein the thickness of the second heat dissipation layer is 300-500 nm; the material of the heat dissipation layer deposited for the second time can be oxidized polyvinylidene fluoride/graphene or AlSiC, the heat conductivity is more than 100W/m.K, and the heat dissipation layer is electrically insulated.

In the above steps, the formation of the laminated film pattern and the formation of the first and second hollow regions are not in order.