阅读说明：本技术 用于改善器件特性的半导体器件 (Semiconductor device for improving device characteristics ) 是由 全辰桓 金熙中 金根楠 韩成熙 黄有商 于 2019-04-17 设计创作，主要内容包括：一种半导体器件包括：衬底,具有由器件隔离区限定的有源区；导电线,在有源区上沿一方向延伸；绝缘衬垫,在导电线的下部的两个侧壁上,导电线的下部与有源区接触；间隔物,在与衬底的表面垂直的方向上与绝缘衬垫隔开,并且顺序地形成在导电线的上部的两个侧壁上；阻挡层,布置在绝缘衬垫与位于所述多个间隔物中间的间隔物之间的间隔处,并且在从位于所述多个间隔物中间的间隔物的一端朝导电线凹入的凹陷部分中；以及导电图案,布置在所述多个间隔物两侧的有源区上。(A semiconductor device includes: a substrate having an active region defined by a device isolation region; a conductive line extending in a direction on the active region; insulating pads on both sidewalls of a lower portion of the conductive line, the lower portion of the conductive line being in contact with the active region; spacers spaced apart from the insulating liner in a direction perpendicular to a surface of the substrate and sequentially formed on both sidewalls of an upper portion of the conductive line; a barrier layer disposed at a space between the insulating liner and a spacer located among the plurality of spacers and in a recess portion recessed from one end of the spacer located among the plurality of spacers toward the conductive line; and a conductive pattern disposed on the active region on both sides of the plurality of spacers.)

1. A semiconductor device, comprising:

a substrate having a plurality of active regions defined by device isolation regions;

a conductive line extending in a direction on the active region of the substrate;

a plurality of insulating pads on both sidewalls of a lower portion of the conductive line, the lower portion of the conductive line being in contact with the active region;

a plurality of spacers spaced apart from the insulating liner in a direction perpendicular to a surface of the substrate and sequentially located on both sidewalls of an upper portion of the conductive line;

a barrier layer between the insulating liner and a spacer among the plurality of spacers and in a recessed portion recessed from an end of the spacer among the plurality of spacers toward the conductive line; and

a conductive pattern on the active region on both sides of the plurality of spacers.

2. The semiconductor device of claim 1, wherein an outermost spacer among the plurality of spacers extends in a vertical direction of the substrate between the insulating pad and the conductive pattern.

3. The semiconductor device of claim 1, wherein the conductive line comprises a protruding conductive line protruding from the surface of the substrate and a buried conductive line below the surface of the substrate.

4. The semiconductor device of claim 3, wherein the plurality of insulating liners comprises an upper insulating liner and a lower insulating liner, the upper insulating liner being higher on both sides of the protruding conductive line than the surface of the substrate, the lower insulating liner being lower on both sides of the buried conductive line than the surface of the substrate, and

a sidewall of the upper insulating liner on the conductive pattern side is perpendicular to the surface of the substrate.

5. The semiconductor device of claim 1, wherein the plurality of insulating spacers comprises a first insulating spacer, a second insulating spacer, and a third insulating spacer arranged sequentially from one sidewall of the conductive line.

6. The semiconductor device of claim 1, wherein the barrier layer in the recessed portion has a rectangular or circular cross-sectional shape toward the conductive line.

7. The semiconductor device of claim 1, wherein the plurality of spacers comprises an inner spacer on one sidewall of the conductive line and a plurality of outer spacers sequentially arranged on one sidewall of the inner spacer.

8. The semiconductor device of claim 7, wherein the plurality of outer spacers comprises a first outer spacer and a second outer spacer sequentially arranged on one sidewall of the inner spacer, the barrier layer underlying the first outer spacer.

9. The semiconductor device of claim 7, wherein the plurality of outer spacers comprises a first outer spacer, an additional outer spacer, and a second outer spacer sequentially arranged on one sidewall of the inner spacer, the blocking layer underlying the first outer spacer and the additional outer spacer.

10. The semiconductor device of claim 1, wherein the plurality of spacers comprises an inner spacer on one sidewall of the conductive line and an air spacer and an outer spacer sequentially arranged on one sidewall of the inner spacer, the blocking layer being under the air spacer.

11. A semiconductor device, comprising:

a substrate having a plurality of active regions defined by device isolation regions;

an interlayer insulating layer on the device isolation region;

a conductive line extending in a direction on the interlayer insulating layer of the substrate;

a plurality of spacers spaced apart from the interlayer insulating layer in a direction perpendicular to a surface of the substrate and on both sidewalls of the conductive line;

a barrier layer at a space between the interlayer insulating layer and a spacer among the plurality of spacers and in a recess portion recessed from one end of the spacer among the plurality of spacers toward the conductive line; and

a conductive pattern on the active region on both sides of the plurality of spacers.

12. The semiconductor device of claim 11, wherein the interlayer insulating layer comprises a plurality of insulating layers on the device isolation region.

13. The semiconductor device according to claim 11, wherein the interlayer insulating layer further comprises an additional recessed portion recessed inward, wherein the additional recessed portion comprises an additional barrier layer.

14. The semiconductor device of claim 13, wherein the barrier layer and the additional barrier layer comprise a same material as a material of an outermost outer spacer among the plurality of spacers.

15. The semiconductor device of claim 11, wherein an inner spacer, among the plurality of spacers, on both sidewalls of the conductive line is on the interlayer insulating layer.

16. A semiconductor device, comprising:

a substrate having a plurality of active regions defined by device isolation regions;

an interlayer insulating layer on the device isolation region;

a conductive line extending in a direction on the interlayer insulating layer and the active region of the substrate;

a plurality of insulating pads on both sidewalls of a lower portion of the conductive line, the lower portion of the conductive line being in contact with the active region;

a plurality of spacers spaced apart from the insulating pad and the interlayer insulating layer in a direction perpendicular to a surface of the substrate and sequentially formed on both sidewalls of an upper portion of the conductive line;

a barrier layer between the insulating liner and the spacer between the interlayer insulating layer and the plurality of spacers, and in a recessed portion recessed from one end of the spacer located in the middle of the plurality of spacers toward the conductive line; and

a conductive pattern on the active region on both sides of the plurality of spacers.

17. The semiconductor device of claim 16, wherein the conductive line comprises a protruding conductive line protruding from the surface of the substrate, wherein upper insulating liners above the surface of the substrate are on both sides of the protruding conductive line, sidewalls of the upper insulating liners on the conductive pattern side being perpendicular to the surface of the substrate.

18. The semiconductor device of claim 16, wherein the plurality of spacers comprises an inner spacer on one sidewall of the conductive line and a plurality of outer spacers sequentially arranged on one sidewall of the inner spacer, the blocking layer underlying one of the outer spacers.

19. The semiconductor device of claim 16, wherein the barrier layer comprises a same material as a material of an outermost outer spacer among the plurality of spacers.

20. The semiconductor device according to claim 16, wherein the interlayer insulating layer includes an additional recessed portion recessed inward, wherein the additional recessed portion includes an additional barrier layer.

Technical Field

The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device for improving device characteristics.

Background

Highly integrated semiconductor devices have poor device characteristics due to difficulties in manufacturing processes. For example, a highly integrated semiconductor device may have a reduced distance between a conductive line (e.g., a wire) and a contact pattern located between the conductive lines, so that the conductive line and the contact pattern may be shorted with each other. In addition, when the capacitance between the conductive line and the contact pattern, the distance of which is reduced, is increased, the operation speed of the semiconductor device may be slower or the device characteristics thereof such as refresh characteristics may be deteriorated.

Disclosure of Invention

The inventive concept provides a semiconductor device capable of improving device characteristics without short circuits even when a distance between a conductive line and a contact pattern is reduced.

According to an aspect of the inventive concept, there is provided a semiconductor device including: a substrate having a plurality of active regions defined by device isolation regions; a conductive line extending in a direction on an active region of a substrate; a plurality of insulating pads on both sidewalls of a lower portion of the conductive line, the lower portion of the conductive line being in contact with the active region; a plurality of spacers spaced apart from the insulating liner in a direction perpendicular to a surface of the substrate and sequentially located on both sidewalls of an upper portion of the conductive line; a barrier layer between the insulating liner and a spacer among the plurality of spacers and in a recessed portion recessed from an end of the spacer among the plurality of spacers toward the conductive line; and a conductive pattern on the active region on both sides of the plurality of spacers.

According to another aspect of the inventive concept, there is provided a semiconductor device including: a substrate having a plurality of active regions defined by device isolation regions; an interlayer insulating layer on the device isolation region; a conductive line extending in one direction on the interlayer insulating layer of the substrate; a plurality of spacers spaced apart from the interlayer insulating layer in a direction perpendicular to a surface of the substrate and on both sidewalls of the conductive line; a barrier layer at an interval between the interlayer insulating layer and a spacer among the plurality of spacers and in a recess portion recessed from one end of the spacer among the plurality of spacers toward the conductive line; and a conductive pattern on the active region on both sides of the plurality of spacers.

According to another aspect of the inventive concept, there is provided a semiconductor device including: a substrate having a plurality of active regions defined by device isolation regions; an interlayer insulating layer on the device isolation region; a conductive line extending in a direction on the interlayer insulating layer and the active region of the substrate; a plurality of insulating pads on both sidewalls of a lower portion of the conductive line, the lower portion of the conductive line being in contact with the active region; a plurality of spacers spaced apart from the insulating pad and the interlayer insulating layer in a direction perpendicular to a surface of the substrate and sequentially formed on both sidewalls of an upper portion of the conductive line; a barrier layer between the insulating liner and the inter-layer insulating layer and spacers among the plurality of spacers, and in a recessed portion recessed from one end of the spacer among the plurality of spacers toward the conductive line; and a conductive pattern on the active region on both sides of the plurality of spacers.

Drawings

At least one embodiment of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a layout view of a semiconductor device according to at least one embodiment of the inventive concept;

fig. 2 is a cross-sectional view of a main portion of a semiconductor device according to at least one embodiment of the inventive concept;

fig. 3 is a cross-sectional view of a main portion of a semiconductor device according to at least one embodiment of the inventive concept;

fig. 4A to 14 are sectional views of main portions of a semiconductor device for explaining a method of manufacturing the semiconductor device according to at least one embodiment of the inventive concept;

fig. 15 to 22 are sectional views of main portions of a semiconductor device for explaining a method of manufacturing the semiconductor device according to at least one embodiment of the inventive concept; and

fig. 23 is a view of a system including a semiconductor device according to at least one embodiment of the inventive concept.

Detailed Description

Fig. 1 is a layout view of a semiconductor device according to at least one embodiment of the inventive concept.

In more detail, the semiconductor device 100 according to at least one embodiment may include a plurality of active regions ACT. The active region ACT may be defined by a device isolation region 114 (of fig. 2, etc.) formed in the substrate 110 (of fig. 2, etc.). As the design rule of the semiconductor device 100 decreases, the active region ACT may be arranged in a stripe form of diagonal or oblique lines as shown.

A plurality of word lines WL (or gate lines) extending parallel to each other in the second direction (X direction) across the active area ACT may be arranged on the active area ACT. The word line WL may be a conductive line. The word lines WL may be arranged at regular intervals. The width of the word lines WL or the interval between the word lines WL may be determined according to a design rule. A plurality of bit lines BL extending parallel to each other in a first direction (Y direction) orthogonal to the word lines WL are formed on the word lines WL. The bit line BL may be a conductive line. The bit lines BL may also be arranged at regular intervals. The width of the bit lines BL or the interval between the bit lines BL may be determined according to a design rule.

In at least one embodiment, the bit lines BL may be arranged in parallel with each other at a pitch of 3F. The word lines WL may be arranged in parallel with each other at a pitch of 2F, respectively. In this case, F may refer to the minimum lithographic feature size. When the bit lines BL and the word lines WL are arranged at the pitch as described above, the semiconductor device 100 may include a semiconductor device having 6F²A unit cell size of (1).

The semiconductor device 100 according to at least one embodiment may include various contact arrangements, such as a direct contact DC, a buried contact BC, a landing pad LP, and the like, formed on the active region ACT. In at least one embodiment, the direct contact DC may refer to a contact connecting the active region ACT to the bit line BL, and the buried contact BC may refer to a contact connecting the active region ACT to a lower electrode (not shown) of the capacitor.

The contact area between the buried contact BC and the active region ACT may be very small in arrangement. Therefore, the conductive landing pad LP may be introduced to enlarge a contact area with respect to a lower electrode (not shown) of the capacitor and the active region ACT. The landing pad LP may be disposed between the active region ACT and the buried contact BC, or may be disposed between the buried contact BC and the lower electrode of the capacitor. In at least one embodiment, the landing pad LP may be disposed between the buried contact BC and the lower electrode of the capacitor. By increasing the contact area through the introduction of the landing pad LP, the contact resistance between the active region ACT and the lower electrode of the capacitor can be reduced.

In the semiconductor device 100 of at least one embodiment, the direct contact DC may be disposed at a central portion of the active region ACT, and the buried contacts BC may be disposed at both end portions of the active region ACT. Since the buried contacts BC are arranged at both ends of the active region ACT, the landing pads LP may be arranged to partially overlap the buried contacts BC adjacent to both ends of the active region ACT.

The word lines WL may be formed as structures in the substrate 110 of the semiconductor device 100 and may be arranged to cross the active region ACT between the direct contact DC and the buried contact BC. As shown, two word lines WL are arranged to cross one active region ACT, and the active region ACT is arranged in a slanted shape to form an angle of less than 90 ° with the word lines WL.

The direct contact DC and the buried contact BC may be symmetrically arranged and thus may be arranged on a straight line along the X axis and the Y axis. Unlike the direct contact DC and the buried contact BC, the landing pads LP may be arranged in a zigzag shape L1 in the first direction (Y direction) in which the bit lines BL extend. Further, the landing pads LP may be arranged to overlap the same side surface of each bit line BL in the second direction (X direction) in which the word lines WL extend. For example, each of the landing pads LP of the first line may overlap a left side surface of the corresponding bit line BL, and each of the landing pads LP of the second line may overlap a right side surface of the corresponding bit line BL.

Fig. 2 is a cross-sectional view of a main portion of a semiconductor device according to at least one embodiment of the inventive concept.

In more detail, the semiconductor device 100a of fig. 2 may be a partial cross-sectional view taken along line I-I' of fig. 1. The semiconductor device 100a may include a substrate 110, the substrate 110 having a plurality of active regions 116 defined by device isolation regions 114. The device isolation region 114 may include a device isolation layer in a device isolation trench 112, the device isolation trench 112 being formed in the substrate 110.

The device isolation region 114 may further include a bit line BL140 extending along the first direction (Y direction) of the substrate 110. The bit line BL140 may include a plurality of layers as shown. For example, the bit line BL140 may be formed by sequentially stacking impurity-doped polysilicon 142, tungsten nitride 144, tungsten 146, and a cap insulating layer 148. The cap insulating layer 148 may include a silicon nitride layer. It is to be narrowly understood that the bit line BL140 may include only impurity-doped polysilicon 142, tungsten nitride 144, and tungsten 146.

In at least one embodiment, unlike the drawing, the bit line BL may be formed as a single layer. For example, the bit line BL140 may include at least one of an impurity-doped semiconductor, a metal nitride, and a metal silicide.

The bit line BL140 may include a first conductive line CL1 and a second conductive line CL 2. The first conductive line CL1 may be formed on the active region 116 of the substrate 110. The second conductive line CL2 may be formed on an interlayer insulating layer 130, the interlayer insulating layer 130 being on the device isolation region 114 formed in the substrate 110.

The interlayer insulating layer 130 may include a plurality of insulating layers, for example, first to third insulating layers 130a, 130b and 130c formed on the device isolation region 114. The first, second, and third insulating layers 130a, 130b, and 130c may include a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, respectively.

The first conductive line CL1 may include a direct contact 135 that contacts the active region 116. The direct contact 135 may comprise impurity doped polysilicon as described above. A plurality of insulating spacers 152 are formed on lower portions of the first conductive lines CL1 in contact with the active regions 116, for example, on both sidewalls of the direct contacts 135.

The insulating liner 152 may be formed to protect a lower portion of the first conductive line CL 1. The insulating liner 152 may be formed to insulate the lower portion of the first conductive line CL1 from the conductive pattern 168a, i.e., the buried contact BC. The insulating liner 152 may include a first insulating liner 152a, a second insulating liner 152b, and a third insulating liner 152c sequentially formed from the first conductive line CL1, i.e., one sidewall of the direct contact 135. The first, second, and third insulating pads 152a, 152b, and 152c may include a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer, respectively.

The first conductive line CL1, i.e., the direct contact 135, may include a protruding conductive line PCL protruding from the surface 110T of the substrate 110 and a buried conductive line BCL formed below the surface 110T of the substrate 110. Upper insulating pads 152U higher than the surface 110T of the substrate 110 are formed on both sides of the protruding conductive line PCL. Lower insulating spacers 152L lower than the surface 110T of the substrate 110 are formed at both sides of the buried conductive line BCL.

The sidewall SL1 of the upper insulating pad 152U on the conductive pattern 168a side may be perpendicular to the surface 110T of the substrate 110. When the sidewall SL1 of the upper insulating liner 152U is vertical, the lower opening length CR1 of the conductive pattern 168a, i.e., the buried contact BC, may be enlarged when the semiconductor device 100a is manufactured, and thus device characteristics such as contact resistance may be reduced.

A plurality of spacers 163 are formed on both sidewalls of upper portions of the first and second conductive lines CL1 and CL 2. The spacer 163 may be referred to as a plurality of spacers. Each of the spacers 163 may include an inner spacer 152d formed on one sidewall of the first and second conductive lines CL1 and CL2, and a first and second outer spacers 154a and 164 sequentially formed on one sidewall of the inner spacer 152 d.

The inner spacers 152d may include a silicon nitride layer. The first outer spacer 154a may include a silicon oxide layer. The second outer spacers 164 may include a silicon nitride layer. When the first outer spacer 154a is removed by etching, the first outer spacer 154a may be an air spacer. At least one embodiment describes two outer spacers, namely a first outer spacer 154a and a second outer spacer 164, but a greater number of outer spacers may be included.

A conductive pattern 168a, i.e., a buried contact BC, is formed on the active region 116 on both sides of the spacer 163. The spacers 163 formed on both sidewalls of the first conductive line CL1 are spaced apart from the insulating liner 152 in a direction (Z direction) perpendicular to the surface 110T of the substrate 110.

Accordingly, the first blocking layer 162a is disposed at a space between the insulating liner 152 and the first outer spacer 154a located in the middle of the spacer 163, and is disposed in the first recess portion 158a recessed from one end of the first outer spacer 154a toward the first conductive line CL 1.

The first blocking layer 162a extends from the first outer spacer 154a toward the first conductive line CL 1. The first barrier layer 162a in the first recess portion 158a may have a rectangular sectional shape toward the first conductive line CL 1. In at least one embodiment, the first barrier layer 162a in the first recess portion 158a may have a circular sectional shape toward the first conductive line CL 1. The present application is not limited by the sectional shape of the first barrier layer 162a in the first recess portion 158 a. A first barrier layer 162a is formed under the first outer spacer 154 a. The first barrier layer 162a may include a silicon nitride layer.

When the first outer spacer 154a is formed as an air spacer by being removed, the first barrier layer 162a may protect the insulating liner 152. In addition, when the first outer spacer 154a is formed as an air spacer, the first barrier layer 162a may suppress an influence of an etching gas, such as Cl gas, penetrating the air spacer on the active region 116 through the insulating liner 152. Therefore, device characteristics such as refresh characteristics can be improved.

The spacers 163 formed on both sidewalls of the second conductive line CL2 are spaced apart from the interlayer insulating layer 130 in a direction perpendicular to the surface 110T of the substrate 110. The second barrier layer 162b is disposed at a space between the interlayer insulating layer 130 and the first outer spacer 154a located in the middle of the spacers, and is disposed in the second recess portion 158b recessed from one end of the first outer spacer 154a toward the second conductive line CL 2.

The second blocking layer 162b extends from the first outer spacer 154a toward the second conductive line CL 2. The inner spacers 152d formed on both sidewalls of the second conductive line CL2 among the spacers 163 are also formed on the surface 130T of the interlayer insulating layer 130. The second barrier layer 162b in the second recess portion 158b may have a rectangular sectional shape toward the second conductive line CL 2.

In at least one embodiment, the second barrier layer 162b in the second recess portion 158b may have a circular sectional shape toward the second conductive line CL 2. The present application is not limited by the sectional shape of the second barrier layer 162b in the second recess portion 158 b. The second barrier layer 162b is formed on the surface 130T of the interlayer insulating layer 130. The second barrier layer 162b includes the same material as that of the first barrier layer 162 a.

When the first outer spacer 154a is formed as an air spacer by being removed, the second blocking layer 162b may protect the interlayer insulating layer 130. In addition, when the first outer spacer 154a is formed as an air spacer, the second blocking layer 162b may suppress an influence of an etching gas, such as Cl gas, penetrating the air spacer on the active region 116 through the interlayer insulating layer 130. Therefore, device characteristics such as refresh characteristics can be improved.

An outermost spacer among the plurality of spacers 163, i.e., the second outer spacer 164, extends in a vertical direction of the substrate 110 between the insulating pad 152 and the conductive pattern 168 a. The second external spacers 164 formed on both sidewalls of the first and second conductive lines CL1 and CL2 may include the same material as that of the first and second blocking layers 162a and 162 b.

Fig. 3 is a cross-sectional view of a main portion of a semiconductor device according to at least one embodiment of the inventive concept.

In at least one embodiment, the semiconductor device 100b of fig. 3 may be a partial cross-sectional view taken along line I-I' of fig. 1. In comparison with the semiconductor device 100a of fig. 2, the semiconductor device 100b is formed with an additional recess portion 158c formed inward under the interlayer insulating layer 130, and an additional barrier layer 162c is formed in the additional recess portion 158 c. In fig. 3, the same reference numerals as in fig. 2 denote the same elements, and further description thereof will be omitted or simplified for convenience.

The semiconductor device 100b includes an interlayer insulating layer 130, and the interlayer insulating layer 130 is formed on the device isolation region 114 on the substrate 110. An additional recess portion 158c is formed inwardly under the interlayer insulating layer 130. That is, the width of the first insulating layer 130a is smaller than the widths of the second and third insulating layers 130b and 130 c. An additional barrier layer 162c is formed in the additional recess portion 158 c. The second barrier layer 162b and the additional barrier layer 162c include the same material as that of the outermost outer spacer among the spacers 163.

The semiconductor device 100b further includes an additional barrier layer 162c, and may further suppress the influence of an etching gas such as Cl gas penetrating the air spacer on the active region 116 through the interlayer insulating layer 130. Therefore, device characteristics such as refresh characteristics can be further improved.

Fig. 4A to 14 are sectional views of main portions of a semiconductor device for explaining a method of manufacturing a semiconductor device according to at least one embodiment of the inventive concept.

In more detail, fig. 4A, fig. 5 to 8, fig. 9A and 9B, fig. 10A and 10B, and fig. 11 to 14 may be a sectional view of a main portion of the semiconductor device taken along a line I-I 'of fig. 1, and fig. 4B may be a sectional view of a main portion of the semiconductor device taken along a line II-II' of fig. 1. In fig. 4A to 14, the same reference numerals as in fig. 2 and 3 denote the same elements, and thus a detailed description thereof will not be given here.

Referring to fig. 4A and 4B, a device isolation trench 112 is formed in the substrate 110, and then a device isolation region 114 is formed by filling an insulating layer in the device isolation trench 112. An active region 116 may be defined in the substrate 110 by the device isolation region 114. As shown in fig. 1, the active region 116 may have a relatively long island shape having a short axis and a long axis, and may be arranged in a slanted shape to form an angle of less than 90 ° with the word line 124 formed over the active region 116.

The substrate 110 may include silicon (Si), such as crystalline Si, poly-Si, or amorphous Si. In at least one embodiment, the substrate 110 may include germanium (Ge) or a compound semiconductor such as SiGe, silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In at least one embodiment, the substrate 110 may include a conductive region, such as an impurity-doped well or an impurity-doped structure.

The device isolation region 114 may be formed as a single insulating layer, but may include an outer insulating layer 114A and an inner insulating layer 114B as shown in fig. 4B. The outer insulating layer 114A and the inner insulating layer 114B may include different materials. For example, the outer insulating layer 114A may include an oxide layer, and the inner insulating layer 114B may include a nitride film. However, the configuration of the device isolation region 114 is not limited thereto. For example, the device isolation region 114 may have a multilayer structure including a combination of at least three kinds of insulating films.

A plurality of word line trenches 118 are formed in the substrate 110. The word line trenches 118 extend parallel to each other, and each may have a line shape crossing the active region 116. As shown in fig. 4B, the device isolation region 114 and the substrate 110 are etched by performing a separate etching process to form word line trenches 118, each word line trench 118 having a lower surface in the form of a step, and thus, the etching depth of the device isolation region 114 may be different from that of the substrate 110.

A gate dielectric layer 122, a word line 124, and a buried insulating layer 126 are sequentially formed in each word line trench 118. In at least one embodiment, after forming word line 124, impurity ions may be implanted into substrate 110 on both sides of word line 120 using word line 124 as a mask to form source/drain regions on active region 116.

Source region 116S is shown in fig. 4A. A direct contact DC may be connected to source region 116S. In at least one embodiment, prior to forming the word line 124, an impurity ion implantation process may be performed to form source/drain regions.

The surface 124T of the word line 124 may be lower than the surface 110T of the substrate 110. The lower surface of the word line 124 may have an uneven shape, and a saddle fin transistor (saddle FinFET) may be formed in the active region 116. In at least one embodiment, the word line 124 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicide nitride (TiSiN), and tungsten silicide nitride (WSiN).

The gate dielectric layer 122 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide/nitride/oxide (ONO) layer, and a high-k dielectric layer having a dielectric constant higher than that of the silicon oxide layer. For example, the gate dielectric layer 122 may have a dielectric constant of about 10 to 25.

In at least one embodiment, the gate dielectric layer 122 may include at least one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), Yttrium Oxide (YO), aluminum oxide (AlO), and lead tantalum scandium oxide (pbtaso). In addition, the gate dielectric layer 122 may include hafnium oxide (HfO)₂) Aluminum oxide (Al)₂O₃) Hafnium aluminum oxide (HfAlO)₃) Tantalum oxide (Ta)₂O₃) Or titanium oxide (TiO)₂)。

The surface 126T of the buried insulating layer 126 may be located at approximately the same level as the surface 110T (upper surface) of the substrate 110. The buried insulating layer 126 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.

As shown in fig. 4A, an interlayer insulating layer 130 is formed in the substrate 110. The interlayer insulating layer 130 may include a first insulating layer 130a, a second insulating layer 130b, and a third insulating layer 130 c. The interlayer insulating layer 130 may include a single insulating layer, as needed. The interlayer insulating layer 130 may include a contact hole 130H, and the contact hole 130H exposes the source region 116S in the active region 116.

The bit line BL140 is formed on the interlayer insulating layer 130, the contact hole 130H, and the buried insulating layer 126. The bit line BL140 may extend in a first direction (Y direction in fig. 1). For example, the bit line BL140 may be formed by sequentially stacking impurity-doped polysilicon 142, tungsten nitride 144, tungsten 146, and a cap insulating layer 148. Impurity-doped polysilicon 142 formed in contact hole 130H in bit line BL140 may constitute direct contact 135 electrically connected to source region 116S.

The bit line BL140 may include a first conductive line CL1 and a second conductive line CL 2. The first conductive line CL1 may be formed on the active region 116 of the substrate 110 or on the buried insulating layer 126. The second conductive line CL2 may be formed on the interlayer insulating layer 130 on the substrate 110 or on the buried insulating layer 126.

Referring to fig. 5, a first insulating liner 152a is formed on a sidewall and a surface of the bit line BL 140. The first insulating liner 152a formed on the sidewall and surface of the bit line BL140 may become an inner spacer through a subsequent process. In addition, an insulating liner 152 is formed in the contact hole 130H exposing the source region 116S of the active region 116.

The insulating liner 152 may include a first insulating liner 152a, a second insulating liner 152b, and a third insulating liner 152c sequentially formed from the first conductive line CL1, i.e., one sidewall of the direct contact 135. The first insulating liner 152a formed on the sidewall and surface of the bit line BL140 and the first insulating liner 152a formed in the contact hole 130H may be formed through the same process.

The insulating liner 152 formed in the contact hole 130H may be formed to protect the lower portion of the first conductive line CL 1. The first, second, and third insulating pads 152a, 152b, and 152c may include a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer, respectively.

Due to the insulating liner 152 formed in the contact hole 130H, the first conductive line CL1, i.e., the direct contact 135, may be divided into a protruding conductive line PCL protruding from the surface 110T of the substrate 110 and a buried conductive line BCL formed under the surface 110T of the substrate 110.

Referring to fig. 6 and 7, as shown in fig. 6, an insulating film 154 for spacers is formed on the entire surface of the first insulating liner 152a formed on the sidewall and surface of the bit line BL140 and the substrate 110 in which the insulating liner 152 formed in the contact hole 130H is formed.

The insulating film 154 for the spacer may include a material having an etching selectivity with respect to the first insulating liner 152a formed on the sidewall and the surface of the bit line BL140 and the first insulating liner 152a formed in the contact hole 130H. The insulating film 154 for the spacer may include a silicon oxide layer. The insulating film 154 for the spacer may be an outer spacer or an air spacer by a subsequent manufacturing process.

As shown in fig. 7, a material film 156 for a mask is formed over the entire surface of the substrate 110 over which the insulating film 154 for spacers is formed. A material film 156 for a mask may be formed on the insulating film 154 for a spacer on the side wall and the surface of the bit line BL 140. The material film 156 for a mask may include a material having etching selectivity with respect to the first insulating layer 130a and the insulating film 154 for a spacer. The material film 156 for the mask may include a titanium nitride film (TiN).

Referring to fig. 8 and fig. 9A and 9B, fig. 9A illustrates a state in which the mask spacer 156a of fig. 8 is removed. Fig. 9B is a partially enlarged view of fig. 9A.

In more detail, the first insulating liner 152a formed on the bit line BL140 and the interlayer insulating layer 130 serves as an etching stopper film, and the material film 156 (of fig. 7) for the mask, the insulating film 154 (of fig. 7) for the spacer, and the third insulating liner 152c are etched back to form the first outer spacer 154a and the mask spacer 156 a. The first outer spacer 154a may be an air spacer as described below.

When the first outer spacer 154a and the mask spacer 156a are formed, the insulating film 154 for spacers and the material film 156 for mask on the first insulating liner 152a on the surface of the bit line BL140 may be removed. When the first outer spacer 154a and the mask spacer 156a are formed, the insulating film 154 for a spacer and the material film 156 for a mask on the first insulating liner 152a on the interlayer insulating layer 130 between the first conductive line CL1 and the second conductive line CL2 may be removed.

Also, when the first outer spacer 154a and the mask spacer 156a are formed, the third insulating liner 152c on the surface 110T of the substrate 110 among the insulating liners 152 may also be etched. Accordingly, as shown in fig. 9B, the insulating pad 152 may be divided into an upper insulating pad 152U and a lower insulating pad 152L, the upper insulating pad 152U being higher than the surface 110T of the substrate 110 on both sides of the protruding conductive line PCL, and the lower insulating pad 152L being lower than the surface 110T of the substrate on both sides of the buried conductive line BCL.

When the first outer spacers 154a and the mask spacers 156a are formed, the sidewalls SL1 of the upper insulating liner 152U may be perpendicular to the surface 110T of the substrate 110. If necessary, when the third insulating liner 152c is further etched using the mask spacer 156a as an etching mask or the mask spacer 156a is removed, the sidewall SL1 of the upper insulating liner 152U may be perpendicular to the surface 110T of the substrate 110. When the third insulation pad 152c is further etched or the mask spacer 156a is removed, the width of the upper insulation pad 152U may be reduced.

When the sidewall SL1 of the upper insulating liner 152U is vertical, etching of the subsequent insulating film 162 (of fig. 10A and 10B) for the spacer may be facilitated, and the lower opening length CR1 of the buried contact BC may be enlarged as described above, and thus device characteristics such as contact resistance may be reduced. In addition, the first outer spacer 154a and the mask spacer 156a may be formed on the first insulating liner 152a on the sidewall of the bit line BL140 through a previous manufacturing process.

Subsequently, by etching the lower portion of the first outer spacer 154a and the first insulating layer 130a using the mask spacer 156a as an etching mask, a first recess portion 158a, a second recess portion 158b, and an additional recess portion 158c are formed. The first recess portion 158a may be a portion in which a lower portion of the first outer spacer 154a on the upper insulating liner 152U is recessed toward the first conductive line CL 1. The second recess portion 158b may be a portion in which a lower portion of the first outer spacer 154a on the first insulating liner 152a on the interlayer insulating layer 130 is recessed toward the second conductive line CL 2. The additional recessed portion 158c may be a portion in which one sidewall of the first insulating layer 130a in the interlayer insulating layer 130 is recessed toward the second conductive line CL 2.

In at least one embodiment, when the first outer spacer 154a is wet-etched, one section of the first and second recess portions 158a and 158b adjacent to the first insulation pad 152a may be circular. One cross section of the additional recessed portion 158c formed in the first insulating layer 130a adjacent to the device isolation region 114 may be circular. The additional recess portion 158c may not be formed, as needed.

Referring to fig. 10A and 10B, an insulating film 162 for spacers is formed on the entire surface of the substrate 110 on which the interlayer insulating layer 130, the insulating liner 152, and the first outer spacers 154a on the sidewalls and surface of the bit lines BL140 are formed, while the first recess portion 158a, the second recess portion 158B, and the additional recess portion 158c are filled. The insulating film 162 for the spacer may include a silicon nitride layer. The insulating film 162 for the spacer may become an outer spacer by a subsequent manufacturing process.

Accordingly, the first and second barrier layers 162a and 162b may be formed on the first and second recess portions 158a and 158b, respectively. The first and second barrier layers 162a and 162b protrude toward the first and second conductive lines CL1 and CL2, respectively, and may extend from the insulating film 162 for the spacer. The third barrier layer 162c protrudes toward the first insulating layer 130a, and may extend from the insulating film 162 for the spacer.

Referring to fig. 11 and 12, as shown in fig. 11, the first insulating liner 152a formed on the bit line BL140 and the interlayer insulating layer 130 serves as an etching stopper film, and the insulating film 162 (of fig. 10A) for the spacer and a portion on the substrate 110 are etched back to form the second outer spacer 164 and the contact hole 166. Buried contacts may be formed in contact holes 166 by a subsequent fabrication process.

Next, as shown in fig. 12, a conductive layer 168 is formed on the entire surface of the resultant product in which the bit line BL140 and the second external spacer 164 are formed, while the contact hole 166 is filled. That is, the conductive layer 168 is formed to fill the contact hole 166 between the first conductive line CL1 and the second conductive line CL 2.

Referring to fig. 13 and 14, as shown in fig. 13, the conductive layer 168 and the first insulating pad 152a on the bit line BL140 are etched back. Accordingly, the spacer 163 is formed on a sidewall of the bit line BL140, i.e., one sidewall of the first and second conductive lines CL1 and CL 2. The spacer 163 includes an inner spacer 152d formed on one sidewall of the bit line BL140, and a first outer spacer 154a and a second outer spacer 164 sequentially formed on one sidewall of the inner spacer 152 d.

As shown in fig. 14, the first outer spacers 154a are etched to form the air spacers 170. The spacer 163a includes an inner spacer 152d formed on one sidewall of the bit line BL140, and an air spacer 170 and a second outer spacer 164 sequentially formed on one sidewall of the inner spacer 152 d. The semiconductor device can be manufactured by such a manufacturing process.

Fig. 15 to 22 are sectional views of main portions of a semiconductor device for explaining a method of manufacturing a semiconductor device according to at least one embodiment of the inventive concept.

In more detail, fig. 15 to 22 are sectional views of main portions of the semiconductor device taken along line I-I' of fig. 1. In fig. 15 to 22, the same reference numerals as in fig. 2 and 3 denote the same elements. Fig. 5 to 22 may be the same as fig. 4A to 14 except that an additional outer spacer 204 is further formed on one sidewall of the first outer spacer 154A. In fig. 5 to 22, the same reference numerals as in fig. 4A to 14 denote the same elements, and a repetitive description thereof will not be given here.

Referring to fig. 15, the manufacturing processes of fig. 4A to 6 are performed as described above. Next, as shown in fig. 15, a material film 202 for oxidation is formed over the entire surface of the substrate 110 over which the insulating film 154 for spacers is formed. A material film 202 for oxidation may be formed on the insulating film 154 for spacers on the side walls and surface of the bit line BL 140. The material film 202 for oxidation may include a material that can be converted into a silicon oxide layer by heat treatment. The material film 202 for oxidation may include a polysilicon film.

Referring to fig. 16, 17A, and 17B, fig. 17A illustrates a state in which the material spacer 202a for oxidation illustrated in fig. 16 is oxidized. Fig. 17B is a partially enlarged view of fig. 17A.

Referring to fig. 16, the first insulating liner 152a formed on the bit line BL140 and the interlayer insulating layer 130 serves as an etch stop film, and the material film 202 (of fig. 15) for oxidation, the insulating film 154 (of fig. 15) for spacers, and the third insulating liner 152c are etched back to form the first outer spacers 154a and the material spacers 202a for oxidation. The first outer spacer 154a may be an air spacer as described below.

When the first outer spacer 154a and the material spacer 202a for oxidation are formed, the insulating film 154 for spacer and the material film 202 for oxidation on the first insulating liner 152a on the surface of the bit line BL140 may be removed. When the first outer spacer 154a and the material spacer 202a for oxidation are formed, the material film 202 for oxidation and the insulating film 154 for spacer on the first insulating liner 152a on the interlayer insulating layer 130 between the first conductive line CL1 and the second conductive line CL2 may be removed.

Also, when the first outer spacer 154a and the material spacer 202a for oxidation are formed, the third insulating liner 152c on the surface 110T of the substrate 110 among the insulating liners 152 may also be etched. Accordingly, as shown in fig. 17B, the insulating pad 152 may be divided into an upper insulating pad 152U and a lower insulating pad 152L, the upper insulating pad 152U being higher than the surface 110T of the substrate on both sides of the protruding conductive line PCL, and the lower insulating pad 152L being lower than the surface 110T of the substrate on both sides of the buried conductive line BCL.

When the first outer spacer 154a and the spacer 202a of the material for oxidation are formed, the sidewall SL1 of the upper insulating liner 152U may be perpendicular to the surface 110T of the substrate 110. When the sidewall SL1 of the upper insulating liner 152U is vertical, the lower opening length CR1 of the buried contact BC may be enlarged as described above, and thus device characteristics such as contact resistance may be reduced. In addition, the first outer spacer 154a and the material spacer 202a for oxidation may be formed on the first insulating liner 152a on the sidewall of the bit line BL140 by a previous manufacturing process.

Next, by etching the lower portion of the first outer spacer 154a and the first insulating layer 130a using the material spacer 202a for oxidation as an etching mask, a first recess portion 158a, a second recess portion 158b, and an additional recess portion 158c are formed. The first, second and additional recessed portions 158a, 158b and 158c will be omitted since they are described above.

Subsequently, the material spacers 202a for oxidation are oxidized to form additional outer spacers 204 outside the first outer spacers 154 a. The oxidation of the material spacers 202a for oxidation may be performed using a wet annealing process.

Referring to fig. 18A and 18B, an insulating film 162 for spacers is formed on the entire surface of the substrate 110 on which the interlayer insulating layer 130, the insulating liner 152, and the first outer spacers 154a on the sidewalls and surface of the bit lines BL140 are formed, while the first recess portion 158A, the second recess portion 158B, and the additional recess portion 158c are filled. The insulating film 162 for the spacer may include a silicon nitride layer. The insulating film 162 for the spacer may become an outer spacer by a subsequent manufacturing process.

Accordingly, the first and second barrier layers 162a and 162b may be formed on the first and second recess portions 158a and 158b, respectively. The first and second barrier layers 162a and 162b protrude toward the first and second conductive lines CL1 and CL2, respectively, and may extend from the insulating film 162 for the spacer. The third barrier layer 162c protrudes toward the first insulating layer 130a, and may extend from the insulating film 162 for the spacer.

Referring to fig. 19 and 20, as shown in fig. 19, the first insulating liner 152a formed on the bit line BL140 and the interlayer insulating layer 130 serves as an etching stopper film, and the insulating film 162 (of fig. 18A) for the spacer and a portion on the substrate 110 are etched back to form the second outer spacer 164 and the contact hole 166. Buried contacts may be formed in contact holes 166 by a subsequent fabrication process.

Next, as shown in fig. 20, a conductive layer 168 is formed on the entire surface of the resultant product in which the bit line BL140 and the second external spacer 164 are formed, while the contact hole 166 is filled. That is, the conductive layer 168 is formed to fill the contact hole 166 between the first conductive line CL1 and the second conductive line CL 2.

Referring to fig. 21 and 22, as shown in fig. 21, the conductive layer 168 and the first insulating pad 152a on the bit line BL140 are etched back. Accordingly, the spacer 163b is formed on a sidewall of the bit line BL140, i.e., one sidewall of the first and second conductive lines CL1 and CL 2. The spacer 163b includes an inner spacer 152d formed on one sidewall of the bit line BL140, and a first outer spacer 154a, an additional outer spacer 204, and a second outer spacer 164 sequentially formed on one sidewall of the inner spacer 152 d.

As shown in fig. 22, the first outer spacers 154a are etched to form the air spacers 170. The spacer 163c includes an inner spacer 152d formed on one sidewall of the bit line BL140, and an air spacer 170, an additional outer spacer 204, and a second outer spacer 164 sequentially formed on one sidewall of the inner spacer 152 d. The semiconductor device can be manufactured by such a manufacturing process.

Fig. 23 is a view of a system including a semiconductor device according to at least one embodiment of the inventive concept.

In more detail, the system 1000 according to at least one embodiment may include a controller 1010, an input/output device 1020, a memory device 1030, and/or an interface 1040. Electronic system 1000 may be a mobile system, or a system for transmitting and receiving information. In at least one embodiment, the mobile system may be a Personal Digital Assistant (PDA), a portable computer, a web tablet, a wireless telephone, a mobile telephone, a digital music player, or a memory card.

The controller 1010, which may be an executable program for controlling the system 1000, may comprise a microprocessor, digital signal processor, microcontroller, or similar device. Input/output devices 1020 may be used to input and output data for system 1000. The system 1000 can be connected to an external device such as a PC or a network by using the input/output means 1020, and can exchange data with the external device. The input/output device 1020 may be, for example, a keyboard, keypad, or display.

The memory device 1030 may store code and/or data for operating the controller 1010 or data processed in the controller 1010. The memory device 1030 may include a semiconductor device according to at least one embodiment of the inventive concept. For example, the memory device 1030 may include a semiconductor device manufactured by the above-described method.

The interface 1040 may be a data transmission path between the system 1000 and an external device. The controller 1010, the input/output device 1020, the memory device 1030, and the interface 1040 may communicate with each other via a bus 1050.

The system 1000 according to at least one embodiment may be used in a mobile phone, an MP3 player, a navigation, a Portable Multimedia Player (PMP), a Solid State Disk (SSD), or a home appliance.

The semiconductor device of the inventive concept can improve device characteristics without short-circuiting even when the distance between the conductive line and the contact pattern is reduced. The semiconductor device of the inventive concept can reduce device characteristics such as contact resistance by making the sidewall of the upper insulating liner vertical and increasing the lower length of the buried contact.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

This application claims the benefit of korean patent application No. 10-2018-0088153, filed in the korean intellectual property office at 27.7.2018, the disclosure of which is incorporated herein by reference in its entirety.