阅读说明：本技术 基于高压输入及esd防护的gpio复用电路 (GPIO multiplexing circuit based on high-voltage input and ESD protection ) 是由 韩红娟 江猛 范佳敏 雷红军 杭晓伟 于 2019-11-07 设计创作，主要内容包括：本发明揭示了一种基于高压输入及ESD防护的GPIO复用电路,所述GPIO复用电路包括与IO端口相连的高压输入模块、IO端口功能模块、及ESD防护模块,所述高压输入模块为带开关控制的高压传输结构,其包括若干MOS管及电阻,IO端口功能模块包括若干MOS管及电阻,ESD防护模块包括若干MOS管及电阻。本发明GPIO复用电路在普通的CMOS工艺且不使用特殊器件下,通过普通的MOS管和电阻,即可实现带开关控制的高压输入脚与GPIO口的复用,且有着可靠的ESD防护。(The invention discloses a GPIO multiplexing circuit based on high-voltage input and ESD protection, which comprises a high-voltage input module connected with an IO port, an IO port function module and an ESD protection module, wherein the high-voltage input module is a high-voltage transmission structure with switch control and comprises a plurality of MOS (metal oxide semiconductor) tubes and resistors, the IO port function module comprises a plurality of MOS tubes and resistors, and the ESD protection module comprises a plurality of MOS tubes and resistors. The GPIO multiplexing circuit can realize the multiplexing of a high-voltage input pin with switch control and a GPIO port through a common MOS tube and a resistor under the common CMOS process without using special devices, and has reliable ESD protection.)

1. The utility model provides a GPIO multiplexing circuit based on high-pressure input and ESD protection, its characterized in that, GPIO multiplexing circuit includes high-pressure input module, IO port functional module and the ESD protection module that links to each other with the IO port, high-pressure input module is the high-pressure transmission structure of band-pass switch control, and it includes a plurality of MOS pipes and resistance, IO port functional module includes a plurality of MOS pipes and resistance, and the ESD protection module includes a plurality of MOS pipes and resistance.

2. The GPIO multiplexing circuit based on high voltage input and ESD protection of claim 1, wherein the high voltage input module comprises MOS transistors M1-M11 and resistors R1-R3, wherein:

MOS tube M1, MOS tube M2 are connected with IO port, MOS tube M3 is connected with MOS tube M1, MOS tube M4 is connected with MOS tube M2, MOS tube M1 is connected with MOS tube M4, MOS tube M2 is connected with MOS tube M3, MOS tube M5 and MOS tube M6 are connected with MOS tube M3 and MOS tube M4 respectively, MOS tube M7 and MOS tube M8 are connected with enable port VEN and MOS tube M3 respectively, MOS tube M5 and MOS tube M7 are connected with power supply voltage VCC respectively, MOS tube M3, MOS tube M4, MOS tube M6 and MOS tube M8 are connected with common voltage VSS respectively;

the MOS transistor M9 is connected between the IO port and the common voltage VSS;

the MOS transistor M10 is connected between the IO port and the output port VOUT;

the MOS transistor M11 is connected between the enable port VEN and the output port VOUT, and the MOS transistor M11 is connected with the common voltage VSS;

the resistor R1 is connected among the MOS tube M1, the MOS tube M2 and the IO port;

the resistor R2 is connected between the MOS transistor M10 and the MOS transistor M2;

the resistor R3 is connected between the MOS transistor M11 and the output port VOUT.

3. The GPIO multiplexing circuit based on high voltage input and ESD protection as claimed in claim 2, wherein MOS transistor M1, MOS transistor M2, MOS transistor M5, MOS transistor M7, and MOS transistor M10 are PMOS transistors, and MOS transistor M3, MOS transistor M4, MOS transistor M6, MOS transistor M8, MOS transistor M9, and MOS transistor M11 are NMOS transistors.

4. The GPIO multiplexing circuit based on high-voltage input and ESD protection of claim 2, wherein in the high-voltage input module:

the source electrode of the MOS transistor M1 is connected with the resistor R1, the drain electrode is connected with the drain electrode of the MOS transistor M3 and the grid electrode of the MOS transistor M2, and the grid electrode is connected with the drain electrode of the MOS transistor M2 and the drain electrode of the MOS transistor M4;

the source electrode of the MOS transistor M2 is connected with the resistor R1, the drain electrode is connected with the grid electrode of the MOS transistor M1 and the drain electrode of the MOS transistor M4, and the grid electrode is connected with the drain electrodes of the MOS transistor M1 and the MOS transistor M3 and the resistor R2;

the grid electrode of the MOS tube M3 is connected with the grid electrodes of the MOS tube M5 and the MOS tube M6, the drain electrodes of the MOS tube M7 and the MOS tube M8, the source electrode is connected with the common voltage VSS, and the drain electrode is connected with the drain electrode of the MOS tube M1 and the grid electrode of the MOS tube M2;

the grid electrode of the MOS transistor M4 is connected with the drain electrodes of the MOS transistor M5 and the MOS transistor M6, the source electrode is connected with the common voltage VSS, and the drain electrode is connected with the drain electrode of the MOS transistor M2 and the grid electrode of the MOS transistor M1;

the source electrode of the MOS tube M5 is connected with a power supply voltage VCC, the drain electrode of the MOS tube M5 is connected with the drain electrode of the MOS tube M6 and the grid electrode of the MOS tube M4, the source electrode of the MOS tube M6 is connected with a common voltage VSS, and the grid electrode of the MOS tube M5 and the grid electrode of the MOS tube M6 are connected with the grid electrode of the MOS tube M3 and the drain electrodes of the MOS tube M7 and the MOS tube M8;

the source electrode of the MOS tube M7 is connected with a power supply voltage VCC, the drain electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M8, the source electrode of the MOS tube M8 is connected with a common voltage VSS, and the grid electrode of the MOS tube M7 and the grid electrode of the MOS tube M8 are respectively connected with an enable port VEN;

the drain electrode of the MOS transistor M9 is connected with the IO port, the source electrode is connected with the common voltage VSS, and the grid electrode is connected with the source electrode;

the source electrode of the MOS transistor M10 is connected with the IO port, the drain electrode is connected with the output port VOUT, the grid electrode is connected with the resistor R2, and the substrate is connected with the IO port;

the grid electrode of the MOS transistor M11 is connected with an enable port VEN, the drain electrode of the MOS transistor M11 is connected with a resistor R3 and then connected with an output port VOUT, and the source electrode of the MOS transistor M11 is connected with a common voltage VSS;

the resistor R1 is connected between the source electrode of the MOS tube M1, the source electrode of the MOS tube M2 and the IO port;

the resistor R2 is connected between the grid of the MOS transistor M10 and the grid of the MOS transistor M2;

the resistor R3 is connected between the drain of the MOS transistor M11 and the output port VOUT.

5. The GPIO multiplexing circuit based on high voltage input and ESD protection as claimed in claim 4, wherein in the high voltage input module, the VEN input at the enable port is active low, the MOS transistor M3 is turned on, the MOS transistor M2 is turned on, the MOS transistor M1 is turned off, the MOS transistor M10 is turned on, the voltage at the resistor R2 is low, the voltage at the resistor R1 is consistent with the voltage at the IO port, and the output port VOUT outputs a voltage close to the IO port.

6. The GPIO multiplexing circuit based on high voltage input and ESD protection of claim 1, wherein the IO port function block comprises MOS transistors M12, M13 and a resistor R4, wherein:

the source electrode of the MOS transistor M12 is connected with a power supply voltage VCC, the grid electrode of the MOS transistor M12 is connected with an input port IN1, and the drain electrode of the MOS transistor M12 is connected with a resistor R4;

the drain electrode of the MOS transistor M13 is connected with the resistor R4, the source electrode is connected with the common voltage VSS, and the grid electrode is connected with the input port IN 2;

the resistor R4 is positioned between the drain electrode of the MOS transistor M12 and the drain electrode of the MOS transistor M13;

the drain of the MOS transistor M12 is connected to the input port IO _ IN, and the drain of the MOS transistor M13 is connected to the IO port.

7. The GPIO multiplexing circuit based on high voltage input and ESD protection of claim 6, wherein the MOS transistor M12 is PMOS transistor and MOS transistor M13 is NMOS transistor.

8. The GPIO multiplexing circuit based on high voltage input and ESD protection as claimed IN claim 6, wherein IN the IO port functional module, when the high voltage transmission is turned off, the IO port is used as a normal input and output, the input port IN1 is at low level, the IO port outputs high level when the input port IN2 is at low level, the IO port outputs low level when the input port IN1 is at high level and the input port IN2 is at high level, the IO port outputs high resistance state when the input port IN1 is at high level and the input port IN2 is at low level, and the input port IO _ IN inputs level through the IO port.

9. The GPIO multiplexing circuit based on high voltage input and ESD protection of claim 1, wherein the ESD protection module comprises MOS transistors M14, M15 and resistors R5-R7, wherein:

the source electrode of the MOS transistor M14 is connected with a power supply voltage VCC, the grid electrode is connected with the source electrode, and the drain electrode is connected with a resistor R5;

the drain electrode of the MOS transistor M15 is connected with the resistor R5, the source electrode is connected with the common voltage VSS, and the grid electrode is connected with the source electrode;

the resistor R5 is positioned between the drain electrode of the MOS transistor M14 and the drain electrode of the MOS transistor M15;

the resistor R6 is positioned between the gate and the source of the MOS transistor M14;

the resistor R7 is positioned between the gate and the source of the MOS transistor M15;

the drain of the MOS transistor M15 is connected to the IO port.

10. The GPIO multiplexing circuit based on high voltage input and ESD protection of claim 9, wherein the MOS transistor M14 is PMOS transistor and MOS transistor M15 is NMOS transistor.

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a GPIO multiplexing circuit based on high-voltage input and ESD protection.

Background

GPIO function is more and more complicated, and when the pin is the high-voltage input pin of taking on-off control, ordinary IO port structure just is not suitable for this, and ordinary ESD protection is also not suitable for this pin simultaneously.

Therefore, in view of the above technical problems, it is necessary to provide a GPIO multiplexing circuit based on high voltage input and ESD protection.

Disclosure of Invention

The invention aims to provide a GPIO multiplexing circuit based on high-voltage input and ESD protection, which is used for realizing multiplexing of a high-voltage input pin with switch control and a GPIO port and has reliable ESD protection.

In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:

the utility model provides a GPIO multiplexing circuit based on high-pressure input and ESD protection, GPIO multiplexing circuit includes high-pressure input module, IO port functional module and the ESD protection module that links to each other with the IO port, high-pressure input module is the high-pressure transmission structure who takes on-off control, and it includes a plurality of MOS pipes and resistance, IO port functional module includes a plurality of MOS pipes and resistance, and the ESD protection module includes a plurality of MOS pipes and resistance.

In one embodiment, the high voltage input module includes MOS transistors M1-M11 and resistors R1-R3, wherein:

MOS tube M1, MOS tube M2 are connected with IO port, MOS tube M3 is connected with MOS tube M1, MOS tube M4 is connected with MOS tube M2, MOS tube M1 is connected with MOS tube M4, MOS tube M2 is connected with MOS tube M3, MOS tube M5 and MOS tube M6 are connected with MOS tube M3 and MOS tube M4 respectively, MOS tube M7 and MOS tube M8 are connected with enable port VEN and MOS tube M3 respectively, MOS tube M5 and MOS tube M7 are connected with power supply voltage VCC respectively, MOS tube M3, MOS tube M4, MOS tube M6 and MOS tube M8 are connected with common voltage VSS respectively;

the MOS transistor M9 is connected between the IO port and the common voltage VSS;

the MOS transistor M10 is connected between the IO port and the output port VOUT;

the MOS transistor M11 is connected between the enable port VEN and the output port VOUT, and the MOS transistor M11 is connected with the common voltage VSS;

the resistor R1 is connected among the MOS tube M1, the MOS tube M2 and the IO port;

the resistor R2 is connected between the MOS transistor M10 and the MOS transistor M2;

the resistor R3 is connected between the MOS transistor M11 and the output port VOUT.

In an embodiment, the MOS transistor M1, the MOS transistor M2, the MOS transistor M5, the MOS transistor M7, and the MOS transistor M10 are PMOS transistors, and the MOS transistor M3, the MOS transistor M4, the MOS transistor M6, the MOS transistor M8, the MOS transistor M9, and the MOS transistor M11 are NMOS transistors.

In one embodiment, the high voltage input module comprises:

the source electrode of the MOS transistor M1 is connected with the resistor R1, the drain electrode is connected with the drain electrode of the MOS transistor M3 and the grid electrode of the MOS transistor M2, and the grid electrode is connected with the drain electrode of the MOS transistor M2 and the drain electrode of the MOS transistor M4;

the source electrode of the MOS transistor M2 is connected with the resistor R1, the drain electrode is connected with the grid electrode of the MOS transistor M1 and the drain electrode of the MOS transistor M4, and the grid electrode is connected with the drain electrodes of the MOS transistor M1 and the MOS transistor M3 and the resistor R2;

the grid electrode of the MOS tube M3 is connected with the grid electrodes of the MOS tube M5 and the MOS tube M6, the drain electrodes of the MOS tube M7 and the MOS tube M8, the source electrode is connected with the common voltage VSS, and the drain electrode is connected with the drain electrode of the MOS tube M1 and the grid electrode of the MOS tube M2;

the grid electrode of the MOS transistor M4 is connected with the drain electrodes of the MOS transistor M5 and the MOS transistor M6, the source electrode is connected with the common voltage VSS, and the drain electrode is connected with the drain electrode of the MOS transistor M2 and the grid electrode of the MOS transistor M1;

the source electrode of the MOS tube M5 is connected with a power supply voltage VCC, the drain electrode of the MOS tube M5 is connected with the drain electrode of the MOS tube M6 and the grid electrode of the MOS tube M4, the source electrode of the MOS tube M6 is connected with a common voltage VSS, and the grid electrode of the MOS tube M5 and the grid electrode of the MOS tube M6 are connected with the grid electrode of the MOS tube M3 and the drain electrodes of the MOS tube M7 and the MOS tube M8;

the source electrode of the MOS tube M7 is connected with a power supply voltage VCC, the drain electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M8, the source electrode of the MOS tube M8 is connected with a common voltage VSS, and the grid electrode of the MOS tube M7 and the grid electrode of the MOS tube M8 are respectively connected with an enable port VEN;

the drain electrode of the MOS transistor M9 is connected with the IO port, the source electrode is connected with the common voltage VSS, and the grid electrode is connected with the source electrode;

the source electrode of the MOS transistor M10 is connected with the IO port, the drain electrode is connected with the output port VOUT, the grid electrode is connected with the resistor R2, and the substrate is connected with the IO port;

the grid electrode of the MOS transistor M11 is connected with an enable port VEN, the drain electrode of the MOS transistor M11 is connected with a resistor R3 and then connected with an output port VOUT, and the source electrode of the MOS transistor M11 is connected with a common voltage VSS;

the resistor R1 is connected between the source electrode of the MOS tube M1, the source electrode of the MOS tube M2 and the IO port;

the resistor R2 is connected between the grid of the MOS transistor M10 and the grid of the MOS transistor M2;

the resistor R3 is connected between the drain of the MOS transistor M11 and the output port VOUT.

In one embodiment, in the high-voltage input module, the low level of the venn input at the enable port is active, the MOS transistor M3 is turned on, the MOS transistor M2 is turned on, the MOS transistor M1 is turned off, the MOS transistor M10 is turned on, the voltage at the resistor R2 is low, the voltage at the resistor R1 is consistent with the voltage at the IO port, and the voltage at the output port VOUT outputs a voltage close to the voltage at the IO port.

In one embodiment, the IO port function module includes MOS transistors M12, M13 and a resistor R4, wherein:

the source electrode of the MOS transistor M12 is connected with a power supply voltage VCC, the grid electrode of the MOS transistor M12 is connected with an input port IN1, and the drain electrode of the MOS transistor M12 is connected with a resistor R4;

the drain electrode of the MOS transistor M13 is connected with the resistor R4, the source electrode is connected with the common voltage VSS, and the grid electrode is connected with the input port IN 2;

the resistor R4 is positioned between the drain electrode of the MOS transistor M12 and the drain electrode of the MOS transistor M13;

the drain of the MOS transistor M12 is connected to the input port IO _ IN, and the drain of the MOS transistor M13 is connected to the IO port.

In one embodiment, the MOS transistor M12 is a PMOS transistor, and the MOS transistor M13 is an NMOS transistor.

IN an embodiment, IN the IO port functional module, when high voltage transmission is turned off, the IO port is used as a common input and output, when the input port IN1 is at a low level and the input port IN2 is at a low level, the IO port outputs a high level, when the input port IN1 is at a high level and the input port IN2 is at a high level, the IO port outputs a low level, when the input port IN1 is at a high level and the input port IN2 is at a low level, the IO port outputs a high impedance state, and the input port IO _ IN inputs a level through the IO port.

In one embodiment, the ESD protection module includes MOS transistors M14, M15, and resistors R5 to R7, wherein:

the source electrode of the MOS transistor M14 is connected with a power supply voltage VCC, the grid electrode is connected with the source electrode, and the drain electrode is connected with a resistor R5;

the drain electrode of the MOS transistor M15 is connected with the resistor R5, the source electrode is connected with the common voltage VSS, and the grid electrode is connected with the source electrode;

the resistor R5 is positioned between the drain electrode of the MOS transistor M14 and the drain electrode of the MOS transistor M15;

the resistor R6 is positioned between the gate and the source of the MOS transistor M14;

the resistor R7 is positioned between the gate and the source of the MOS transistor M15;

the drain of the MOS transistor M15 is connected to the IO port.

In one embodiment, the MOS transistor M14 is a PMOS transistor, and the MOS transistor M15 is an NMOS transistor.

In one embodiment, the MOS transistor M14 is a PMOS transistor, and the MOS transistor M15 is an NMOS transistor.

Compared with the prior art, the invention has the following advantages:

the GPIO multiplexing circuit can realize the multiplexing of a high-voltage input pin with switch control and a GPIO port through a common MOS tube and a resistor under the common CMOS process without using special devices, and has reliable ESD protection.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a block diagram of a GPIO multiplexing circuit according to the present invention;

FIG. 2 is a schematic circuit diagram of a high voltage input module according to an embodiment of the present invention;

FIG. 3 is a schematic circuit diagram of an IO port functional module according to an embodiment of the present invention;

fig. 4 is a schematic circuit diagram of an ESD protection module according to an embodiment of the invention.

Detailed Description

The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.

Referring to fig. 1, the invention discloses a GPIO multiplexing circuit based on high voltage input and ESD protection, the GPIO multiplexing circuit includes a high voltage input module connected to an IO port, an IO port function module, and an ESD protection module, the high voltage input module is a high voltage transmission structure with switch control, and includes a plurality of MOS transistors and resistors, the IO port function module includes a plurality of MOS transistors and resistors, and the ESD protection module includes a plurality of MOS transistors and resistors.

The present invention is further described below in conjunction with various modules.

A high-voltage input module:

referring to fig. 2, the high voltage input module in this embodiment includes MOS transistors M1-M11 and resistors R1-R3, wherein MOS transistor M1, MOS transistor M2, MOS transistor M5, MOS transistor M7, and MOS transistor M10 are PMOS transistors, and MOS transistor M3, MOS transistor M4, MOS transistor M6, MOS transistor M8, MOS transistor M9, and MOS transistor M11 are NMOS transistors.

In the embodiment, a MOS transistor M1 and a MOS transistor M2 are connected with an IO port, a MOS transistor M3 is connected with a MOS transistor M1, a MOS transistor M4 is connected with a MOS transistor M2, a MOS transistor M1 is connected with a MOS transistor M4, a MOS transistor M2 is connected with a MOS transistor M3, a MOS transistor M5 and a MOS transistor M6 are connected with a MOS transistor M3 and a MOS transistor M4, a MOS transistor M7 and a MOS transistor M8 are respectively connected with an enable port VEN and a MOS transistor M3, a MOS transistor M5 and a MOS transistor M7 are respectively connected with a power supply voltage VCC, and a MOS transistor M3, a MOS transistor M4, a MOS transistor M6 and a MOS transistor M8 are respectively connected with a common voltage VSS;

the MOS transistor M9 is connected between the IO port and the common voltage VSS;

the MOS transistor M10 is connected between the IO port and the output port VOUT;

the MOS transistor M11 is connected between the enable port VEN and the output port VOUT, and the MOS transistor M11 is connected with the common voltage VSS;

the resistor R1 is connected among the MOS tube M1, the MOS tube M2 and the IO port;

the resistor R2 is connected between the MOS transistor M10 and the MOS transistor M2;

the resistor R3 is connected between the MOS transistor M11 and the output port VOUT.

Further:

the source electrode of the MOS transistor M1 is connected with the resistor R1, the drain electrode is connected with the drain electrode of the MOS transistor M3 and the grid electrode of the MOS transistor M2, and the grid electrode is connected with the drain electrode of the MOS transistor M2 and the drain electrode of the MOS transistor M4;

the source electrode of the MOS transistor M2 is connected with the resistor R1, the drain electrode is connected with the grid electrode of the MOS transistor M1 and the drain electrode of the MOS transistor M4, and the grid electrode is connected with the drain electrodes of the MOS transistor M1 and the MOS transistor M3 and the resistor R2;

the grid electrode of the MOS tube M3 is connected with the grid electrodes of the MOS tube M5 and the MOS tube M6, the drain electrodes of the MOS tube M7 and the MOS tube M8, the source electrode is connected with the common voltage VSS, and the drain electrode is connected with the drain electrode of the MOS tube M1 and the grid electrode of the MOS tube M2;

the grid electrode of the MOS transistor M4 is connected with the drain electrodes of the MOS transistor M5 and the MOS transistor M6, the source electrode is connected with the common voltage VSS, and the drain electrode is connected with the drain electrode of the MOS transistor M2 and the grid electrode of the MOS transistor M1;

the source electrode of the MOS tube M5 is connected with a power supply voltage VCC, the drain electrode of the MOS tube M5 is connected with the drain electrode of the MOS tube M6 and the grid electrode of the MOS tube M4, the source electrode of the MOS tube M6 is connected with a common voltage VSS, and the grid electrode of the MOS tube M5 and the grid electrode of the MOS tube M6 are connected with the grid electrode of the MOS tube M3 and the drain electrodes of the MOS tube M7 and the MOS tube M8;

the source electrode of the MOS tube M7 is connected with a power supply voltage VCC, the drain electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M8, the source electrode of the MOS tube M8 is connected with a common voltage VSS, and the grid electrode of the MOS tube M7 and the grid electrode of the MOS tube M8 are respectively connected with an enable port VEN;

the drain electrode of the MOS transistor M9 is connected with the IO port, the source electrode is connected with the common voltage VSS, and the grid electrode is connected with the source electrode;

the source electrode of the MOS transistor M10 is connected with the IO port, the drain electrode is connected with the output port VOUT, the grid electrode is connected with the resistor R2, and the substrate is connected with the IO port;

the grid electrode of the MOS transistor M11 is connected with an enable port VEN, the drain electrode of the MOS transistor M11 is connected with a resistor R3 and then connected with an output port VOUT, and the source electrode of the MOS transistor M11 is connected with a common voltage VSS;

the resistor R1 is connected between the source electrode of the MOS tube M1, the source electrode of the MOS tube M2 and the IO port;

the resistor R2 is connected between the grid of the MOS transistor M10 and the grid of the MOS transistor M2;

the resistor R3 is connected between the drain of the MOS transistor M11 and the output port VOUT.

The high-voltage input module in the embodiment is a high-voltage transmission structure with switch control, the low level input of the VEN is enabled to be effective, the MOS tube M3 is turned on, the MOS tube M2 is turned on, the MOS tube M1 is turned off, the MOS tube M10 is turned on, the voltage at the resistor R2 is low, the voltage at the resistor R1 is consistent with the voltage at the IO port, and the output port VOUT outputs a voltage close to the IO port and is not clamped by the power supply voltage VCC; the high level of the VEN input of the enable port is invalid, the MOS tube M11 is opened, and the output of the output port VOUT is pulled low to be low level.

Wherein M10 is a large-sized PMOS tube, which meets the port ESD rule, the substrate is connected with the IO port, M9 is a large-sized ESD protection tube, R1, R2 and R3 are ESD protection resistors, and the protection related path is not an electrostatic path.

IO port function module:

referring to fig. 3, the IO port functional module in this embodiment includes MOS transistors M12 and M13 and a resistor R4, where the MOS transistor M12 is a PMOS transistor and the MOS transistor M13 is an NMOS transistor.

IN the present embodiment, the source of the MOS transistor M12 is connected to the power supply voltage VCC, the gate is connected to the input port IN1, and the drain is connected to the resistor R4;

the drain electrode of the MOS transistor M13 is connected with the resistor R4, the source electrode is connected with the common voltage VSS, and the grid electrode is connected with the input port IN 2;

the resistor R4 is positioned between the drain electrode of the MOS transistor M12 and the drain electrode of the MOS transistor M13;

the drain of the MOS transistor M12 is connected to the input port IO _ IN, and the drain of the MOS transistor M13 is connected to the IO port.

IN the IO port functional module of this embodiment, when high-voltage transmission is closed, the IO port can be used as a common input and output, the input port IN1 is a low level, when the input port IN2 is a low level, the IO port outputs a high level, the input port IN1 is a high level, when the input port IN2 is a high level, the IO port outputs a low level, the input port IN1 is a high level, when the input port IN2 is a low level, the IO port outputs a high impedance state, and the input port IO _ IN passes through the IO port input level.

The resistor R4 protects the input port IO _ IN from electrostatic charges, and the resistor R4 prevents the IO port from being clamped by the power supply voltage VCC when the IO port is applied with a high voltage.

An ESD protection module:

referring to fig. 4, the ESD protection module in this embodiment includes MOS transistors M14 and M15 and resistors R5 to R7, wherein the MOS transistor M14 is a PMOS transistor, and the MOS transistor M15 is an NMOS transistor.

In the embodiment, the source electrode of the MOS transistor M14 is connected to a power supply voltage VCC, the gate electrode is connected to the source electrode, and the drain electrode is connected to the resistor R5;

the drain electrode of the MOS transistor M15 is connected with the resistor R5, the source electrode is connected with the common voltage VSS, and the grid electrode is connected with the source electrode;

the resistor R5 is positioned between the drain electrode of the MOS transistor M14 and the drain electrode of the MOS transistor M15;

the resistor R6 is positioned between the gate and the source of the MOS transistor M14;

the resistor R7 is positioned between the gate and the source of the MOS transistor M15;

the drain of the MOS transistor M15 is connected to the IO port.

The MOS transistor M14 and the MOS transistor M15 in this embodiment are large-sized transistors conforming to the ESD rule, and are main leakage paths of static electricity, and the R5 can prevent the clamping of the power supply voltage VCC when the IO port is applied with a high voltage.

According to the technical scheme, the invention has the following beneficial effects:

the GPIO multiplexing circuit can realize the multiplexing of a high-voltage input pin with switch control and a GPIO port through a common MOS tube and a resistor under the common CMOS process without using special devices, and has reliable ESD protection.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.