阅读说明：本技术 一种数字电路输入管脚抗噪声电路 (Digital circuit input pin anti-noise circuit ) 是由 吴小光 李威力 于 2019-10-08 设计创作，主要内容包括：本发明涉及一种数字电路输入管脚抗噪声电路,包括信号滤波电路、信号整形电路,信号整形电路包括上升沿检测模块、下降沿检测模块、常零电平检测模块、常高电平检测模块、基本RS触发器模块。原始信号经信号滤波电路滤波后,同时发送至上升沿检测模块、下降沿检测模块、常零电平检测模块和常高电平检测模块；信号经过常零电平检测模块和下降沿检测模块检测处理后,发送至与门电路及基本RS触发器模块的复位端；信号经过常高电平检测模块和上升沿检测模块检测处理后,发送至与门电路及基本RS触发器模块的置位端；经基本RS触发器模块的输出端输出。本发明的优点是,可以极小的延迟滤除高频噪声,整形并去除信号畸变导致的不连续高低电平现象。(The invention relates to an anti-noise circuit for an input pin of a digital circuit, which comprises a signal filter circuit and a signal shaping circuit, wherein the signal shaping circuit comprises a rising edge detection module, a falling edge detection module, a constant zero level detection module, a constant high level detection module and a basic RS trigger module. The method comprises the steps that original signals are filtered by a signal filtering circuit and are simultaneously sent to a rising edge detection module, a falling edge detection module, a constant zero level detection module and a constant high level detection module; after being detected and processed by the constant zero level detection module and the falling edge detection module, the signal is sent to an AND gate circuit and a reset end of a basic RS trigger module; after being detected and processed by the normal high level detection module and the rising edge detection module, the signal is sent to an AND gate circuit and a setting end of a basic RS trigger module; and the output is output through the output end of the basic RS trigger module. The invention has the advantages of filtering high-frequency noise with extremely small delay, shaping and removing discontinuous high and low level phenomena caused by signal distortion.)

1. The digital circuit input pin anti-noise circuit is characterized by comprising a signal filter circuit and a signal shaping circuit, wherein the signal shaping circuit comprises a rising edge detection module, a falling edge detection module, a constant zero level detection module, a constant high level detection module and a basic RS trigger module;

the original signal is filtered by a signal filter circuit and is connected with a rising edge detection module, a falling edge detection module, a constant zero level detection module and a constant high level detection module, wherein the constant zero level detection module and the falling edge detection module are sequentially connected with an AND gate circuit and a reset end of a basic RS trigger module; the normally high level detection module and the rising edge detection module are sequentially connected with an AND gate circuit and a setting end of a basic RS trigger module; the output end of the basic RS trigger module outputs a processed signal;

the signal filtering circuit comprises a basic RS trigger structure, a basic NAND gate structure, a basic NOR gate structure and a plurality of delay structures; the input signal is input to more than two series delay links in sequence, the input signal and the signal respectively output from each delay link are output to the same NAND gate and the same OR gate, then output to the reset end of the basic RS trigger from the NAND gate, and output to the position end of the basic RS trigger from the OR gate.

2. The digital circuit input pin noise immune circuit according to claim 1, characterized in that, the rising edge detection module comprises a basic OR structure and a basic delay structure, the input signal is sequentially input to more than two series delay links, the input signal after reverse processing and the signal respectively output from each delay link are output to the same OR structure, and then output after being processed by the OR structure.

3. The digital circuit input pin noise immune circuit according to claim 1, characterized in that, said falling edge detection module comprises basic NAND structure, basic delay structure, the input signal is input to more than two series delay links in turn, the input signal after reverse processing and the signal respectively output from each delay link are output to the same NAND structure, and then output after being processed by the NAND structure.

4. The digital circuit input pin noise immune circuit according to claim 1, characterized in that, the constant zero level detection module comprises a basic OR structure and a basic delay structure, the input signal is sequentially input to more than two series delay links, the input signal and the signal respectively output from each delay link are output to the same OR structure, and then output after being processed by the OR structure.

5. The digital circuit input pin noise immune circuit according to claim 1, characterized in that, said very high level detection module comprises basic nand architecture and basic delay architecture, the input signal is input to more than two series delay links in turn, the input signal and the signal output from each delay link are output to the same nand architecture, and then output after being processed by the nand architecture.

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to an anti-noise circuit for an input pin of a digital circuit.

Background

Along with the development of electronic technology in recent years, the speed of signal communication between chips is multiplied along with the upgrading of the technology, in order to meet the communication speed of high bandwidth, signals with steeper edges have to be adopted for communication, so that more interference such as high-frequency noise, crosstalk, ringing and the like is brought to the communication line in the system, and particularly in the communication based on the shared bus backplane, the quality of the signals is difficult to guarantee due to the large number of nodes on the bus and the long communication line.

Therefore, the anti-interference capability of the chip pins is particularly important, especially for the input pins of the digital chip, if the input pins are not processed any way, wrong data can be received, which causes a safety hazard, and only simple filtering is performed on the input signals, if the filtering time constant is too small, signal distortion caused by reflection of a long transmission line cannot be filtered, and if the filtering time constant is too large, too long signal delay is caused, and the signals can be distorted or disappeared, so that when the signal distortion time is close to a signal half cycle, the filtering method can be disabled.

Disclosure of Invention

The invention aims to solve the problems and provides an anti-noise circuit for an input pin of a digital circuit, which can filter high-frequency noise with extremely small delay, shape and remove discontinuous high and low level phenomena caused by signal distortion.

In order to achieve the purpose, the invention provides the following technical scheme:

a digital circuit input pin anti-noise circuit comprises a signal filter circuit and a signal shaping circuit, wherein the signal shaping circuit comprises a rising edge detection module, a falling edge detection module, a constant zero level detection module, a constant high level detection module and a basic RS trigger module.

The original signal is filtered by a signal filter circuit and is connected with a rising edge detection module, a falling edge detection module, a constant zero level detection module and a constant high level detection module, wherein the constant zero level detection module and the falling edge detection module are sequentially connected with an AND gate circuit and a reset end of a basic RS trigger module; the normally high level detection module and the rising edge detection module are sequentially connected with an AND gate circuit and a setting end of a basic RS trigger module; the output end of the basic RS trigger module outputs a processed signal;

the method comprises the steps that an original signal is filtered by a signal filtering circuit and is simultaneously sent to a rising edge detection module, a falling edge detection module, a constant zero level detection module and a constant high level detection module of a signal shaping circuit;

after being detected and processed by the constant zero level detection module and the falling edge detection module, the signal is sent to an AND gate circuit and then sent to a reset end of the basic RS trigger module;

after being detected and processed by the normal high level detection module and the rising edge detection module, the signal is sent to an AND gate circuit and then sent to a setting end of the basic RS trigger module;

and finally, outputting the data through the output end of the basic RS trigger module.

The input and output ends of two NAND gates G1 and G2 are cross-connected to form the basic RS flip-flop.

The signal filtering circuit comprises a basic RS trigger structure, a basic NAND gate structure, a basic NOT gate structure and a plurality of delay structures. The input signal is input to more than two series delay links in sequence, the input signal and the signal respectively output from each delay link are output to the same NAND gate and the same OR gate, and then output to the reset end of the standard RS trigger from the NAND gate, and simultaneously output to the position end of the standard RS trigger from the OR gate.

The rising edge detection module comprises a basic OR structure and a basic delay structure, wherein input signals are sequentially input to more than two series delay links, the input signals subjected to reverse processing and signals respectively output from each delay link are output to the same OR structure, and then the signals are output after being processed by the OR structure.

The falling edge detection module comprises a basic NAND structure and a basic delay structure, wherein input signals are sequentially input to more than two series delay links, the input signals subjected to reverse processing and signals respectively output from each delay link are output to the same NAND structure, and then the input signals are output after being processed by the NAND structure.

The constant zero level detection module comprises a basic OR structure and a basic delay structure, wherein an input signal is sequentially input to more than two series delay links, the input signal and a signal respectively output from each delay link are output to the same OR structure, and then the signals are output after being processed by the OR structure.

The very high level detection module comprises a basic NAND structure and a basic delay structure, wherein an input signal is sequentially input to more than two series delay links, the input signal and a signal respectively output from each delay link are output to the same NAND structure, and then the input signal and the signal are output after being processed by the NAND structure.

Compared with the prior art, the invention has the beneficial effects that:

the technical scheme adopted by the invention is that the digital circuit input pin anti-noise circuit comprises a signal filtering circuit and a signal shaping circuit, wherein the signal shaping circuit comprises a rising edge detection module, a falling edge detection module, a constant zero level detection module, a constant high level detection module and a basic RS trigger module. The circuit can filter high-frequency noise with very small delay, and can shape and remove discontinuous high and low level phenomena caused by the signal distortion caused by the repeated oscillation of a long transmission line.

Drawings

In order to more clearly illustrate the technical solution of the embodiment of the present invention, the drawings needed to be used in the description of the embodiment will be briefly introduced below, it is obvious that the drawings in the following description are only for more clearly illustrating the embodiment of the present invention or the technical solution in the prior art, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a general block diagram of the anti-noise circuit of the present invention;

FIG. 2 is a circuit diagram of a signal filter according to the present invention;

FIG. 3 is a circuit diagram of a constant zero detection module according to the present invention;

FIG. 4 is a circuit diagram of a normally high detection module of the present invention;

FIG. 5 is a circuit diagram of a rising edge detection module according to the present invention;

fig. 6 is a circuit diagram of a falling edge detection module of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood and implemented by those skilled in the art, the present invention is further described with reference to the following specific examples, which are provided for illustration only and are not intended to limit the present invention.

The digital circuit input pin anti-noise circuit shown in fig. 1-6 comprises a signal filtering circuit and a signal shaping circuit, wherein the signal shaping circuit comprises a rising edge detection module, a falling edge detection module, a constant zero level detection module, a constant high level detection module and a basic RS trigger module.

The method comprises the steps that an original signal is filtered by a signal filtering circuit and is simultaneously sent to a rising edge detection module, a falling edge detection module, a constant zero level detection module and a constant high level detection module of a signal shaping circuit;

after being detected and processed by the constant zero level detection module and the falling edge detection module, the signal is sent to an AND gate circuit and then sent to a reset end of the basic RS trigger module;

after being detected and processed by the normal high level detection module and the rising edge detection module, the signal is sent to an AND gate circuit and then sent to a setting end of the basic RS trigger module;

and finally, outputting the data through the output end of the basic RS trigger module.

Referring to fig. 2, the signal filtering circuit includes a basic RS flip-flop structure, a basic nand gate structure, a basic or gate structure, and several delay structures. The input signal is input to more than two series delay links in sequence, the input signal and the signal respectively output from each delay link are output to the same NAND gate and the same OR gate, and then output to the reset end of the standard RS trigger from the NAND gate, and simultaneously output to the position end of the standard RS trigger from the OR gate.

The number N of the filter circuit delay links and the delay time T of each stage can be set according to specific conditions. The maximum width of the "glitch" that the filter circuit can filter is N times T time, and a signal exceeding the time will normally pass through the filter. The filtering circuit causes a delay in the transmission of the signal, which is N times T.

The rising edge detection module is shown in fig. 5 and comprises a basic OR structure and a basic delay structure, wherein input signals are sequentially input into more than two series delay links, the input signals subjected to reverse processing and signals respectively output from each delay link are output to the same OR structure, and then the signals are output after being processed by the OR structure.

The number N of the module delay links and the delay time T of each level can be set according to specific conditions. The greater the number N of delay elements and the longer the delay time T of each stage, the lower the level of the input signal must have been for N-1 times T before the rising edge, otherwise the rising edge will not be recognized.

The falling edge detection module is as shown in FIG. 6: the input signal is input to more than two serial delay links in sequence, the input signal after reverse processing and the signal respectively output from each delay link are output to the same NAND structure, and then the input signal is output after being processed by the NAND structure.

The number N of the module delay links and the delay time T of each level can be set according to specific conditions. The greater the number N of delay elements and the longer the delay time T of each stage, the higher the level of the input signal must have a duration of N-1 times T before the falling edge, otherwise the falling edge will not be recognized.

The constant zero level detection module is shown in fig. 3 and comprises a basic or structure and a basic delay structure, wherein an input signal is sequentially input into more than two series delay links, the input signal and a signal respectively output from each delay link are output to the same or structure, and then the output signal is output after the or structure processing.

The number N of the module delay links and the delay time T of each level can be set according to specific conditions. The larger the number N of delay elements and the longer the delay time T of each stage, the longer the time required for the normal zero detection, and the lower level less than this time (N times T time) will not be considered as the normal zero level.

The very high level detection module is shown in fig. 4 and comprises a basic nand structure and a basic delay structure, wherein an input signal is sequentially input to more than two series delay links, the input signal and a signal respectively output from each delay link are output to the same nand structure, and then the input signal and the signal are output after being processed by the nand structure.

The number N of the module delay links and the delay time T of each level can be set according to specific conditions. The larger the number N of delay elements and the longer the delay time T of each stage, the longer the time required for normally high detection, and the high level less than this time (N times T time) will not be considered as normally high.

Basic RS flip-flop module: two NAND structures are included, wherein the output of one NAND structure is connected to the input of the other NAND structure, and the other input of the two NAND structures is the set terminal and the reset terminal of the basic RS flip-flop module respectively.

The invention can filter high-frequency noise with very small delay, and can reshape and remove the received discontinuous high-low level phenomenon caused by the signal distortion caused by the repeated oscillation of the long transmission line, thereby overcoming the defects of the prior art.

The details of the present invention not described in detail are prior art.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.