阅读说明：本技术 包括非易失性存储器件的半导体存储器模块 (Semiconductor memory module including nonvolatile memory device ) 是由 崔桢焕 李泰成 于 2019-07-24 设计创作，主要内容包括：本公开涉及包括非易失性存储器件的半导体存储器模块。该半导体存储器模块包括：数据缓冲器,所述数据缓冲器与外部设备交换第一数据信号；非易失性存储器件,所述非易失性存储器件分别通过数据线连接到所述数据缓冲器；以及控制器,所述控制器连接到所述数据线。所述控制器从所述外部设备接收地址、命令和控制信号,并且根据所述地址、所述命令和所述控制信号,所述控制器通过第一控制线控制所述数据缓冲器并且通过第二控制线控制所述非易失性存储器件。(The present disclosure relates to a semiconductor memory module including a nonvolatile memory device. The semiconductor memory module includes: a data buffer exchanging a first data signal with an external device; nonvolatile memory devices connected to the data buffers through data lines, respectively; and a controller connected to the data line. The controller receives an address, a command, and a control signal from the external device, and controls the data buffer through a first control line and the nonvolatile memory device through a second control line according to the address, the command, and the control signal.)

1. A semiconductor memory module, comprising:

a data buffer configured to exchange a first data signal with an external device external to the semiconductor memory module;

a nonvolatile memory device connected to the data buffer through a data line; and

an internal memory module controller connected to the data line,

wherein the internal memory module controller is further configured to:

receiving address, command and control signals from the external device; and is

Controlling the data buffer by a first control line and controlling the nonvolatile memory device by a second control line according to the address, the command, and the control signal.

2. The semiconductor memory module according to claim 1, wherein, in accordance with the command and the control signal, the internal memory module controller selects one of the following states: a first state to receive a second data signal from the data line, a second state to transmit a third data signal to the data line, and a third state to ignore a fourth data signal transmitted through the data line.

3. The semiconductor memory module of claim 1, wherein the data buffer has a first state to receive a second data signal from the data line, a second state to transmit a third data signal to the data line, and a third state to ignore a fourth data signal transmitted through the data line under the control of the internal memory module controller.

4. The semiconductor memory module of claim 1, wherein the nonvolatile memory device has a first state of receiving a second data signal from the data line, a second state of transmitting a third data signal to the data line, and a third state of ignoring a fourth data signal transmitted through the data line under the control of the internal memory module controller.

5. The semiconductor memory module according to claim 1, wherein in a case where the internal memory module controller receives the address, the command, or the control signal from the external device when the internal memory module controller communicates with the nonvolatile memory device through the data line or is to communicate with the nonvolatile memory device through the data line, the internal memory module controller stops or cancels communication with the nonvolatile memory device.

6. The semiconductor memory module according to claim 1, wherein the internal memory module controller includes an interface circuit connected to the data line, and

wherein the internal memory module controller is further configured to communicate with the data buffer and with the non-volatile storage device in common using the interface circuit.

7. The semiconductor memory module of claim 1,

the internal memory module controller includes a buffer memory, and

wherein the internal memory module controller is further configured to:

storing a second data signal received from the data buffer or the nonvolatile memory device through the data line into the buffer memory; and

transmitting the second data signal stored in the buffer memory as a third data signal to the nonvolatile memory device or the data buffer through the data line.

8. The semiconductor memory module according to claim 7, wherein the second data signal to be sent from the data buffer to the nonvolatile memory device through the data line and the third data signal to be sent from the nonvolatile memory device to the data buffer through the data line bypass the buffer memory of the internal memory module controller depending on the command and the control signal.

9. The semiconductor memory module of claim 7, wherein the internal memory module controller is further configured to: discarding the fourth data signal previously stored in the buffer memory when the free storage capacity of the buffer memory is less than a threshold.

10. The semiconductor memory module of claim 1, wherein the control signal comprises a first control signal, and

wherein the internal memory module controller is further configured such that:

when the first control signal is in an active state, the internal memory module controller controls the nonvolatile memory device such that the nonvolatile memory device ignores the second data signal transmitted through the data line and the internal memory module controller receives or transmits the second data signal through the data line.

11. The semiconductor memory module of claim 10, wherein the control signal further comprises a second control signal, and

wherein the internal memory module controller is further configured such that:

when the first control signal is in an active state and the second control signal is in an active state, the internal memory module controller controls the nonvolatile memory device such that the nonvolatile memory device exchanges a fourth data signal with the data line and the internal memory module controller ignores the fourth data signal transmitted through the data line.

12. The semiconductor memory module according to claim 10, wherein the internal memory module controller is further configured to deactivate the data buffer and exchange a fourth data signal with the nonvolatile memory device through the data line when the first control signal is in a deactivated state.

13. The semiconductor memory module of claim 1, wherein the control signal comprises a first control signal and a second control signal, and

wherein the internal memory module controller is further configured to receive a second data signal from the data buffer through the data line or transmit a third data signal to the data buffer through the data line when one of the first control signal and the second control signal is in an active state.

14. The semiconductor memory module of claim 13, wherein the control signal further comprises a third control signal, and

wherein the internal memory module controller is further configured to control a first one of the non-volatile memory devices such that the first non-volatile memory device exchanges a fourth data signal with the data line, control a second one of the non-volatile memory devices such that the second non-volatile memory device ignores the fourth data signal sent through the data line, and ignore the fourth data signal sent through the data line, based on the first control signal being in an active state and the third control signal being in an active state.

15. The semiconductor memory module of claim 13, wherein the internal memory module controller is further configured to deactivate the data buffer and exchange a fourth data signal with the first non-volatile memory device or the second non-volatile memory device through the data line based on the first control signal and the second control signal being in a deactivated state.

16. A semiconductor memory module, comprising:

a data buffer configured to exchange data signals with an external device external to the semiconductor memory module;

a first nonvolatile memory device connected to the data buffer through a data line;

a second nonvolatile memory device connected to the data buffer through the data line; and

a controller connected to the data line,

wherein the controller is configured to receive an address, a command and a control signal from the external device, and

wherein, depending on the address, the command, and the control signal, the first non-volatile memory device is configured to communicate with the controller and the data buffer through the data lines, and the second non-volatile memory device is configured to communicate directly with the data buffer through the data lines.

17. The semiconductor memory module of claim 16, wherein the controller includes an error correction block, and

wherein the controller is further configured to:

performing error correction coding on data to be written to the first nonvolatile memory device through the data lines; and

performing error correction decoding on the data read from the first nonvolatile memory device through the data line.

18. A semiconductor memory module, comprising:

a data buffer configured to exchange data signals with an external device external to the semiconductor memory module;

a nonvolatile memory device connected to the data buffer through a data line; and

a controller connected to the data line,

wherein the data line includes:

a first wire extending from a side of the controller;

a second line extending from the first line toward the data buffer; and

a third line extending from the first line toward the nonvolatile memory device,

wherein the controller is further configured to:

receiving address, command and control signals from the external device; and is

Controlling the data buffer by a first control line and controlling the nonvolatile memory device by a second control line according to the address, the command, and the control signal.

19. The semiconductor memory module according to claim 18, wherein the first lines have the same length as each other regardless of a position of the first line connected to the first node of the second line or a position of the first line connected to the second node of the third line.

20. The semiconductor memory module according to claim 18, wherein one of the first lines is connected to a first one of the nonvolatile memory devices farthest from the controller and to a first one of the data buffers closest to the controller, and

wherein another one of the first lines is connected to a second nonvolatile memory device, which is closest to the controller, among the nonvolatile memory devices and to a second data buffer, which is farthest from the controller, among the data buffers.

Technical Field

Embodiments of the inventive concepts disclosed herein relate to semiconductor devices, and more particularly, to semiconductor memory modules including nonvolatile memory devices.

Background

The computing system includes a processor, a main memory, and a secondary memory. The secondary memory may store data for an operating system, applications, or data generated by an operating system or applications installed on the computing system. The secondary memory includes a hard disk drive, solid state disk, etc., and is accessed by the processor over a particular bus, such as a peripheral component interconnect express (PCIe) bus.

The main memory is used for temporarily storing data used by the processor among data stored in the secondary memory. Typically, the main memory includes memory that supports high-speed random access, such as Synchronous Dynamic Random Access Memory (SDRAM). Main memory is manufactured to operate in compliance with standards such as dual in-line memory modules (DIMMs), registered DIMMs (rdimms), and low-load DIMMs (lrdimms).

A main memory manufactured in conformity with the standard is implemented in such a manner that a semiconductor memory package is attached to a printed circuit board. Main memory manufactured in compliance with the standard is implemented as attached to or easily removable from a computing system. For this reason, the main memory is referred to as a "semiconductor memory module".

Today, main memories have been developed: which has a large storage capacity with a relatively low cost compared to SDRAM, has an operation speed close to that of SDRAM, and stores data in a nonvolatile manner. Such a main memory includes a nonvolatile memory device such as a phase change ram (pram), a resistance ram (rram), a magnetic ram (mram), a ferroelectric ram (fram), or a flash memory, and is called a "storage class memory" (SCM).

Existing computing systems have been manufactured using main memory manufactured according to standards such as DIMMs, RDIMMs, and LRDIMMs. Thus, memory level memory is being developed to conform to standards such as DIMMs, RDIMMs, and LRDIMMs in order to apply memory level memory to existing computing systems without additional cost.

However, the standard of the existing main memory is decided in consideration of the operation characteristics of the SDRAM and is not consistent with the operation characteristics of the nonvolatile memory device. Therefore, there is a need for a semiconductor memory module that conforms to the standard of a main memory while including a nonvolatile memory device.

Disclosure of Invention

Embodiments of the inventive concept provide a semiconductor memory module having reduced cost and reduced noise while conforming to the standards of a main memory.

According to one exemplary embodiment, a semiconductor memory module includes: a data buffer exchanging a first data signal with an external device external to the semiconductor memory module; nonvolatile memory devices connected to the data buffers through data lines, respectively; and an internal memory module controller connected to the data line. The controller receiving address, command and control signals from the external device; and the controller controls the data buffer through a first control line and controls the nonvolatile memory device through a second control line according to the address, the command, and the control signal.

According to an exemplary embodiment that may include the above embodiments, a semiconductor memory module includes: a data buffer exchanging data signals with an external device external to the semiconductor memory module; first nonvolatile memory devices connected to the data buffers through data lines, respectively; second nonvolatile memory devices connected to the data buffers through the data lines, respectively; and a controller connected to the data line. The controller receives an address, a command, and a control signal from the external device, and the first nonvolatile memory device communicates with the controller and the data buffer through the data line and the second nonvolatile memory device directly communicates with the data buffer through the data line according to the address, the command, and the control signal.

According to an exemplary embodiment that may include the above embodiments, a semiconductor memory module includes: a data buffer exchanging data signals with an external device external to the semiconductor memory module; nonvolatile memory devices connected to the data buffers through data lines, respectively; and a controller connected to the data line. The data lines include a first line extending from a side of the controller, a second line extending from the first line toward the data buffer, and a third line extending from the first line toward the nonvolatile memory device. The controller receives an address, a command, and a control signal from the external device, and controls the data buffer through a first control line and the nonvolatile memory device through a second control line according to the address, the command, and the control signal.

Drawings

The above and other objects and features of the present inventive concept will become apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a block diagram illustrating a semiconductor memory module according to a first embodiment of the inventive concept.

Fig. 2 is a flowchart illustrating an operation method of a semiconductor memory module according to some embodiments of the inventive concept.

Fig. 3 is a diagram illustrating an example of adjusting an external selection signal and an internal selection signal.

Fig. 4 is a flowchart illustrating an example of writing data from the memory controller to the first to ninth nonvolatile memory devices by the controller.

Fig. 5 is a diagram illustrating an example of transmitting a data signal from a memory controller to a controller.

Fig. 6 is a diagram illustrating an example of further transmission of the data signal from the memory controller to the controller after fig. 5.

Fig. 7 is a diagram illustrating an example in which the controller writes data stored in the buffer to the first nonvolatile memory device when the flush condition is satisfied after fig. 6.

Fig. 8 is a flowchart illustrating an example of the memory controller reading data from the semiconductor memory module.

Fig. 9 is a diagram illustrating an example in which the memory controller reads the data signals stored in the buffer after fig. 7.

Fig. 10 is a diagram illustrating an example in which the memory controller reads a data signal not stored in the buffer after fig. 9.

Fig. 11 is a flowchart illustrating an example of a controller managing a buffer.

Fig. 12 is a flowchart illustrating an example in which the controller arbitrates communication through the first to ninth data lines.

Fig. 13 is a diagram illustrating an example in which a memory controller directly accesses a first nonvolatile memory device through a first data line.

Fig. 14 is a block diagram illustrating a semiconductor memory module according to a second embodiment of the inventive concept.

Fig. 15 is a block diagram illustrating a semiconductor memory module according to a third embodiment of the inventive concept.

Fig. 16 is a block diagram illustrating a semiconductor memory module according to a fourth embodiment of the inventive concept.

Fig. 17 and 18 are diagrams illustrating examples of adjusting an external selection signal and an internal selection signal.

Fig. 19 is a block diagram illustrating a semiconductor memory module according to a fifth embodiment of the inventive concept.

Detailed Description

Fig. 1 is a block diagram illustrating a semiconductor memory module 100 according to a first embodiment of the inventive concept. Referring to fig. 1, a semiconductor memory module 100 includes a controller 110, nonvolatile memory devices (NVMs) 121 to 129, and Data Buffers (DBs) 131 to 139. The controller 110, the nonvolatile memory devices 121 to 129, and the data buffers 131 to 139 may be implemented by different semiconductor packages, and the semiconductor packages may be mounted on the printed circuit board 101 to form the memory module 100. Each semiconductor package may include one or more semiconductor chips mounted on a package substrate and covered with a molding layer.

The controller 110 may receive an external address ADDRe, an external command CMDe, an external clock signal CKe, and an external select signal Se from the external memory controller 10. The external address ADDRe may be received in the form of an address signal set, and the external command CMDe may be received in the form of a command signal set. The signals received by the controller 110 from the memory controller 10 are not limited to the above signals. The controller 110 may receive various signals (e.g., control signals) from the memory controller 10. Memory controller 10 may be external to memory module 100, e.g., as part of a host device, and not mounted on printed circuit board 101. The controller 110 may be included within the memory module 100 as part of the memory module 100 and thus may be referred to herein as an internal memory module controller (as opposed to an external memory controller such as the memory controller 10) internal to the memory module 100.

The controller 110 may be connected to the first through ninth nonvolatile memory devices 121 through 129 and the first through ninth data buffers 131 through 139 through first through ninth data lines 141 through 149. For example, each of the first to ninth data lines 141 to 149 may include two or more (e.g., 8) lines transmitting the internal data signals DQi and at least one (e.g., 2) line transmitting the internal data strobe signal DQSi. Accordingly, each of the first to ninth data lines 141 to 149 may be referred to as a data line group in some cases.

The controller 110 may receive the internal data signals DQi and the internal data strobe signals DQSi from the first to ninth nonvolatile memory devices 121 to 129 or the first to ninth data buffers 131 to 139 through the first to ninth data lines 141 to 149. The controller 110 may latch the level of the internal data signal DQi in synchronization with the transition timing of the internal data strobe signal DQSi.

The controller 110 may transmit the internal data signal DQi and the internal data strobe signal DQSi to the first to ninth nonvolatile memory devices 121 to 129 or the first to ninth data buffers 131 to 139 through the first to ninth data lines 141 to 149. The controller 110 may generate the internal data strobe signal DQSi from the external clock signal CKe, and may adjust the level of the internal data signal DQi in synchronization with the conversion timing of the internal data strobe signal DQSi.

The controller 110 may collectively transmit the internal address ADDRi, the internal command CMDi, the internal clock signal CKi, and the internal select signal Si to the first through ninth nonvolatile memory devices 121 through 129 through the first control lines 151 and 152 in response to the external address ADDRe, the external command CMDe, the external clock signal CKe, and the external select signal Se. The internal address ADDRi may be transmitted in the form of an address signal set, and the internal command CMDi may be transmitted in the form of a command signal set. It will be noted that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions and/or sections, these elements, components, regions and/or sections should not be limited by these terms. Unless the context indicates otherwise, these terms are only used to distinguish one element, component, region or section from another element, component, region or section, e.g., as a naming convention. Thus, a first element, component, region or section discussed in one section of the specification below could be termed a second element, component, region or section in another section of the specification or claims without departing from the teachings of the present invention. In addition, even if a term is not described in the specification using "first", "second", or the like, it may be still referred to as "first" or "second" in the claims in order to distinguish required elements from each other in some cases.

The signals transmitted by the controller 110 to the first to ninth nonvolatile memory devices 121 to 129 are not limited to the above signals. The controller 110 may transmit various signals (e.g., control signals) including the internal selection signal Si to the first through ninth nonvolatile memory devices 121 through 129. The signals sent by the controller 110 to the first through ninth nonvolatile memory devices 121 through 129 may be the same as or similar to the signals received by the controller 110 from the memory controller 10.

The controller 110 may allow the first through ninth nonvolatile memory devices 121 through 129 to receive and write the internal data signals DQi transmitted through the first through ninth data lines 141 through 149 by using the internal command CMDi and the internal selection signal Si. The controller 110 may specify the location of the memory space in which each of the first through ninth nonvolatile memory devices 121 through 129 stores the internal data signal Dqi by using the internal address ADDRi.

Further, by using the internal command CMDi and the internal selection signal Si, the controller 110 may allow the first through ninth nonvolatile memory devices 121 through 129 to read the stored data and transmit the read data as the internal data signal Dqi through the first through ninth data lines 141 through 149. The controller 110 may specify the location of a memory space in which each of the first through ninth nonvolatile memory devices 121 through 129 is to read data by using the internal address ADDRi.

The controller 110 may control the first to ninth data buffers 131 to 139 in response to an external command CMDe and an external selection signal Se. The controller 110 may transmit a common buffering command BCOM to the first to ninth data buffers 131 to 139 through the second control lines 161 and 162. The buffered command BCOM may be implemented by a combination of buffered command signals.

The first through ninth nonvolatile memory devices 121 through 129 may receive and write internal data signals DQi from the first through ninth data lines 141 through 149 in response to the internal command CMDi, the internal address ADDRi, and the internal selection signal Si. Each of the data buffers 131 in the first to ninth nonvolatile memory devices 121 to 129 may latch the level of the internal data signal DQi in synchronization with the conversion timing of the internal data strobe signal DQSi.

The first through ninth nonvolatile memory devices 121 through 129 may read data written therein in response to the internal command CMDi, the internal address ADDRi, and the internal selection signal Si, and may transmit the read data as the internal data signal DQi to the first through ninth data lines 141 through 149.

The first through ninth nonvolatile memory devices 121 through 129 may each generate the internal data strobe signal DQSi from the internal clock signal CKi, and may adjust the level of the internal data signal DQi in synchronization with the transition timing of the internal data strobe signal DQSi.

The first to ninth data buffers 131 to 139 may operate in response to the buffering command BCOM. When the buffer command BCOM indicates a read operation, the first to ninth data buffers 131 to 139 may transmit the internal data signals DQi and the internal data strobe signals DQSi, which are transmitted through the first to ninth data lines 141 to 149, to the memory controller 10 as the external data signals DQe and the external data strobe signals DQSe.

When the buffer command BCOM indicates a write operation, the first to ninth data buffers 131 to 139 may transmit the external data signal DQe and the external data strobe signal DQSe transmitted from the memory controller 10 as the internal data signal DQi and the internal data strobe signal DQSi to the first to ninth data lines 141 to 149.

As shown in fig. 1, the controller 110, the first to ninth nonvolatile memory devices 121 to 129, and the first to ninth data buffers 131 to 139 may be commonly connected to the first to ninth data lines 141 to 149.

In this case, the number of wirings required for the semiconductor memory module 100 and the complexity of the wiring arrangement can be reduced as compared with the case where the connections between the first to ninth nonvolatile memory devices 121 to 129 and the controller 110 and the connections between the first to ninth data buffers 131 to 139 and the controller 110 are realized by using different data lines. Therefore, the manufacturing cost of the semiconductor memory module 100 is reduced.

Further, compared to the case where the connections between the first to ninth nonvolatile memory devices 121 to 129 and the controller 110 and the connections between the first to ninth data buffers 131 to 139 and the controller 110 are realized by using different data lines, the distance between the wirings is increased, and thus the interference between the wirings is reduced. Thus, noise generated due to disturbance at the semiconductor memory module 100 is reduced.

The controller 110 may include a physical block (PHY)111, the physical block 111 supporting common communication with the first through ninth nonvolatile memory devices 121 through 129 and the first through ninth data buffers 131 through 139 via first through ninth data lines 141 through 149 (e.g., via the same set of switches, drivers, and other circuitry of the physical block 111). Physical block 111 may exchange internal data signals DQi and internal data strobe signals DQSi with first to ninth data lines 141 to 149.

The physical block 111 may transmit or receive the internal data signal DQi and the internal data strobe signal DQSi in the same manner when communicating with the first through ninth nonvolatile memory devices 121 through 129 and when communicating with the first through ninth data buffers 131 through 139.

The physical block 111 may receive an external address ADDRe, an external command CMDe, an external clock signal CKe, and an external select signal Se from the memory controller 10. Physical block 111 may generate an internal address ADDRi, an internal command CMDi, an internal clock signal CKi, and an internal select signal Si from an external address ADDRe, an external command CMDe, an external clock signal CKe, and an external select signal Se.

When all the memory spaces of the first through ninth nonvolatile memory devices 121 through 129 are configured to be accessed by the memory controller 10, the physical block 111 may directly output the external address ADDRe as the internal address ADDRi through the first control lines 151 and 152.

When some memory spaces of the first to ninth nonvolatile memory devices 121 to 129 are accessed by the memory controller 10 and the remaining memory spaces are used as meta areas of the semiconductor memory module 100, the physical block 111 may convert an external address ADDRe into an internal address ADDRi and may output the internal address ADDRi through the first control lines 151 and 152.

Physical block 111 can directly transmit external command CMDe transmitted from memory controller 10 as internal command CMDi through first control lines 151 and 152. The physical block 111 may directly transmit the external clock signal CKe as the internal clock signal Cki through the first control lines 151 and 152.

The physical block 111 may directly transmit the external selection signal Se as the internal selection signal Si through the first control lines 151 and 152, or may convert the external selection signal Se into the internal selection signal Si and may transmit the internal selection signal Si through the first control lines 151 and 152. The physical block 111 may send the buffering command BCOM to the first to ninth data buffers 131 to 139 through the second control lines 161 and 162. Physical block 111 may include an interface (e.g., interface circuitry) for controller 110, and may include, for example, various switches and drivers for routing communications between memory controller 10, controller 110, nonvolatile memory devices 121 through 129, and data buffers 131 and 139.

Since the controller 110, the first to ninth nonvolatile memory devices 121 to 129, and the first to ninth data buffers 131 to 139 commonly use the first to ninth data lines 141 to 149, arbitration is required as to whether any of the first entity (e.g., the controller 110), the second entity (e.g., the first to ninth nonvolatile memory devices 121 to 129), and the third entity (e.g., the first to ninth data buffers 131 to 139) performs communication.

For example, if the third entity performs communication while the first entity and the second entity perform communication, a collision may occur. The controller 110 may perform arbitration to prevent conflicts from occurring. When performing arbitration, the timing at which the physical block 111 receives the external address ADDRi, the external command CMDe, the external clock signal CKe, and the external select signal Se from the memory controller 10 may be different from the timing at which the physical block 111 transmits the internal address ADDRi, the internal command CMDi, the internal clock signal CKi, and the internal select signal Si to the first through ninth nonvolatile memory devices 121 through 129.

In the case where the controller 110 uses different wirings in communication with the first to ninth nonvolatile memory devices 121 to 129 and in communication with the first to ninth data buffers 131 to 139, different physical blocks corresponding to the different wirings may be required. As illustrated in fig. 1, in the case where one physical block 111 is provided in the controller 110, the complexity and manufacturing cost of the controller 110 are reduced. Thus, the complexity and manufacturing cost of the semiconductor memory module 100 is reduced.

The controller 110 may also include a buffer 112. The controller 110 may store the internal data signals DQi transmitted from the first to ninth nonvolatile memory devices 121 to 129 in the buffer 112. The controller 110 may read data stored in the buffer 112 and may transmit the read data to the first to ninth data buffers 131 to 139 as the internal data signal DQi.

Similarly, the controller 110 may store the internal data signals DQi transmitted from the first to ninth data buffers 131 to 139 in the buffer 112. The controller 110 may read the data stored in the buffer 112 and may transmit the read data as the internal data signal DQi to the first through ninth nonvolatile memory devices 121 through 129.

The controller 110 may store information on the external address ADDRe, the external command CMDe, and the external selection signal Se received from the memory controller 10 in the buffer 112. The controller 110 may generate an internal address ADDRi, an internal command CMDi, and an internal selection signal Si based on information stored in the buffer 112.

Fig. 2 is a flowchart illustrating an operation method of the semiconductor memory module 100 according to an embodiment of the inventive concept. Referring to fig. 1 and 2, in operation S110, the controller 110 may receive internal data signals DQi from an external device (e.g., the memory controller 10) through the first to ninth data buffers 131 to 139 and the common first to ninth data lines 141 to 149 (hereinafter, referred to as "common data lines").

In operation S120, the controller 110 may transmit the internal data signals DQi to the first to ninth nonvolatile memory devices 121 to 129 through the common data lines 141 to 149.

In operation S130, the controller 110 may receive the internal data signals DQi from the first to ninth nonvolatile memory devices 121 to 129 through the common data lines 141 to 149.

In operation S140, the controller 110 may transmit the internal data signal DQi to an external device (e.g., the memory controller 10) through the common data lines 141 to 149 and the first to ninth data buffers 131 to 139.

Fig. 3 is a diagram illustrating an example of adjusting the external selection signal Se and the internal selection signal Si. Referring to fig. 1 and 3, the external selection signal Se may include a first external selection signal Se1 and a second external selection signal Se 2. The first external selection signal Se1 may be activated (e.g., to a low level) by the memory controller 10 to cause the memory controller 10 or set the memory controller 10 to access the first through ninth nonvolatile memory devices 121 through 129 through the controller 110.

The second external selection signal Se2 may be activated (e.g., to a low level) by the memory controller 10 to cause the memory controller 10 or set the memory controller 10 to access the first through ninth nonvolatile memory devices 121-129 without passing through the controller 110 (e.g., bypassing the controller 110).

The internal select signal Si may include a first internal select signal Si1 and a second internal select signal Si 2. The first internal selection signal Si1 may be activated (e.g., to a low level) by the controller 110 to cause the controller 110 or set the controller 110 to access the first through ninth nonvolatile memory devices 121 through 129.

The second internal selection signal Si2 may be activated (e.g., to a low level) by the controller 110 to cause the controller 110 or set the controller 110 to restrict communication with the first through ninth nonvolatile memory devices 121 through 129. In one embodiment, the second internal selection signal Si2 may be omitted. Communication with the first through ninth nonvolatile memory devices 121 through 129 may be restricted by deactivating (deactivating) the first internal selection signal Si1 (e.g., to a high level) instead of by the second internal selection signal Si 2.

In the first portion or the first period, the memory controller 10 and the controller 110 may communicate with each other through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149. For example, communication between the memory controller 10 and the controller 110 may be established to allow the memory controller 10 to write data to or read data from the first through ninth nonvolatile memory devices 121 through 129 through the controller 110.

In an example of a write operation, the memory controller 10 may transmit an external address ADDRe and an external command CMDe indicating the write operation to the controller 110. Further, the memory controller 10 may activate the first external selection signal Se1 for providing a notification that the first to ninth nonvolatile memory devices 121 to 129 are targets of write operations. The memory controller 10 may deactivate the second external selection signal Se2 for providing notification of the write operation performed by the controller 110.

When the external command CMDe indicates a write operation, the controller 110 may transmit a write command WR as a buffer command BCOM to the first to ninth data buffers 131 to 139. The controller 110 may receive write data from the memory controller 10 through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149 in the form of internal data signals DQi.

To prevent the first to ninth nonvolatile memory devices 121 to 129 from colliding at the first to ninth data lines 141 to 149, the controller 110 may deactivate the first internal selection signal Si1 and may activate the second internal selection signal Si 2. In an example of a read operation, the memory controller 10 may transmit an external address ADDRe and an external command CMDe indicating the read operation to the controller 110. The memory controller 10 may activate the first external selection signal Se1 and may deactivate the second external selection signal Se 2.

When the external command CMDe indicates a read operation, the controller 110 may transmit the read command RD as a buffer command BCOM to the first to ninth data buffers 131 to 139. In one embodiment, the data requested by memory controller 10 may already be stored in buffer 112 of controller 110.

The controller 110 may transmit the requested data to the memory controller 10 through the first to ninth data lines 141 to 149 and the first to ninth data buffers 131 to 139 in the form of the internal data signals DQi. To prevent collisions, the controller 110 may deactivate the first internal select signal Si1 and may activate the second internal select signal Si 2.

In the first section, the first to ninth data buffers 131 to 139 may exchange the internal data signals DQi with the controller 110 through the first to ninth data lines 141 to 149. The first to ninth nonvolatile memory devices 121 to 129 may ignore the internal data signals DQi transmitted through the first to ninth data lines 141 to 149 (e.g., based on the first and second internal selection signals Si1 and Si2 in response to the first and second external selection signals Se1 and Se2) and may not transmit any signal to the first to ninth data lines 141 to 149.

In the second portion or period, the controller 110 and the first to ninth nonvolatile memory devices 121 to 129 may communicate with each other through the first to ninth data lines 141 to 149.

For example, communication may be performed between the controller 110 and the first to ninth nonvolatile memory devices 121 to 129 when data stored in the buffer 112 is written to the first to ninth nonvolatile memory devices 121 to 129 by the memory controller 10 or when data requested by the memory controller 10 is read from the first to ninth nonvolatile memory devices 121 to 129.

The second part is associated with communication performed within the semiconductor memory module 100 and is not associated with the memory controller 10. Accordingly, the first and second external selection signals Se1 and Se2 may be in a deactivated state (e.g., high level). The controller 110 may transmit the internal address ADDRi and the internal command CMDi indicating a read or write operation to the first through ninth nonvolatile memory devices 121 through 129.

To provide notification that the first to ninth nonvolatile memory devices 121 to 129 are communication targets, the controller 110 may activate the first internal selection signal Si1 (to a low level) and may deactivate the second internal selection signal Si2 (to a high level). Since the first to ninth data buffers 131 to 139 are not associated with the second portion, the controller 110 may not send the buffering command BCOM.

The controller 110 may transmit data to or receive data from the first to ninth nonvolatile memory devices 121 to 129 through the first to ninth data lines 141 to 149 in the form of internal data signals DQi.

In the second section, the first to ninth nonvolatile memory devices 121 to 129 may exchange internal data signals DQi with the controller 110 through the first to ninth data lines 141 to 149. The first to ninth data buffers 131 to 139 may ignore (e.g., based on the buffering command BCOM in response to the first to ninth external selection signals Se1 and Se2) the internal data signals DQi transmitted through the first to ninth data lines 141 to 149 and may not transmit any signal to the first to ninth data lines 141 to 149.

In the third section, the memory controller 10 and the first to ninth nonvolatile memory devices 121 to 129 may communicate with each other through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149.

For example, communication may be performed between the memory controller 10 and the first to ninth nonvolatile memory devices 121 to 129 in order to cause the memory controller 10 or the memory controller 10 to set the data to be written directly to the first to ninth nonvolatile memory devices 121 to 129, or to cause the memory controller 10 or the memory controller 10 to set the data to be read directly from the first to ninth nonvolatile memory devices 121 to 129.

The memory controller 10 may transmit an external address ADDRe and an external command CMDe indicating a write or read operation to the controller 110. The controller 110 may convert the external address ADDRe and the external command CMDe into an internal address ADDRi and an internal command CMDi and transmit the internal address ADDRi and the internal command CMDi to the first to ninth nonvolatile memory devices 121 to 129, or may transmit the external address ADDRe and the external command CMDe as the internal address ADDRi and the internal command CMDi to the first to ninth nonvolatile memory devices 121 to 129 without conversion.

Further, the memory controller 10 may activate the first external selection signal Se1 (to a low level) so as to provide notification that the first to ninth nonvolatile memory devices 121 to 129 are access targets. The memory controller 10 may activate the second external selection signal Se2 (to a low level) to provide notification that access is performed without passing through the controller 110.

According to the external command CMDe, the controller 110 may transmit a write command WR or a read command RD as a buffering command BCOM to the first to ninth data buffers 131 to 139. The first through ninth nonvolatile memory devices 121 through 129 may exchange data with the memory controller 10 through the first through ninth data lines 141 through 149 in the form of internal data signals DQi.

In order to prevent collision from occurring at the first to ninth data lines 141 to 149, the controller 110 may ignore the internal data signals DQi transmitted through the first to ninth data lines 141 to 149 (e.g., based on the first and second external selection signals Se1 and Se2) and may not transmit any signal to the first to ninth data lines 141 to 149.

In the third section, the first to ninth data buffers 131 to 139 may exchange internal data signals DQi with the first to ninth nonvolatile memory devices 121 to 129 through the first to ninth data lines 141 to 149. The controller 110 may ignore the internal data signals DQi transmitted through the first to ninth data lines 141 to 149 and may not transmit any signal to the first to ninth data lines 141 to 149.

In some embodiments, the memory controller 10 may be prohibited from directly accessing the first through ninth nonvolatile memory devices 121 through 129 without passing through the controller 110. In this case, the second external selection signal Se2 may be omitted.

Fig. 4 is a flowchart illustrating an example of writing data from the memory controller 10 to the first to ninth nonvolatile memory devices 121 to 129 by the controller 110. Referring to fig. 1 and 4, the controller 110 may receive an address ADDR, a command CMD, and a data signal DQ from the memory controller 10 in operation S210.

For example, the controller 110 receives an external address ADDRe, an external command CMDe, and an external selection signal Se from the memory controller 10. The first to ninth data buffers 131 to 139 may transmit the external data signal DQe received from the memory controller 10 to the controller 110 as the internal data signal Dqi.

In operation S220, the controller 110 stores the external address ADDRe and the external command CMDe (e.g., a write command) received from the memory controller 10 and the internal data signals DQi received through the first to ninth data buffers 131 to 139 in the buffer 112. For example, the controller 110 may store the external address ADDRe and the external command CMDe or information about the external address ADDRe and the external command CMDe in the buffer 112.

The controller 110 may complete the first operation according to the external command CMDe (write command in operation S210) of the memory controller 10 by storing the external address ADDRe, the external command CMDe, and the internal data signal DQi (operation S220). The controller 110 may perform a second operation (e.g., a flush operation) of storing the internal data signals DQi stored in the buffer 112 into the first through ninth nonvolatile memory devices 121 through 129 without intervention of the memory controller 10. For example, the controller 110 may support a write back operation.

In operation S230, the controller 110 determines whether a flush condition is satisfied. For example, when a flush command is received from the memory controller 10 as the external command CMDe, the flush condition may be satisfied. For another example, the flush condition may be satisfied when the idle time during which the memory controller 10 does not access the semiconductor memory module 100 is not less than the threshold value.

When the flush condition is not satisfied, the flush operation is not performed, and the process is terminated. When the flush condition is satisfied, operation S240 is performed. In operation S240, the controller 110 transmits the internal address ADDRi, the internal command CMDi, and the internal data signal DQi stored in the buffer 112 and the internal selection signal Si to the first through ninth nonvolatile memory devices 121 through 129.

In operation S250, the first through ninth nonvolatile memory devices 121 through 129 perform a write operation according to the internal address ADDRi, the internal command CMDi, and the internal data signal DQi from the controller 110, and the internal select signal Si. Accordingly, the data requested to be written by the memory controller 10 can be finally written in the first to ninth nonvolatile memory devices 121 to 129.

As described above, the controller 110 may refer to the flush condition to prevent communication between the memory controller 10 and the controller 110 from conflicting with communication between the controller 110 and the first to ninth nonvolatile memory devices 121 to 129.

Fig. 5 is a diagram illustrating an example of transmitting a data signal DQ from the memory controller 10 to the controller 110. In one embodiment, the remaining components except the memory controller 10, the controller 110, and the first nonvolatile memory device 121 are omitted. The second to ninth nonvolatile memory devices 122 to 129 may operate simultaneously with the first nonvolatile memory device 121. The external data signal DQe and the internal data signal DQi may be commonly referred to as the data signal DQ.

Referring to fig. 5, the memory controller 10 may transmit an external address ADDRe and an external command CMDe to the controller 110 and may control an external selection signal Se as in the first part of fig. 3 in operation S311. The external command CMDe may be a write command. In operation S312, the memory controller 10 may transmit a data signal DQ to the controller 110 through the first data line 141. The controller 110 may receive the external address ADDRe, the external command CMDe, the external selection signal Se, and the data signal DQ by using the physical block 111.

In operation S313, the controller 110 may store the external address ADDRe and the data signal DQ received from the memory controller 10 as the first data entity DQ _ ET1 to the first region 113 of the buffer 112. In operation S314, the controller 110 may store a first write pointer W _ PTR1 pointing to the first data entity DQ _ ET1 to the second region 114 of the buffer 112.

The first write pointer W _ PTR1 may include information indicating that a write operation is performed or information regarding a location of the first region 113 where the first data entity DQ _ ET1 is stored. For example, the first write pointer W _ PTR1 may serve as a dirty flag (dirty flag) indicating that any data entity stored in the first area 113 may be written to the first through ninth non-volatile storage devices 121 through 129.

Fig. 6 is a diagram illustrating an example of further transmission of the data signal DQ from the memory controller 10 to the controller 110 after fig. 5. Referring to fig. 6, the memory controller 10 may transmit an external address ADDRe and an external command CMDe (e.g., a write command) to the controller 110 and may control an external selection signal Se as in the first part of fig. 3 in operation S315.

In operation S316, the memory controller 10 may transmit a data signal DQ to the controller 110 through the first data line 141. In operation S317, the controller 110 may store the external address ADDRe and the data signal DQ received from the memory controller 10 as the second data entity DQ _ ET2 to the first region 113. In operation S318, the controller 110 may store a second write pointer W _ PTR2 pointing to a second data entity DQ _ ET2 to the second region 114.

In one embodiment, the controller 110 may replace the first data entity DQ _ ET1 with the second data entity DQ _ ET2 when the external address ADDRe of the second data entity DQ _ ET2 is the same as the external address ADDRe of the first data entity DQ _ ET 1. Also, the controller 110 may replace the first write pointer W _ PTR1 with the second write pointer W _ PTR 2.

Fig. 7 is a diagram illustrating an example in which the controller 110 writes the data stored in the buffer 112 to the first nonvolatile memory device 121 when the flush condition is satisfied after fig. 6. Referring to fig. 7, the controller 110 reads the oldest first write pointer W _ PTR1 from among the write pointers stored in the second area 114 of the buffer 112 in operation S321.

In operation S322, the controller 110 reads the first data entity DQ _ ET1 according to the first write pointer W _ PTR1 thus read. The controller 110 may generate the internal address ADDRi from the external address ADDRe of the first data entity DQ _ ET 1. The controller 110 may generate an internal command CMDi (e.g., a write command) from the first write pointer W _ PTR 1.

In operation S323, the controller 110 transmits the internal address ADDRi and the internal command CMDi to the first nonvolatile memory device 121 through the first data line 141 by using the physical block 111, and may adjust the internal selection signal Si as in the second part of fig. 3. In operation S324, the controller 110 transmits a data signal DQ to the first nonvolatile memory device 121 through the first data line 141 by using the physical block 111.

Similarly, in operation S325, the controller 110 reads the second write pointer W _ PTR2 from the second area 114; in operation S326, the controller 110 reads the second data entity DQ _ ET2 from the first region 113. The controller 110 may control the internal selection signal Si like the second part of fig. 3 by transmitting the internal address ADDRi and the internal command CMDi to the first nonvolatile memory device 121 through the first data line 141 using the physical block 111 in operation S327 and transmit the data signal DQ in operation S328.

The first non-volatile memory device 121 may write the data signal DQ of the first data entity DQ _ ET1 according to operation S323, and may write the data signal DQ of the second data entity DQ _ ET2 according to operation S327.

In one embodiment, the controller 110 may remove the corresponding write pointer of the second region 114 after writing the data signal DQ of the specific data entity to the first nonvolatile memory device 121. The controller 110 may write the data signal DQ of a specific data entity to the first nonvolatile memory device 121 and then may hold the specific data entity in the first region 113 or may remove the specific data entity from the first region 113.

Fig. 8 is a flowchart illustrating an example in which the memory controller 10 reads data from the semiconductor memory module 100. Referring to fig. 1 and 8, the controller 110 receives an external address ADDRe, an external command CMDe (e.g., a read command), and an activated external selection signal Se from the memory controller 10 in operation S410.

In operation S420, the controller 110 determines whether the data signal DQ corresponding to the external address ADDRe exists in the buffer 112. In the case where the data signal DQ corresponding to the external address ADDRe exists in the buffer 112, the controller 110 transmits the data signal DQ stored in the buffer 112 to the memory controller 10 in operation S480. The read process may then be terminated.

In the case where the data signal DQ corresponding to the external address ADDRe does not exist in the buffer 112, operation S430 is performed. In operation S430, the controller 110 may notify the memory controller 10 that a backup read operation is required. For example, the controller 110 may notify the memory controller 10 that a backup read operation is required by activating an error signal, deactivating a ready signal, or outputting a dummy data signal with an error.

The backup read operation may indicate a read operation of reading data requested by the memory controller 10 from the first through ninth nonvolatile memory devices 121 through 129 and storing the read data to the buffer 112 of the controller 110.

In operation S440, the controller 110 transmits an internal address ADDRi corresponding to an external address ADDRe, an internal command CMDi (e.g., a read command), and an activated internal selection signal Si to the first through ninth nonvolatile memory devices 121 through 129.

In operation S450, the controller 110 receives data signals DQ corresponding to the internal address ADDRi from the first to ninth nonvolatile memory devices 121 to 129, and may store the received data signals DQ to the buffer 112.

In operation S460, the controller 110 notifies the memory controller 10 that the backup read operation is completed. For example, the controller 110 may notify the memory controller 10 that the backup read operation is completed by deactivating an error signal, activating a ready signal, or stopping outputting a dummy data signal having an error.

In operation S470, the controller 110 receives the external address ADDRe, the external command CMDe, and the activated external selection signal Se from the memory controller 10. Operation S470 may correspond to a retry of operation S410. Accordingly, the information received in operation S470 may be the same as the information received in operation S410. In operation S480, the controller 110 may transmit the data signal DQ stored in the buffer 112 to the memory controller 10. Thereafter, the read process may be terminated.

In one embodiment, in response to the notification of operation S430, the memory controller 10 may periodically repeat operation S470 (or operation S410) of requesting a read operation from the controller 110. By repeating operation S430, the controller 110 may provide a notification that the data is not ready. In this case, operation S460 may be omitted. When the controller 110 does not perform the notification of operation S430, the memory controller 10 may successfully read data from the semiconductor memory module 100 through operation S480.

As described above, the controller 110 may notify the memory controller 10 that a backup read operation is required to prevent communication between the memory controller 10 and the controller 110 from conflicting with communication between the controller 110 and the first to ninth nonvolatile memory devices 121 to 129.

Fig. 9 is a diagram illustrating an example in which the memory controller 10 reads the data signal DQ stored in the buffer 112 after fig. 7. Referring to fig. 9, the memory controller 10 transmits an external address ADDRe and an external command CMDe (e.g., a read command) to the controller 110 and may control an external selection signal Se as in the first part of fig. 3 in operation S511.

In response to the external command CMDe, the controller 110 determines whether a data entity corresponding to the external address ADDRe exists in the first area 113 of the buffer 112. For example, the external address ADDRe received from the memory controller 10 may coincide with the external address ADDRe of the second data entity DQ _ ET 2.

In operation S512, the controller 110 reads the data signal DQ of the second data entity DQ _ ET2 stored in the first region 113. In operation S513, the controller 110 transmits the data signal DQ read from the first region 113 to the memory controller 10 through the first data line 141.

Fig. 10 is a diagram illustrating an example in which the memory controller 10 reads the data signal DQ not stored in the buffer 112 after fig. 9. Referring to fig. 10, the memory controller 10 may transmit an external address ADDRe and an external command CMDe (e.g., a read command) to the controller 110 and may control an external selection signal Se as in the first part of fig. 3 in operation S514.

The controller 110 may determine that a data entity corresponding to the external address ADDRe received from the memory controller 10 is not stored in the buffer 112. Controller 110 may notify memory controller 10 that a backup read operation is required.

In operation S515, the controller 110 transmits the internal address ADDRi, the internal command CMDi (e.g., a read command), and the internal selection signal Si adjusted as illustrated in the second part of fig. 3 to the first nonvolatile memory device 121. The first nonvolatile memory device 121 may read data according to the internal address ADDRi, the internal command CMDi, and the activated internal selection signal Si.

In operation S516, the first nonvolatile memory device 121 transmits the read data as a data signal DQ to the controller 110 through the first data line 141. In operation S517, the controller 110 stores the external address ADDRe received from the memory controller 10 and the data signal DQ received from the first nonvolatile memory device 121 as the third data entity DQ _ ET3 in the first region 113 of the buffer 112.

When the third data entity DQ _ ET3 is stored in the first region 113, the controller 110 may notify the memory controller 10 that the back-up read operation has been completed. When the backup read operation has been completed, the memory controller 10 transmits the external address ADDRe and the external command CMDe to the controller 110 and may control the external selection signal Se as in the first part of fig. 3 in operation S518.

In operation S519, the controller 110 reads the data signal DQ of the third data entity DQ _ ET3 of the first region 113. In operation S520, the controller 110 transmits the data signal DQ read from the first region 113 to the memory controller 10 through the first data line 141.

Fig. 11 is a flowchart illustrating an example of a method in which the controller 110 manages the buffer 112. Referring to fig. 1 and 11, the controller 110 monitors the storage capacity of the buffer 112 in operation S610.

In operation S620, according to the result of the monitoring, the controller 110 determines whether the free storage capacity of the buffer 112 is less than a threshold. In the case where the free storage capacity of the buffer 112 is not less than the threshold value, the process is terminated. In the case where the free storage capacity of the buffer 112 is less than the threshold, operation S630 is performed.

In operation S630, the controller 110 may discard a Least Recently Used (LRU) data signal DQ among the data signals DQ stored in the buffer 112. For example, the controller 110 may discard the clean data signals DQ that do not need to be written to the first through ninth nonvolatile memory devices 121 through 129.

As another example, the controller 110 may write the dirty data signals DQ, which should be written to the first to ninth nonvolatile memory devices 121 to 129, to the first to ninth nonvolatile memory devices 121 to 129 (refer to fig. 7), and may discard the corresponding data signals DQ.

For example, the controller 110 may be configured to discard the oldest used data signal DQ first or discard the clean data signal DQ first. The priority of data that may be discarded by the controller 110 may be set by the memory controller 10.

Fig. 12 is a flowchart illustrating an example in which the controller 110 arbitrates communication through the first to ninth data lines 141 to 149. Referring to fig. 1 and 12, the controller 110 receives an external command CMDe or an external selection signal Se from the memory controller 10 in operation S710. For example, the arbitration method according to one embodiment of the inventive concept may be triggered by the external command CMDe or the external selection signal Se.

In operation S720, the controller 110 determines whether communication with the first through ninth nonvolatile memory devices 121 through 129 is being performed (e.g., will be performed). When the controller 110 does not communicate with the first to ninth nonvolatile memory devices 121 to 129, the controller 110 may perform an access associated with the external command CMDe (refer to fig. 5, 6, 9, 10, or 13). Thereafter, the process is terminated.

If the controller 110 is communicating with the first through ninth nonvolatile memory devices 121 through 129, the controller 110 may send (e.g., activate) a stop signal to the first through ninth nonvolatile memory devices 121 through 129 in operation S740. According to the stop signal, the first through ninth nonvolatile memory devices 121 through 129 may stop exchanging the internal data signals DQi with the first through ninth data lines 141 through 149. The controller 110 may then perform the access associated with the external command CMDe.

In operation S750, the controller 110 may retry the operation stopped by the stop signal after performing the access associated with the external command CMDe. For example, the controller 110 may request the first to ninth nonvolatile memory devices 121 to 129 to resume the stopped operation. For another example, the controller 110 may request an operation to be stopped again from the beginning by the internal address ADDRi, the internal command CMDi, and the internal select signal Si.

Fig. 13 is a diagram illustrating an example in which the memory controller 10 directly accesses the first nonvolatile memory device 121 through the first data line 141. Referring to fig. 13, the memory controller 10 transmits an external address ADDRe and an external command CMDe (e.g., a write command) to the controller 110 in operation S811, and may control an external selection signal Se as in the third part of fig. 3.

The physical block 111 of the controller 110 may generate an internal address ADDRi and an internal command CMDi from the external address ADDRe and the external command CMDe. In operation S812, the controller 110 transmits the internal address ADDRi, the internal command CMDi, and the internal selection signal Si adjusted as illustrated in the third part of fig. 3 to the first nonvolatile memory device 121. In operation S813, the memory controller 10 directly transmits a data signal DQ to the first nonvolatile memory device 121 through the first data line 141 (e.g., no data passes through the controller 110). For example, the data signal DQ may pass through the data buffer 131 without being stored to the controller.

In operation S814, the memory controller 10 transmits an external address ADDRe and an external command CMDe (e.g., a read command) to the controller 110, and may control the external selection signal Se as in the third part of fig. 3. The physical block 111 of the controller 110 may generate an internal address ADDRi and an internal command CMDi from the external address ADDRe and the external command CMDe.

In operation S815, the controller 110 transmits the internal address ADDRi, the internal command CMDi, and the internal selection signal Si adjusted as illustrated in the third part of fig. 3 to the first nonvolatile memory device 121. In operation S816, the memory controller 10 receives the data signal DQ directly from the first nonvolatile memory device 121 through the first data line 141 (e.g., no data passes through the controller 110).

Fig. 14 is a block diagram illustrating a semiconductor memory module 100_1 according to a second embodiment of the inventive concept. The components of the semiconductor memory module 100_1 are the same as those of the semiconductor memory module 100 of fig. 1 except for the first to ninth data lines 141a to 149 a. Therefore, additional description will be omitted to avoid redundancy.

Referring to fig. 14, the first to ninth data lines 141a to 149a may include a first line extending from opposite sides of the controller 110, a second line connecting the first line and the first to ninth nonvolatile memory devices 121 to 129, and a third line connecting the first line and the first to ninth data buffers 131 to 139. The second and third lines may be implemented as the same lines as described with reference to fig. 1. The first line may have the same length regardless of a position of the first node connected with the second line or a position of the second node connected with the third line.

The loads of the first to ninth data lines 141a to 149a from the controller 110 may become balanced. The loads of the first to ninth data lines 141a to 149a may become balanced as viewed from the first to ninth nonvolatile memory devices 121 to 129. Also, the loads of the first to ninth data lines 141a to 149a may become balanced from the first to ninth data buffers 131 to 139. Therefore, the transmission timings of the internal data signals DQi may be equalized. Therefore, time lag can be prevented.

Fig. 15 is a block diagram illustrating a semiconductor memory module 100_2 according to a third embodiment of the inventive concept. The components of the semiconductor memory module 100_2 are the same as those of the semiconductor memory module 100 of fig. 1 except for the first to ninth data lines 141b to 149 b. Therefore, additional description will be omitted to avoid redundancy.

Referring to fig. 15, the first lines of the first to ninth data lines 141b to 149b may have different lengths. The positions of the first and second nodes may be adjusted to make the loads of the first to ninth data lines 141b to 149b more similar. For example, the data line 141b or 149b may be formed by connecting a second line of the nonvolatile memory device 121 or 129 farthest from the controller 110 and a third line of the data buffer 135 or 136 closest to the controller 110 to one first line.

The data line 142b or 148b may be formed by connecting a second line of the nonvolatile memory device 122 or 128, which is second distant from the controller 110, and a third line of the data buffer 134 or 137, which is second near to the controller 110, with another first line.

The data line 145b or 146b may be formed by connecting a second line of the nonvolatile memory device 125 or 126 closest to the controller 110 and a third line of the data buffer 131 or 139 farthest from the controller 110 to another first line.

Fig. 16 is a block diagram illustrating a semiconductor memory module 100_3 according to a fourth embodiment of the inventive concept. In comparison with the semiconductor memory module 100 of fig. 1, the semiconductor memory module 100_3 includes first to ninth nonvolatile memory devices 121a to 129a of a first rank (rank) and first to ninth nonvolatile memory devices 121b to 129b of a second rank. Note that although data lines 141-149 are shown, the modified data line structure of fig. 14 or 15 may be used instead.

The controller 110 may collectively transmit the internal address ADDRi, the internal command CMDi, and the internal selection signal Si to the first through ninth nonvolatile memory devices 121a through 129a in the first bank and the first through ninth nonvolatile memory devices 121b through 129b in the second bank through the first control lines 151 and 152.

The first nonvolatile memory devices 121a and 121b may be commonly connected to the first data line 141. The second nonvolatile memory devices 122a and 122b may be commonly connected to the second data line 142. Also, a specific nonvolatile memory in the first bank may be commonly connected to one data line together with a corresponding nonvolatile memory device in the second bank.

Fig. 17 and 18 are diagrams illustrating an example of adjusting the external selection signal Se and the internal selection signal Si. Referring to fig. 16 to 18, the external selection signal Se may include first to third external selection signals Se1 to Se 3. The first external selection signal Se1 may be activated (to a low level) by the memory controller 10 to cause the memory controller 10 or set the memory controller 10 to access the first through ninth nonvolatile memory devices 121a through 129a in the first bank through the controller 110.

The second external selection signal Se2 may be activated (to a low level) by the memory controller 10 to cause the memory controller 10 or set the memory controller 10 to access the first through ninth nonvolatile memory devices 121b through 129b in the second bank through the controller 110. The third external select signal Se3 may be activated (to a low level) by the memory controller 10 to cause the memory controller 10 or set the memory controller 10 to access the first through ninth nonvolatile memory devices 121a through 129a in the first bank or the first through ninth nonvolatile memory devices 121b through 129b in the second bank without going through the controller 110 (e.g., bypassing the controller 110).

The internal selection signals Si may include the first through third internal selection signals Si1 through Si 3. The first internal selection signal Si1 may be activated (to a low level) by the controller 110 to cause the controller 110 or set the controller 110 to access the first through ninth nonvolatile memory devices 121a through 129a in the first bank.

The second internal selection signal Si2 may be activated (to a low level) by the controller 110 to cause the controller 110 or set the controller 110 to access the first through ninth nonvolatile memory devices 121b through 129b in the second bank. The third internal selection signal Si3 may be activated by the controller 110 to cause the controller 110 or to set the controller 110 to disable communication of the first through ninth non-volatile storage devices 121a through 129a in the first bank and communication of the first through ninth non-volatile storage devices 121b through 129b in the second bank.

In the first section, the memory controller 10 and the controller 110 may communicate with each other through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149. In the first section, the memory controller 10 may provide notification that the first to ninth nonvolatile memory devices 121a to 129a in the first bank are access targets by activating the first external selection signal Se 1. Information on activation of the first external selection signal Se1 may be stored to the buffer 112.

The controller 110 may transmit the write command WR or the read command RD as the buffer command BCOM. The controller 110 may disable the communication of the nonvolatile memory devices 121a to 129a and 121b to 129b by activating the third internal selection signal Si 3.

In the second section, the controller 110 and the first to ninth nonvolatile memory devices 121a to 129a in the first bank may communicate with each other through the first to ninth data lines 141 to 149. According to the activation information of the first external selection signal Se1 stored in the buffer 112, the controller 110 may activate the first internal selection signal Si1 to communicate with the first through ninth nonvolatile memory devices 121a through 129a in the first bank.

In the third section, the memory controller 10 and the first to ninth nonvolatile memory devices 121a to 129a in the first bank may communicate with each other through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149.

The memory controller 10 may activate the first external select signal Se1 and the third external select signal Se3 to provide notification that the memory controller 10 directly accesses the first through ninth nonvolatile memory devices 121a through 129a in the first bank. The controller 110 may transmit the write command WR or the read command RD as the buffer command BCOM.

In the fourth section, the memory controller 10 and the controller 110 may communicate with each other through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149. In the fourth section, the memory controller 10 may activate the second external selection signal Se2 to provide notification that the first to ninth nonvolatile memory devices 121b to 129b in the second bank are access targets. Information on activation of the second external selection signal Se2 may be stored to the buffer 112.

The controller 110 may transmit the write command WR or the read command RD as the buffer command BCOM. The controller 110 may disable the communication of the nonvolatile memory devices 121a to 129a and 121b to 129b by activating the third internal selection signal Si 3.

In the fifth section, the controller 110 and the first to ninth nonvolatile memory devices 121b to 129b in the second bank may communicate with each other through the first to ninth data lines 141 to 149. According to the activation information of the second external selection signal Se2 stored in the buffer 112, the controller 110 may activate the second internal selection signal Si2 to communicate with the first through ninth nonvolatile memory devices 121b through 129b in the second bank.

In the sixth section, the memory controller 10 and the first to ninth nonvolatile memory devices 121b to 129b in the second bank may communicate with each other through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149.

The memory controller 10 may activate the second external selection signal Se2 and the third external selection signal Se3 to provide notification that the first to ninth nonvolatile memory devices 121b to 129b in the second bank are direct access targets. The controller 110 may transmit the write command WR or the read command RD as the buffer command BCOM.

Fig. 19 is a block diagram illustrating a semiconductor memory module 100_4 according to a fifth embodiment of the inventive concept. In contrast to the semiconductor memory module 100_3 of fig. 16, the memory controller 10 includes the first error correction block 11, and the first error correction code ECC1 is included in this first error correction block 11. The controller 110 may comprise a second error correction block 115, in which second error correction block 115 a second error correction code ECC2 is comprised. Note that although data lines 141-149 are shown, the modified data line structure of fig. 14 or 15 may be used instead.

To prevent a conflict between the first error correction block 11 of the memory controller 10 and the second error correction block 115 of the controller 110, the memory controller 10 may be configured to pass through the buffer 112 of the controller 110 when accessing the first to ninth nonvolatile memory devices 121a to 129a in the first bank and to bypass the buffer 112 of the controller 110 when accessing the first to ninth nonvolatile memory devices 121b to 129b in the second bank.

For example, when the memory controller 10 writes data to the first to ninth nonvolatile memory devices 121a to 129a in the first bank, the first error correction block 11 may generate a first error correction parity bit (e.g., error correction encoding may be performed), and the second error correction block 115 may generate a second error correction parity bit (e.g., error correction encoding may be performed). The first error correction parity bit and the second error correction parity bit may be written to the first through ninth nonvolatile memory devices 121a through 129a along with data.

When the memory controller 10 reads data from the first to ninth nonvolatile memory devices 121a to 129a, the second error correction block 115 may correct errors (e.g., error correction decoding may be performed) by using the second error correction parity bits, and the first error correction block 11 may correct errors (e.g., error correction decoding may be performed) by using the first error correction parity bits.

When the memory controller 10 writes data to the first through ninth nonvolatile memory devices 121b through 129b in the second bank, the first error correction block 11 may generate first error correction parity bits. The first error correction parity bits may be written to the first through ninth nonvolatile memory devices 121b through 129b along with the data.

When the memory controller 10 reads data from the first through ninth nonvolatile memory devices 121b through 129b, the first error correction block 11 may correct errors by using the first error correction parity bits.

According to aspects of the inventive concept, the nonvolatile memory device, the data buffer, and the controller communicate with each other through a common data line. Accordingly, a semiconductor memory module having reduced cost and reduced noise while conforming to the standard of a main memory is provided.

Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as set forth in the following claims.