阅读说明：本技术 适应于功能工程翻新的集成电路建立时序修复方法 (Integrated circuit establishing time sequence repairing method suitable for functional engineering renovation ) 是由 黄鹏程 赵振宇 乐大珩 马驰远 何小威 冯超超 贾勤 余金山 于 2019-09-09 设计创作，主要内容包括：本发明公开了一种适应于功能工程翻新的集成电路建立时序修复方法,本发明提出了一套规范化的设计流程包括网表的工程翻新、物理数据的工程翻新、翻新网表的化简、化简网表的布局布线、逻辑替换、分支连接以及第一次等价性检查,第一次等价性检查通过后再进行分支优化、第二次等价性检查,第二次等价性检查通过再进行位置翻新、绕线翻新。本发明通过设计流程实现新增时序单元的位置合理摆放、时序功能工程翻新后数据路径的重新规划、时序功能工程翻新后绕线资源的重新分配,从而以加速工程翻新后物理设计中建立时序的修复,减少功能工程翻新带来的设计周期开销。(The invention discloses an integrated circuit establishing time sequence repairing method suitable for functional engineering renovation, and provides a set of standardized design flow comprising the engineering renovation of a net list, the engineering renovation of physical data, the simplification of a renovated net list, the layout and wiring of the simplified net list, logic replacement, branch connection and first equivalence check, wherein the first equivalence check is followed by branch optimization and second equivalence check, and the second equivalence check is followed by position renovation and winding renovation. The invention realizes the reasonable arrangement of the positions of the newly added time sequence units, the re-planning of the data paths after the time sequence functional engineering is renovated and the re-distribution of the winding resources after the time sequence functional engineering is renovated through the design process, thereby accelerating the repair of the time sequence established in the physical design after the engineering is renovated and reducing the design cycle overhead caused by the renovation of the functional engineering.)

1. An integrated circuit establishment timing sequence repair method suitable for functional engineering renovation is characterized by comprising the following implementation steps:

1) saving an initial physical design state db0 of a module to be renovated before renovation operation is carried out, carrying out function modification on the module to be renovated to obtain a renovated module rt1, carrying out function engineering renovation on an initial netlist _0 of the module to be renovated based on the modification to obtain a first netlist _1, and carrying out function engineering renovation on an initial testability design netlist _ dft _0 to obtain a first testability design netlist _ dft _ 1;

2) importing a first netlist _1 under an initial physical design state db0, placing a set Coll _1 formed by non-sequential logic units in the imported first netlist _1 without placing, placing a set Regs _1 formed by sequential logic units without winding, and directly storing the set Regs _1 as a first physical design state db 1;

3) simplifying the renovated netlist and saving the renovated netlist as a second physical design state db 2;

4) acquiring the position information of all registers in the initial physical design state db0 and storing the position information as a file reg _ place.tcl, executing the file reg _ place.tcl in the second physical design state db2, placing the positions of all registers at the same position as the position of the register in the initial physical design state db0 in advance, re-placing the position of the combinational logic unit according to the physical design distance of the module to be renovated, constructing a clock tree, performing winding and optimization, and storing the position information as a third physical design state db 3;

5) finding out the data paths related to the renovated units in the first physical design state db1 for re-planning, keeping part of the data paths of the non-renovated units in a disconnected state and forming branches where the data paths are disconnected, and saving the data paths as a fifth physical design state db 5;

6) connecting the sets of the branches in the disconnected state in the fifth physical design state db5 one by one, storing and covering the fifth physical design state db5, and recording a netlist corresponding to the new fifth physical design state db5 as a fifth netlist _ 5;

7) carrying out equivalence check on the fifth netlist _5 and the first netlist _1, and if the equivalence check is passed, executing the step 8) in a skipping mode, and if the equivalence check is passed, executing the step 6) in the skipping mode to change branch connection;

8) for each of the set of branches in the fifth physical design state db5 in the disconnected state, finding a combinational logic unit driving the branch, traversing all inverters and buffers behind the unit, selecting the most appropriate inverter or buffer to drive the branch according to the position information and the load information on the layout, still saving and covering the fifth physical design state db5, and covering the fifth netlist _5 by the netlist corresponding to the new fifth physical design state db 5;

9) carrying out equivalence check on the fifth netlist _5 and the first netlist _1, and executing the step 10) if the equivalence check is passed, otherwise, executing the step 8) for branch optimization;

10) the refurbishment of the cells in the fifth physical design state db5 eliminates the presence of cell overlap in the fifth physical design state db5, preserving the overlay of the fifth physical design state db 5;

11) and performing wire winding renovation on the fifth physical design state db5 or performing wire winding and wire winding optimization in the physical design process, preserving the coverage of the fifth physical design state db5, and ending and exiting.

2. The integrated circuit building timing repair method adapted to functional engineering refurbishment according to claim 1, wherein the detailed steps of step 1) include:

1.1) saving the initial physical design state db0 of the module to be refurbished before the refurbishment operation is carried out;

1.2) carrying out function modification on a module to be renovated to obtain a renovated module rt 1;

1.3) carrying out functional engineering renovation and correcting wrong functional design on the original netlist _0 of the module to be renovated based on modification to obtain a first netlist _ 1; performing functional engineering renovation and correcting wrong functional design on an initial testability design netlist _ dft _0 of a module to be renovated based on modification to obtain a first testability design netlist _ dft _ 1;

1.4) carrying out equivalence check on the first testability design netlist _ dft _1 and the renovated module rt1, carrying out equivalence check on the new netlist _1 and the first testability design netlist _ dft _1, and skipping to execute the step 2 if the equivalence checks are all passed); otherwise, the jump executes step 1.2).

3. The integrated circuit building timing repair method adapted to functional engineering refurbishment according to claim 1, wherein the detailed steps of step 3) comprise: simplifying the first netlist _1, deleting inverters on all data paths to the maximum extent on the basis of keeping equivalence, deleting buffer on all data paths to obtain a second netlist _2, importing the second netlist _2 into the initial physical design state db0, and saving the second netlist _2 as a second physical design state db 2.

4. The integrated circuit building timing repair method adapted to functional engineering refurbishment according to claim 1, wherein the detailed steps of step 3) comprise: the simplification process is directly performed in the first physical design state db1, and the inverters inverter on all data paths are deleted to the maximum extent and the buffer buffers on all data paths are deleted on the basis of keeping equivalence, and the result is stored as a second physical design state db 2.

5. The integrated circuit building timing repair method adapted to functional engineering refurbishment according to claim 1, wherein the detailed steps of step 3) comprise: the initialization operation is performed in the place and route tool directly using the first testability design netlist _ dft _1, saved as the second physical design state db 2.

6. The integrated circuit building timing repair method adapted to functional engineering refurbishment according to claim 1, wherein the detailed steps of step 5) comprise: in the first physical design state db1, finding out all fan-out register sets Coll1_ out _ regs of a set Coll _1 formed by non-sequential logic units, then finding out all fan-in register sets Coll1_ in _ regs of a register set Coll1_ out _ regs, and grabbing out all units on all data paths from a Q end of the register set Coll1_ in _ regs to a D end of the register set Coll1_ out _ regs to form a set Coll1_ rel _ cells _ db 1; capturing and deleting the connection relation of all units in the set coll1_ rel _ cells _ db1, and saving the current design state as a fourth physical design state db 4; capturing all the units on all the data paths from the Q end of the register set coll1_ in _ regs to the D end of the register set coll1_ out _ regs in a third physical design state db3 to form a set coll1_ rel _ cells _ db 3; the position information of the cells in the set coll1_ rel _ cells _ db3 and their interconnection relationship are written into a file rel _ cell _ db3_ place. tcl, the file rel _ cell _ db3_ place. tcl is executed in the fourth physical design state db4, so that all data paths from the Q terminal of the register set coll1_ in _ regs to the D terminal of the register set coll1_ out _ regs are reestablished, and the current design state is saved as the fifth physical design state db 5.

7. The method for establishing time sequence repair of integrated circuits adaptive to functional engineering renovation as claimed in claim 6, wherein the step 6) of connecting the sets of branches in the disconnected state in the fifth physical design state db5 one by one specifically refers to connecting the sets of combined logic units one by one according to the functions of the combined logic units in the sets coll1_ rel _ cells _ db1 and coll1_ rel _ cells _ db3 before and after replacement.

Technical Field

The invention relates to the field of physical design of a super-large scale integrated circuit, relates to repair of a built time sequence (setup) in physical design, and particularly relates to a method for repairing the built time sequence of the integrated circuit, which is suitable for Engineering Change Order (ECO).

Background

Since the advent of CMOS integrated circuit technology, the integration and complexity of integrated circuits and chips has increased exponentially, and the front-end logic designs of integrated circuits and chips have become increasingly complex. Meanwhile, the operating frequency of the integrated circuit also shows an increasing trend along with the progress of the process, and the timing requirement of the physical design of the integrated circuit becomes more and more complex and more demanding. When the front-end logic needs to repair a design bug (bug), the back-end physical design has two ways of doing rework and functional engineering renovation (ECO). The cost of redoing is often enormous, almost doubling the design cycle, and is generally used only in extreme cases. The cost of engineering refurbishment (ECO) is relatively small and is widely regarded by the industry. As the operating frequency of integrated circuits is increasing, the design complexity is increasing, the influence of functional engineering refreshing (ECO) on the physical design timing (timing) is becoming more and more serious, and one refreshing operation often causes tens of thousands of paths (paths) to generate a timing violation, so that timing repair becomes very difficult.

Disclosure of Invention

The technical problems to be solved by the invention are as follows: the invention provides a set of standardized design flow, and realizes reasonable arrangement of positions of newly-added time sequence units, re-planning of data paths after time sequence functional engineering is renovated and re-distribution of winding resources after time sequence functional engineering is renovated through the design flow, so that time sequence repair built in physical design after engineering renovation is accelerated, and design cycle overhead caused by functional engineering renovation is reduced.

In order to solve the technical problems, the invention adopts the technical scheme that:

an integrated circuit establishment timing sequence repair method suitable for functional engineering renovation comprises the following implementation steps:

1) saving an initial physical design state db0 of a module to be renovated before renovation operation is carried out, carrying out function modification on the module to be renovated to obtain a renovated module rt1, carrying out function engineering renovation on an initial netlist _0 of the module to be renovated based on the modification to obtain a first netlist _1, and carrying out function engineering renovation on an initial testability design netlist _ dft _0 to obtain a first testability design netlist _ dft _ 1;

2) importing a first netlist _1 under an initial physical design state db0, placing a set Coll _1 formed by non-sequential logic units in the imported first netlist _1 without placing, placing a set Regs _1 formed by sequential logic units without winding, and directly storing the set Regs _1 as a first physical design state db 1;

3) simplifying the renovated netlist and saving the renovated netlist as a second physical design state db 2;

4) acquiring the position information of all registers in the initial physical design state db0 and storing the position information as a file reg _ place.tcl, executing the file reg _ place.tcl in the second physical design state db2, placing the positions of all registers at the same position as the position of the register in the initial physical design state db0 in advance, re-placing the position of the combinational logic unit according to the physical design distance of the module to be renovated, constructing a clock tree, performing winding and optimization, and storing the position information as a third physical design state db 3;

5) finding out the data paths related to the renovated units in the first physical design state db1 for re-planning, keeping part of the data paths of the non-renovated units in a disconnected state and forming branches where the data paths are disconnected, and saving the data paths as a fifth physical design state db 5;

6) connecting the sets of the branches in the disconnected state in the fifth physical design state db5 one by one, storing and covering the fifth physical design state db5, and recording a netlist corresponding to the new fifth physical design state db5 as a fifth netlist _ 5;

7) carrying out equivalence check on the fifth netlist _5 and the first netlist _1, and if the equivalence check is passed, executing the step 8) in a skipping mode, and if the equivalence check is passed, executing the step 6) in the skipping mode to change branch connection;

8) for each of the set of branches in the fifth physical design state db5 in the disconnected state, finding a combinational logic unit driving the branch, traversing all inverters and buffers behind the unit, selecting the most appropriate inverter or buffer to drive the branch according to the position information and the load information on the layout, still saving and covering the fifth physical design state db5, and covering the fifth netlist _5 by the netlist corresponding to the new fifth physical design state db 5;

9) carrying out equivalence check on the fifth netlist _5 and the first netlist _1, and executing the step 10) if the equivalence check is passed, otherwise, executing the step 8) for branch optimization;

10) the refurbishment of the cells in the fifth physical design state db5 eliminates the presence of cell overlap in the fifth physical design state db5, preserving the overlay of the fifth physical design state db 5;

11) and performing wire winding renovation on the fifth physical design state db5 or performing wire winding and wire winding optimization in the physical design process, preserving the coverage of the fifth physical design state db5, and ending and exiting.

Optionally, the detailed steps of step 1) include:

1.1) saving the initial physical design state db0 of the module to be refurbished before the refurbishment operation is carried out;

1.2) carrying out function modification on a module to be renovated to obtain a renovated module rt 1;

1.3) carrying out functional engineering renovation and correcting wrong functional design on the original netlist _0 of the module to be renovated based on modification to obtain a first netlist _ 1; performing functional engineering renovation and correcting wrong functional design on an initial testability design netlist _ dft _0 of a module to be renovated based on modification to obtain a first testability design netlist _ dft _ 1;

1.4) carrying out equivalence check on the first testability design netlist _ dft _1 and the renovated module rt1, carrying out equivalence check on the new netlist _1 and the first testability design netlist _ dft _1, and skipping to execute the step 2 if the equivalence checks are all passed); otherwise, the jump executes step 1.2).

Optionally, the detailed steps of step 3) include: simplifying the first netlist _1, deleting inverters on all data paths to the maximum extent on the basis of keeping equivalence, deleting buffer on all data paths to obtain a second netlist _2, importing the second netlist _2 into the initial physical design state db0, and saving the second netlist _2 as a second physical design state db 2.

Optionally, the detailed steps of step 3) include: the simplification process is directly performed in the first physical design state db1, and the inverters inverter on all data paths are deleted to the maximum extent and the buffer buffers on all data paths are deleted on the basis of keeping equivalence, and the result is stored as a second physical design state db 2.

Optionally, the detailed steps of step 3) include: the initialization operation is performed in the place and route tool directly using the first testability design netlist _ dft _1, saved as the second physical design state db 2.

Optionally, the detailed steps of step 5) include: in the first physical design state db1, finding out all fan-out register sets Coll1_ out _ regs of a set Coll _1 formed by non-sequential logic units, then finding out all fan-in register sets Coll1_ in _ regs of a register set Coll1_ out _ regs, and grabbing out all units on all data paths from a Q end of the register set Coll1_ in _ regs to a D end of the register set Coll1_ out _ regs to form a set Coll1_ rel _ cells _ db 1; capturing and deleting the connection relation of all units in the set coll1_ rel _ cells _ db1, and saving the current design state as a fourth physical design state db 4; capturing all the units on all the data paths from the Q end of the register set coll1_ in _ regs to the D end of the register set coll1_ out _ regs in a third physical design state db3 to form a set coll1_ rel _ cells _ db 3; the position information of the cells in the set coll1_ rel _ cells _ db3 and their interconnection relationship are written into a file rel _ cell _ db3_ place. tcl, the file rel _ cell _ db3_ place. tcl is executed in the fourth physical design state db4, so that all data paths from the Q terminal of the register set coll1_ in _ regs to the D terminal of the register set coll1_ out _ regs are reestablished, and the current design state is saved as the fifth physical design state db 5.

Optionally, the step 6) of connecting the sets of branches in the fifth physical design state db5 in the disconnected state one by one specifically refers to connecting the sets one by one according to the functions of the combinational logic units in the sets coll1_ rel _ cells _ db1 and coll1_ rel _ cells _ db3 before and after replacement.

Compared with the prior art, the invention has the following advantages: before the method, the function engineering renovation often causes serious establishment timing violation, particularly in high-performance design, the traditional timing sequence repairing method is difficult to repair the serious establishment timing violation caused by the function engineering renovation, the repairing process is very time-consuming, and the design progress is seriously influenced. The invention is suitable for the design flow proposed by the method for building time sequence repair of the integrated circuit for renovating the functional engineering, and can reasonably plan the change of the original data path and the introduction of the new data path after the functional engineering of any module is renovated by a standardized means, thereby effectively repairing the violation of the built time sequence introduced by the renovation of the functional engineering, and having little influence on the violation of DRC (design rule check) in the process of repairing and building the time sequence. The invention realizes the reasonable arrangement of the positions of the newly added time sequence units, the re-planning of the data paths after the time sequence functional engineering is renovated and the re-distribution of the winding resources after the time sequence functional engineering is renovated through the design process, thereby accelerating the repair of the time sequence established in the physical design after the engineering is renovated and reducing the design cycle overhead caused by the renovation of the functional engineering.

Drawings

FIG. 1 is a schematic flow chart of a method according to an embodiment of the present invention.

Detailed Description