Method of manufacturing an array of MRAM-cells, method of writing the MRAM-cells

文档序号:1568625 发布日期:2020-01-24 浏览:9次 中文

阅读说明:本技术 制造mram单元的阵列的方法、写入该mram单元的方法 (Method of manufacturing an array of MRAM-cells, method of writing the MRAM-cells ) 是由 应继锋 王仲盛 牛宝华 于 2019-07-15 设计创作,主要内容包括:一种制造磁性随机存取存储器单元的阵列的方法包括写入磁性随机存取存储器单元。写入存储器单元包括确定所述存储器单元的阵列的最佳写入电流;以及将所述最佳写入电流应用于所述阵列中的第一存储器单元。将第一读取电流应用于第一存储器单元以响应于应用所述最佳写入电流,确定第一存储器单元的磁取向是否已经改变。当第一存储器单元的磁取向没有改变时,将第二写入电流应用于第一存储器单元。第二写入电流不同于最佳写入电流。将第二读取电流应用于第一存储器单元,以响应于应用第二读取电流,确定第一存储器单元的磁取向是否改变。本发明实施例还涉及写入磁性随机存取存储器单元的方法。(A method of fabricating an array of magnetic random access memory cells includes writing magnetic random access memory cells. Writing to a memory cell comprises determining an optimal write current for the array of memory cells; and applying the optimal write current to a first memory cell in the array. A first read current is applied to the first memory cell to determine whether the magnetic orientation of the first memory cell has changed in response to applying the optimal write current. The second write current is applied to the first memory cell when the magnetic orientation of the first memory cell is not changed. The second write current is different from the optimal write current. A second read current is applied to the first memory cell to determine whether the magnetic orientation of the first memory cell has changed in response to applying the second read current. Embodiments of the present invention also relate to methods of writing magnetic random access memory cells.)

1. A method of fabricating an array of magnetic random access memory cells, comprising:

a write magnetic random access memory cell comprising:

determining an optimal write current for the array of magnetic random access memory cells;

applying the optimal write current to a first magnetic random access memory cell in the array;

applying a first read current to the first magnetic random access memory cell to determine whether a magnetic orientation of the first magnetic random access memory cell has changed in response to the applying the optimal write current;

applying a second write current to the first magnetic random access memory cell when the magnetic orientation of the first magnetic random access memory cell is not changed, wherein the second write current is different from the optimal write current; and

applying a second read current to the first magnetic random access memory cell to determine whether a magnetic orientation of the first magnetic random access memory cell has changed in response to the applying the second read current.

2. The method of fabricating an array of magnetic random access memory cells of claim 1, further comprising:

applying a third write current to the first magnetic random access memory cell when the magnetic orientation of the first magnetic random access memory cell is not changed after applying the second write current, wherein the third write current is different from the optimal write current and the second write current; and

applying a third read current to the first magnetic random access memory cell to determine whether a magnetic orientation of the first magnetic random access memory cell has changed in response to the applying the third write current.

3. The method of fabricating an array of magnetic random access memory cells of claim 2, wherein the second write current is greater than the optimal write current and the third write current is less than the optimal write current.

4. The method of fabricating an array of magnetic random access memory cells of claim 2, wherein the second write current is less than the optimal write current and the third write current is greater than the optimal write current.

5. The method of fabricating an array of magnetic random access memory cells of claim 2, further comprising: iteratively repeating applying a write current and a read current when the magnetic orientation of the first magnetic random access memory cell is not changed,

wherein iteratively applying the write current and the read current is stopped when the magnetic orientation of the first magnetic random access memory cell has changed, an

Wherein a write current at each application of the write current is different from any other write current.

6. The method of fabricating an array of magnetic random access memory cells of claim 5, wherein the write current applied at each iteration alternates between being greater than the optimal write current and being less than the optimal write current.

7. The method of fabricating an array of magnetic random access memory cells of claim 5, wherein each successive write current less than the optimal write current is less than a previous write current less than the optimal write current, and each successive write current greater than the optimal write current is greater than a previous write current greater than the optimal write current.

8. The method of fabricating an array of magnetic random access memory cells of claim 5, wherein the write current applied after said applying said optimal write current alternates between a write current less than said optimal write current and a write current greater than said optimal write current.

9. A method of fabricating an array of magnetic random access memory cells, comprising:

determining an optimal write current for the array of magnetic random access memory cells, comprising:

(a) applying a first write current to one of a plurality of magnetic random access memory cells in the array of magnetic random access memory cells;

(b) applying a first read current to one of the plurality of magnetic random access memory cells to determine whether a magnetic orientation of the one of the plurality of magnetic random access memory cells has changed in response to the applying the first write current;

(c) applying a second write current to one of the plurality of magnetic random access memory cells when the magnetic orientation of the one of the plurality of magnetic random access memory cells is not changed, wherein the second write current is different from the optimal write current;

(d) applying a second read current to one of the plurality of magnetic random access memory cells to determine whether the magnetic orientation of the one of the plurality of magnetic random access memory cells has changed in response to the applying the second write current, wherein the second read current has the same value as the first read current;

(e) applying a third write current to one of the plurality of magnetic random access memory cells when the magnetic orientation of the one of the plurality of magnetic random access memory cells has not changed after applying the second write current, wherein the third write current is different from the optimal write current and the second write current;

(f) applying a third read current to one of the plurality of magnetic random access memory cells to determine whether the magnetic orientation of the one of the plurality of magnetic random access memory cells has changed in response to the applying the third write current, wherein the third read current has the same value as the first read current and the second read current;

(g) iteratively repeating applying a write current and a read current when the magnetic orientation of the one of the plurality of magnetic random access memory cells is not changed;

wherein iteratively repeating applying a write current and a read current stops when the magnetic orientation of one of the plurality of magnetic random access memory cells has changed,

wherein the write current at each application of the write current is different from any other write current, an

Wherein the first write current has a first magnitude and the magnitude of the subsequently applied write current is increased in a stepwise manner;

(h) determining a value of a write current that causes a change in magnetic orientation of the magnetic random access memory cell;

(i) repeating (a) through (h) for each magnetic random access memory cell of the plurality of magnetic random access memory cells in the array of magnetic random access memory cells; and

(j) determining the optimal write current based on the determined write current for each of the plurality of magnetic random access memory cells.

10. A method of writing to a magnetic random access memory cell, comprising:

applying a first write current to the first magnetic random access memory cell;

determining whether a magnetic orientation of the first magnetic random access memory cell changes in response to the applying the first write current;

applying a second write current to the first magnetic random access memory cell when the magnetic orientation of the first magnetic random access memory cell is not changed, wherein the second write current is different from the first write current;

determining whether a magnetic orientation of the first magnetic random access memory cell has changed in response to the applying the second write current;

applying a third write current to the first magnetic random access memory cell when the magnetic orientation of the first magnetic random access memory cell has not changed after applying the second write current, wherein the third write current is different from the first write current and the second write current; and

determining whether a magnetic orientation of the first magnetic random access memory cell has changed in response to the applying the third write current.

Technical Field

Embodiments of the present invention relate to methods of fabricating an array of MRAM cells, methods of writing the MRAM cells.

Background

Magnetic Random Access Memory (MRAM) offers comparable performance to volatile solid State Random Access Memory (SRAM) and provides comparable density and lower power consumption to volatile Dynamic Random Access Memory (DRAM). MRAM provides faster access times and suffers minimal degradation over time compared to non-volatile memory (NVM) flash memory, however flash memory can only be rewritten a limited number of times. The MRAM cell is formed by a Magnetic Tunnel Junction (MTJ) comprising two ferromagnetic layers separated by a thin insulating barrier, and operates by electron tunneling between the two ferromagnetic layers through the insulating barrier.

Disclosure of Invention

An embodiment of the present invention provides a method of fabricating an array of magnetic random access memory cells, comprising writing a magnetic random access memory cell, the writing magnetic random access memory cell comprising: determining an optimal write current for the array of magnetic random access memory cells; applying the optimal write current to a first magnetic random access memory cell in the array; applying a first read current to the first magnetic random access memory cell to determine whether a magnetic orientation of the first magnetic random access memory cell has changed in response to the applying the optimal write current; applying a second write current to the first magnetic random access memory cell when the magnetic orientation of the first magnetic random access memory cell is not changed, wherein the second write current is different from the optimal write current; and applying a second read current to the first magnetic random access memory cell to determine whether a magnetic orientation of the first magnetic random access memory cell has changed in response to the applying the second read current.

Another embodiment of the present invention provides a method of manufacturing an array of magnetic random access memory cells, comprising determining an optimal write current for the array of magnetic random access memory cells, the determining an optimal write current for the array of magnetic random access memory cells comprising: (a) applying a first write current to one of a plurality of magnetic random access memory cells in the array of magnetic random access memory cells; (b) applying a first read current to one of the plurality of magnetic random access memory cells to determine whether a magnetic orientation of the one of the plurality of magnetic random access memory cells has changed in response to the applying the first write current; (c) applying a second write current to one of the plurality of magnetic random access memory cells when the magnetic orientation of the one of the plurality of magnetic random access memory cells is not changed, wherein the second write current is different from the optimal write current; (d) applying a second read current to one of the plurality of magnetic random access memory cells to determine whether the magnetic orientation of the one of the plurality of magnetic random access memory cells has changed in response to the applying the second write current, wherein the second read current has the same value as the first read current; (e) applying a third write current to one of the plurality of magnetic random access memory cells when the magnetic orientation of the one of the plurality of magnetic random access memory cells has not changed after applying the second write current, wherein the third write current is different from the optimal write current and the second write current; (f) applying a third read current to one of the plurality of magnetic random access memory cells to determine whether the magnetic orientation of the one of the plurality of magnetic random access memory cells has changed in response to the applying the third write current, wherein the third read current has the same value as the first read current and the second read current; (g) iteratively repeating applying a write current and a read current when the magnetic orientation of the one of the plurality of magnetic random access memory cells is not changed; wherein iteratively repeating applying a write current and a read current stops when the magnetic orientation of one of the plurality of magnetic random access memory cells has changed, wherein the write current at each application of the write current is different from any other write current, and wherein the first write current has a first magnitude and the magnitude of a subsequently applied write current increases in a stepwise manner; (h) determining a value of a write current that causes a change in magnetic orientation of the magnetic random access memory cell; (i) repeating (a) through (h) for each magnetic random access memory cell of the plurality of magnetic random access memory cells in the array of magnetic random access memory cells; and (j) determining the optimal write current based on the determined write current for each of the plurality of magnetic random access memory cells.

According to yet another embodiment of the present invention, there is provided a method of writing to a magnetic random access memory cell, the method comprising: applying a first write current to the first magnetic random access memory cell; determining whether a magnetic orientation of the first magnetic random access memory cell changes in response to the applying the first write current; applying a second write current to the first magnetic random access memory cell when the magnetic orientation of the first magnetic random access memory cell is not changed, wherein the second write current is different from the first write current; determining whether a magnetic orientation of the first magnetic random access memory cell has changed in response to the applying the second write current; applying a third write current to the first magnetic random access memory cell when the magnetic orientation of the first magnetic random access memory cell has not changed after applying the second write current, wherein the third write current is different from the first write current and the second write current; and determining whether a magnetic orientation of the first magnetic random access memory cell has changed in response to the applying the third write current.

Drawings

FIG. 1A is a schematic diagram of an MTJ MRAM cell according to an embodiment of the disclosure.

Fig. 1B is a schematic cross-sectional view of an MTJ film stack according to an embodiment of the disclosure.

Fig. 2A, 2B, and 2C show schematic cross-sectional views of magnetic layers of an MTJ film stack according to embodiments of the disclosure.

Fig. 3A and 3B illustrate memory operations of the MTJ cell.

Fig. 3C and 3D illustrate memory operations of the MTJ cell.

Fig. 4 shows an MRAM array.

FIG. 5A shows an optimal write current distribution for an array of magnetic random access memory cells.

FIG. 5B shows the error rate of an array of magnetic random access memory cells at different write currents.

FIG. 5C shows the error rate of an array of magnetic random access memory cells at a jump write current.

FIG. 5D compares the error rates of multiple applications of write current at constant write current and at jump write current for an array of magnetic random access memory cells.

FIG. 6 illustrates an iterative process of ramping write current according to an embodiment of the present disclosure.

Fig. 7 is a flow chart illustrating a method of writing an MRAM cell according to an embodiment of the present disclosure.

Fig. 8 shows a circuit for a hopping write scheme, where LV denotes a low voltage, HV denotes a high voltage, and Iref denotes a reference current, in fig. 8, according to an embodiment of the present disclosure.

Fig. 9 is a flow chart of a method of determining an optimal write current for an array of MRAM cells in accordance with an embodiment of the present disclosure.

FIG. 10 shows a programmable circuit for setting the step size and write current range of an iterative write current change, R in FIG. 10, in accordance with embodiments of the present disclosure1Rn represents resistors with different numbers, Is represents current source current, Rs represents current source resistor, Iout represents output current, and Vin tableThe input voltage is shown.

FIG. 11 shows a functional test circuit according to an embodiment of the present disclosure.

Detailed Description

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on the process conditions and/or desired performance of the device. Also, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second portions are not in direct contact. Various components may be arbitrarily drawn in different scales for simplicity and clarity. In the drawings, some layers/components may be omitted for the sake of simplicity.

Furthermore, spatially relative terms (such as "below …," "below …," "lower," "above," "upper," etc.) may be used for ease of description to describe one element or component's relationship to another element(s) or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, the term "made of …" may mean "including" or "consisting of …". Further, in the following manufacturing processes, there are one or more additional operations in or between the described operations, and the order of the operations may be changed. In this disclosure, the term "one of A, B and C" means "A, B and/or C" (a, B, C, a and B, a and C, B and C, or A, B and C), and does not mean one element from a, one element from B, and one element from C unless explicitly described otherwise.

The MRAM cell includes a multi-layer film stack that includes a magnetic layer. In some MRAM devices, one or more non-magnetic spacer layers may be inserted between multiple magnetic layers to optimize magnetic interaction, depending on the magnetic design. In some embodiments, one or more diffusion barrier layers may be inserted into the film stack to minimize adverse diffusion phenomena. Furthermore, in MTJ MRAM cells, each layer in the film stack, except for the tunneling barrier, needs to be conductive to maximize the read/write window.

In some embodiments, the materials for the seed layer, spacer layer, and/or diffusion barrier layer are appropriately selected to provide the particular crystal structure and orientation desired, without disrupting the magnetic interaction of the functional layer. In addition, the seed layer, spacer layer and diffusion barrier layer should be smooth, non-specifically oriented (amorphous), conductive and non-magnetic.

The magnetic tunneling function of an MTJ MRAM cell depends on the particular crystal structure and orientation of the MTJ film. In order to have the desired crystal structure and orientation of the MTJ film, the entire film stack needs to be grown on a smooth, amorphous, conductive, non-magnetic seed layer. Among various materials, tantalum (Ta) is most widely used as a seed layer, and can be easily grown as a smooth and amorphous layer. In addition, a non-magnetic spacer layer such as molybdenum (Mo) is commonly used in the MTJ film. In addition to tantalum (Ta) and molybdenum (Mo), cobalt (Co), platinum (Pt), iridium (Ir), and/or nickel (Ni) may also be used as a seed layer or spacer layer.

A plurality of crystalline magnetic layers are grown from the crystal lattice of the MgO layer, or the plurality of crystalline magnetic layers use the crystal lattice as a growth template.

FIG. 1A is a schematic diagram of an MTJ MRAM cell according to an embodiment of the disclosure. The MTJ film stack 100 is disposed between the lower metal layer Mx and the upper metal layer My of the semiconductor device. Metal layers Mx and My are used to connect one element to another element in a semiconductor device formed at different levels above a substrate. Further, the lower metal layer Mx is coupled to a switching device SW, which may be formed of a MOS FET, including but not limited to a planar MOS FET, a fin FET, a Gate All Around (GAA) FET, or any other switching device. A control terminal of the switching device (e.g., a gate terminal of the FET) is coupled to the word line. One terminal of the switching device SW is coupled to the lower metal layer Mx and the other terminal is coupled to a power supply line, which is a fixed potential (e.g., ground voltage) in some embodiments. The upper metal layer My is coupled to a bit line. In some embodiments, the switching device SW is disposed between the upper metal layer My and the bit line.

The MTJ film stack 100 includes a first electrode layer 110 coupled to the lower metal layer Mx and a second electrode layer 155 coupled to the upper metal layer My. As shown in fig. 1B, the MTJ function layer 101 is disposed between the first electrode layer 110 and the second electrode layer 155.

The MTJ function layer 101 includes: a second fixed magnetic layer 130, a free magnetic layer 140, and a tunneling barrier layer 135 made of a non-magnetic material and disposed between the second fixed magnetic layer 130 and the free magnetic layer 140. The free magnetic layer 140 and the second fixed magnetic layer 130 include one or more ferromagnetic materials that can each be magnetically oriented. The free magnetic layer 140 is configured such that the magnetic orientation can be changed or rotated by exposure to an external magnetic field. The second fixed magnetic layer 130 is configured such that the magnetic orientation is fixed and not responsive to typical magnetic fields. In some embodiments, the thickness of the free magnetic layer 140 is in the range of about 0.8nm to about 1.5 nm. In some embodiments, the thickness of the second fixed layer 130 is in the range of about 0.8nm to about 2.0 nm.

Tunneling barrier 135 comprises a relatively thin oxide layer capable of electrically isolating free magnetic layer 140 from second fixed magnetic layer 130 at low potentials and capable of conducting current by electron tunneling at higher potentials. In some embodiments, tunnel barrier layer 135 is made of magnesium oxide (MgO), having a thickness in a range of about 0.5nm to about 1.2 nm.

In some embodiments, the MTJ functional layer 101 further includes an antiferromagnetic layer 125 as described in fig. 1B. Antiferromagnetic layer 125 is used to fix the magnetic orientation of second fixed magnetic layer 130. The antiferromagnetic layer 125 comprises ruthenium (Ru) or any other suitable antiferromagnetic material. In some embodiments, the thickness of the antiferromagnetic layer 125 is in the range of about 0.4nm to about 1.0 nm.

As shown in fig. 1B, the MTJ functional layer 101 further includes a first fixed magnetic layer, and the first fixed magnetic layer 120 includes one or more magnetic materials.

The second fixed magnetic layer 130 includes multiple layers of magnetic materials. In some embodiments, as shown in fig. 2A, the second fixed magnetic layer 130 includes four layers 1301, 1302, 1303, and 1304, wherein layer 1304 is in contact with the tunneling barrier layer 135 and layer 1301 is in contact with the antiferromagnetic layer 125. In some embodiments, layer 1301 (the bottom most layer) comprises a Co layer. In some embodiments, the cobalt layer has a thickness in a range from about 0.4nm to about 0.6 nm. In some embodiments, layer 1302 comprises a multilayer structure of cobalt (Co) and platinum (Pt). The cobalt layer has a thickness in the range of about 0.3nm to about 0.6nm and the platinum layer has a thickness in the range of about 0.2nm to about 0.5 nm. The cobalt layer may be the same thickness as the platinum layer or greater than the platinum layer. In some embodiments, multiple cobalt layers and multiple platinum layers are alternately stacked such that the total thickness of layer 1302 is in the range of about 2.0nm to about 5.0 nm. In certain embodiments, layer 1301 is a cobalt layer and layer 1302 is a multilayer of a cobalt layer and a platinum layer, as set forth above. In the present disclosure, an "elemental" layer generally means that the "element" is present in an amount greater than 99 atomic percent.

Layer 1303 is a spacer layer. In some embodiments, the spacer layer comprises Ta, Mo, Co, Pt, Ir, and/or Ni. In some embodiments, the spacer layer 1303 has a thickness in a range from about 0.2nm to about 0.5 nm. Layer 1304 is a cobalt iron boron (CoFeB) layer, a cobalt/palladium (CoPd) layer, and/or a cobalt iron (CoFe) layer. In some embodiments, the thickness of layer 1304 is in the range of about 0.8nm to about 1.5 nm.

The first fixed magnetic layer 120 includes a plurality of layers of magnetic materials. In some embodiments, as shown in FIG. 2B, the first fixed magnetic layer 120 includes two layers 1201 and 1202, where layer 1202 is in contact with the antiferromagnetic layer 125. In some embodiments, layer 1201 comprises a multilayer structure of cobalt (Co) and platinum (Pt). In some embodiments, the cobalt layer has a thickness in the range of about 0.3nm to about 0.6nm and the platinum layer has a thickness in the range of about 0.2nm to about 0.5 nm. The thickness of the cobalt layer may be the same as or greater than the thickness of the platinum layer. In some embodiments, multiple cobalt layers and multiple platinum layers are alternately stacked such that the total thickness of layer 1201 is in the range of about 5.0nm to about 10.0 nm. In some embodiments, layer 1202 comprises a cobalt layer having a thickness in the range of about 0.4nm to about 0.6 nm.

In some embodiments, the free magnetic layer 140 includes a cobalt iron boron (CoFeB), cobalt/palladium (CoPd), and/or cobalt iron (CoFe) layer having a thickness in a range of about 1.0nm to about 2.0 nm. In other embodiments, the free magnetic layer 140 includes multiple layers of magnetic material. In some embodiments, as shown in FIG. 2C, the free magnetic layer 140 comprises three layers 1401, 1402, and 1403, wherein layer 1401 is in contact with the tunneling barrier 135. In some embodiments, layers 1401 and 1403 are cobalt iron boron (CoFeB), cobalt/palladium (CoPd), and/or cobalt iron (CoFe) layers having thicknesses in the range of about 1.0 to about 2.0. Layer 1402 is a spacer layer. In some embodiments, the spacer layer comprises Ta, Mo, Co, Pt, Ir, and/or Ni. In some embodiments, the thickness of the spacer layer 1402 is in a range of about 0.2nm to about 0.6 nm.

In some embodiments, as shown in fig. 1B, the MTJ functional layer 101 further includes a seed layer 115 formed on the first electrode layer 110, a capping layer 145 formed on the free magnetic layer 140, and a diffusion barrier layer 150 formed on the capping layer 145. In some embodiments, capping layer 145 is made of a dielectric material, such as magnesium oxide or aluminum oxide, and has a thickness in the range of about 0.5nm to about 1.5 nm. In particular, for programming, the first electrode layer 110 is made of a conductive material, such as a metal, to reduce the resistance of the first fixed magnetic layer 120. The second electrode layer 155 is also made of a conductive material such as metal to reduce resistivity during reading.

In some embodiments, the seed layer 115 includes a layer of Pt or a layer of Pt and a layer of Ta. The seed layer 115 is used for growth of the first fixed magnetic layer 120, and generally has a smooth surface morphology, high conductivity, and substantially no diffusion into the first fixed magnetic layer 120. The thickness of the seed layer 115 is in the range of about 0.5nm to about 20nm in some embodiments, and in the range of about 1.0nm to about 10nm in other embodiments. In some embodiments, the seed layer 115 is amorphous.

In some embodiments, the diffusion barrier 150 includes a tantalum layer and/or a double alloy layer of iridium and tantalum. Diffusion barriers for MTJ film stacks typically have very smooth surface morphology, high conductivity, and are substantially effective in mitigating diffusion problems. Furthermore, the diffusion barrier layer should also tolerate low levels of oxidation without significant conductivity degradation. The thickness of the diffusion barrier layer 150 is in the range of about 0.1nm to about 10nm in some embodiments, and in the range of about 0.5nm to about 5.0nm in other embodiments.

In some embodiments, spacer layer 1303 and/or spacer layer 1402 include a layer of iridium and/or a layer of a double alloy of iridium and tantalum. Spacer layers for MTJ film stacks are typically required to have very smooth surface morphology and high conductivity, and to be substantially free of diffusion problems. In addition, the spacer layer should also tolerate a low level of oxidation without significant degradation of its conductivity. The thickness of spacer layers 1303 and/or 1402 is, in some embodiments, in a range from about 0.1nm to about 10nm and, in other embodiments, in a range from about 0.5nm to about 5.0 nm.

In some embodiments, the first electrode layer 110 is formed on the lower metal layer Mx, for example, made of Cu, Al, W, Co, Ni, and/or their alloys; and, for example, an upper metal layer My is made of Cu, Al, W, Co, Ni, and/or an alloy thereof, and is formed on the second electrode layer 155.

The fixed magnetic layer, free magnetic layer, antiferromagnetic layer, and spacer/barrier layer may be formed by CVD, PVD or ALD or any other suitable film deposition method. The tunneling barrier layer may be formed by CVD, PVD or ALD or any other suitable film deposition method. The first and second electrode layers may also be formed by CVD, PVD, ALD or electroplating or any other suitable film deposition method.

In some embodiments, the first electrode layer 110 is formed on the patterned lower metal layer Mx, the seed layer 115 is formed on the first electrode layer 110, the first fixed magnetic layer 120 is formed on the seed layer 115, the antiferromagnetic layer 125 is formed on the first fixed magnetic layer 120, the second fixed magnetic layer 130 is formed on the antiferromagnetic layer 125, the tunneling barrier layer 135 is formed on the second fixed magnetic layer 130, the free magnetic layer 140 is formed on the tunneling barrier layer 135, the capping layer 145 is formed on the free magnetic layer 140, the diffusion barrier layer 150 is formed on the capping layer 145, and the second electrode layer 155 is formed on the diffusion barrier layer 150. One or more photolithography and etching operations are performed to pattern the stack layers into MTJ film stacks for each memory cell. In other embodiments, a trench for a memory cell is formed in a dielectric layer and an MTJ film is formed in the trench.

In some embodiments, the MRAM cell is formed over a dielectric material disposed over a substrate. In some embodiments, the substrate comprises silicon (Si) and/or silicon oxide or other suitable semiconductor material. Transistors, driver circuits, logic circuits, or any other electronic devices are formed from semiconductor materials and integrated with the MRAM cells.

Fig. 3A to 3D illustrate memory operations of the MTJ cell. As shown in fig. 3A-3D, the MTJ cell includes a fixed magnetic layer 10, a tunneling barrier layer 15, and a free magnetic layer 20. The fixed magnetic layer 10 corresponds to the second fixed magnetic layer 130 or a combination of the first fixed magnetic layer 120, the antiferromagnetic layer 125, and the second fixed magnetic layer 130 of fig. 1B. The tunneling barrier layer 15 corresponds to the tunneling barrier layer 135 of fig. 1B and the free magnetic layer 20 corresponds to the free magnetic layer 140 of fig. 1B. In fig. 3A to 3D, the remaining layers are omitted. The current source 30 is coupled in series to the MTJ structure.

In FIG. 3A, the fixed magnetic layer 10 and the free magnetic layer 20 are magnetically oriented in opposite directions. In some embodiments, the direction of rotation of the fixed magnetic layer 10 and the free magnetic layer 20 is parallel to the film stacking direction (perpendicular to the surface of the film). In FIG. 3B, the fixed magnetic layer 10 and the free magnetic layer 20 are magnetically oriented in the same direction. In other embodiments, as shown in fig. 3C and 3D, the rotation direction of the fixed magnetic layer 10 and the free magnetic layer 20 is perpendicular to the film stacking direction (parallel to the surface of the film). In FIG. 3C, the fixed magnetic layer 10 and the free magnetic layer 20 are magnetically oriented in opposite directions, while in FIG. 3D, the fixed magnetic layer 10 and the free magnetic layer 20 are magnetically oriented in the same direction.

If the same current I is forced by the current source 30CFlowing through the MTJ cell, the cell voltage V is found in the case of FIG. 3A (or FIG. 3C)1Greater than the cell voltage V in the case of FIG. 3B (or FIG. 3D)2Because the resistance of the oppositely oriented MTJ cell shown in fig. 3A (or fig. 3C) is greater than the resistance of the identically oriented MTJ cell shown in fig. 3B (or fig. 3D). Dual logic data ("0" and "1") may be stored in the MTJ cell and retrieved based on the cell orientation and resulting resistance. Furthermore, the cell is non-volatile since the stored data does not require a storage energy source.

Fig. 4 shows an MRAM array 50. Each memory cell includes an MTJ cell Mc and a transistor Tr such as a MOS FET. A gate of the transistor Tr is coupled to the word line WL and a drain (or source) of the transistor Tr is coupled to one end of the MTJ cell Mc, and the other end of the MTJ cell is coupled to the bit line BL. Further, a signal line PL for programming is disposed adjacent to the MTJ cell.

A memory cell is read by asserting the word line of the cell, forcing a read current to flow through the bit line BL of the cell, and then measuring the voltage on the bit line BL. For example, to read the state of the target MTJ cell, the word line WL is asserted to turn on the transistor Tr. The free magnetic layer of the target MTJ cell is thus coupled to a fixed potential SL, e.g., a ground potential, through the transistor Tr. Next, a read current is forced to occur at the bit line BL. Since only the given read transistor Tr is turned on, the read current flows through the target MTJ cell to ground. Then, the voltage of the bit line BL is measured to determine the state ("0" or "1") of the target MTJ cell. In some embodiments, as shown in fig. 4, each MTJ cell has one read transistor Tr. Accordingly, this type of MRAM architecture is referred to as 1T 1R. In other embodiments, two transistors are assigned to one MTJ cell, forming a 2T1R system. Other cell array configurations may be employed.

Current MRAM testing and their field applications (eMRAM, cache, DRAM, and flash replacement) use constant bias (voltage or current) conditions during write/read testing and field applications. Because of the high sensitivity of the MRAM stack to intrinsic process variations, large die-to-die variations across the wafer, block-to-block variations across the die, and bit-to-bit variations across the block are observed. Different dies (dies located on different wafer locations, e.g., center die versus edge die), different blocks and individual bits of MRAM cells typically have significantly different read/write windows, and if a constant read/write bias is used (note that for large arrays of MRAM that can be a practical use of several hundred Megabytes (MB) to Gigabytes (GB), the die-chip can be as large as a 22mm x 32mm full mask field), the read/write window/margin (margin) cannot be tested at very high rates. Without correction, the overall wafer ensemble average constant write/degree window is too narrow to be practical and close to unusable for manufacturing, testing, and field applications. Because significant "optimum write current" differences are typically observed on bits within a small array, there is a need to improve write operations.

In embodiments of the present disclosure, a jump algorithm is employed in executing each write command (as compared to a constant write current) to further reduce the write failure rate in operation and improve yield.

In some embodiments, in the first step of the functional test, the "jump" mode of the writing algorithm will be turned off. In this step, based on the test results for a particular cell population, a regulated and optimized write/read current will be found and set.

Each MRAM cell has an optimal write current (Iopt). As shown in fig. 5A, the optimal write current for the MRAM cells in the array varies according to a gaussian distribution. In this embodiment, the unit of Iopt is μ a. When the write current deviates from the optimum write current, the error rate may increase exponentially. Because the optimal write current for a given magnetic random access memory cell may deviate significantly from the optimal write current for the array, applying the optimal write current for the array may not result in a change in the magnetic orientation of the given magnetic random access memory cell. Thus, the application of the write current may be performed multiple times in order to change the magnetic orientation. As shown in fig. 5B, applying the write current five times in a repeat provides an error rate that a given memory cell does not change orientation. The Y-axis in the graph shown in fig. 5B is logarithmic, and the X-axis is in units of μ a. Thus, it is readily understood that slight changes in Iopt can result in large differences in error rates.

In an embodiment of the present disclosure, multiple different write currents are applied to a given MRAM cell in a hopping scheme. As shown in fig. 5C, where the Y-axis is a logarithmic scale and the X-axis is in units of μ a, the use of the hopping scheme of the write current reduces the error rate by two orders of magnitude when the magnetic orientation of the MRAM is not changed compared to the repeated application of the same write current alone. FIG. 5D compares the error rates of a MRAM cell that applies a write current multiple times at a constant write current and a jump write current, where the current (I) is in units of μ A. The hopping scheme will be explained in more detail with reference to fig. 6.

The write current set by the first step of the functional test is the ensemble average Iopt. Within the cell population, there are MRAM cells whose Iopt differs significantly from the population average. When writing a current set in this way, the cells will have a high error rate.

In an embodiment of the present disclosure, a write process is used that applies a write current using a set of varying currents multiple times. This set of write currents will be centered on the global average set in the first step and cover the range of variation. In a second step of the functional test, such a variation range can be determined and set on the basis of an overall error rate analysis. Multiple attempts (multiple shots) will generate jumps by search patterns within this range. In field operation of an array of MRAM cells, the multiple-attempt "jump" scheme thus determined is used for the write process.

In an embodiment of the present disclosure, a write operation that applies a write current multiple times uses a set of varying write currents. The multiple write current application jumps through the search pattern as shown in fig. 6. With the jump write scheme, fewer devices fail. In a skip write scheme, the set of currents will be centered around the global average set in the first step and cover the range of variation. This range/step of variation can be determined and set based on an overall "Iopt" analysis in the second step of the functional test.

FIG. 6 illustrates a transition write current iteration process in accordance with an embodiment of the disclosure. The step size Δ I represents the difference in write current in μ a for a given write operation, while Δ I represents the total range in μ a between the highest and lowest write current values. In this embodiment, the first write current Wrt1 is the optimal write current for the array. The optimum write current for the array is predetermined during functional testing of the MRAM array. After application of the optimal write current Wrt1, a read current is applied to determine whether the magnetic orientation of the MRAM cell has changed. In some embodiments, the read current is fixed. The read current is determined during functional testing. In some embodiments, a fixed read current for a die, block, or array is set according to different design schemes.

An MRAM cell is acceptable and good if the magnetic orientation has been changed due to the application of an optimal write current. If the magnetic orientation of the MRAM cell has not changed, a second write current Wrt2 is applied. The value of the second write current Wrt2 is different from the value of the optimal write current Wrt 1. In some embodiments, the second write current Wrt2 is less than the optimal write current Wrt1, and in other embodiments, the second write current Wrt2 is greater than the optimal write current Wrt 1. After applying second write current Wrt2, a read current is applied to determine whether the magnetic orientation of the MRAM cell has changed. An MRAM cell is good if the magnetic orientation has been changed due to the application of second write current Wrt 2. If the magnetic orientation of the MRAM cell has not changed, a third write current Wrt 3 is applied. The value of the third write current Wrt 3 is different from the value of the optimal write current Wrt1 and different from the value of the second write current Wrt 2. The third write current Wrt 3 is less than or greater than the optimal write current Wrt1 according to the second write current Wrt 2. The third write current Wrt 3 is opposite to the second write current Wrt2 because the third write current Wrt 3 is greater than the optimal write current Wrt1 if the second write current Wrt2 is less than the optimal write current Wrt1 and the third write current Wrt 3 is less than the optimal write current Wrt1 if the second write current Wrt2 is greater than the optimal write current Wrt 1. In some embodiments, the magnitude Δ i of the difference between the second write current Wrt2 and the optimal write current Wrt1 is the same as the magnitude Δ i of the difference between the third write current Wrt 3 and the optimal write current Wrt 1.

After applying third write current Wrt 3, a read current is applied to determine whether the magnetic orientation of the MRAM cell has changed. An MRAM cell is good if the magnetic orientation has been changed due to the application of the third write current Wrt 3. If the magnetic orientation of the MRAM cell has not changed, a fourth write current Wrt 4 is applied. The value of the fourth write current Wrt 4 is different from the value of the optimal write current Wrt1, different from the value of the second write current Wrt2, and different from the value of the third write current Wrt 3. The fourth write current Wrt 4 is less than or greater than the optimal write current Wrt1 according to the third write current Wrt 3. The fourth write current Wrt 4 is opposite the third write current Wrt 3 because the fourth write current Wrt 4 is greater than the optimal write current Wrt1 if the third write current Wrt 3 is less than the optimal write current Wrt1 and the fourth write current Wrt 4 is less than the optimal write current Wrt1 if the third write current Wrt 3 is greater than the optimal write current Wrt 1. The magnitude 2 Δ i of the difference between the fourth write current Wrt 4 and the optimal write current Wrt1 is greater than the magnitude Δ i of the difference between the third write current Wrt 3 and the optimal write current Wrt1 and the magnitude Δ i of the difference between the second write current Wrt2 and the optimal write current Wrt 1.

After applying fourth write current Wrt 4, a read current is applied to determine whether the magnetic orientation of the MRAM cell has changed. An MRAM cell is good if the magnetic orientation has been changed due to the application of fourth write current Wrt 4. If the magnetic orientation of the MRAM cell has not changed, a fifth write current Wrt5 is applied. The value of the fifth write current Wrt5 is different from the value of the optimal write current Wrt1, different from the value of the second write current Wrt2, different from the value of the third write current Wrt 3, and different from the value of the fourth write current Wrt 4. The fifth write current Wrt5 is less than or greater than the optimal write current Wrt1 according to the fourth write current Wrt 4. The fifth write current Wrt5 is opposite the fourth write current Wrt 4 because the fifth write current Wrt5 is greater than the optimal write current Wrt1 if the fourth write current Wrt 4 is less than the optimal write current Wrt1, and the fifth write current Wrt5 is less than the optimal write current Wrt1 if the fourth write current Wrt 4 is greater than the optimal write current Wrt 1. The magnitude 2 Δ i of the difference between the fifth write current Wrt5 and the optimal write current Wrt1 is greater than the magnitude Δ i of the difference between the third write current Wrt 3 and the optimal write current Wrt1 and the magnitude Δ i of the difference between the second write current Wrt2 and the optimal write current Wrt 1. In some embodiments, the magnitude 2 Δ i of the difference between the fifth write current Wrt5 and the optimal write current Wrt1 is the same as the magnitude 2 Δ i of the difference between the fourth write current Wrt 4 and the optimal write current Wrt 1.

After applying fifth write current Wrt5, a read current is applied to determine whether the magnetic orientation of the MRAM cell has changed. An MRAM cell is good if the magnetic orientation has been changed due to the application of fifth write current Wrt 5. If the magnetic orientation of the MRAM cell has not changed, the MRAM cell is rejected. In this embodiment, 5 iterations of the write current are performed to determine whether the MRAM cell is good or rejected. In some embodiments, the difference between the fourth write current Wrt 4 and the fifth write current Wrt5 is the total range Δ I of magnitudes of write currents applied to the MRAM cell.

As shown in FIG. 6, the hopping scheme alternates between write currents having magnitudes less than and greater than the optimal write current, centered around the optimal write current Wrt1 for the MRAM array. The method according to the present disclosure is not limited to 5 iterations to determine if the MRAM is acceptable. In other embodiments, 3 or 4 iterations of applying the write current are performed. In other embodiments, more than 5 iterations of applying the write current are performed.

FIG. 7 is a flow chart illustrating a method 200 of writing an MRAM cell according to an embodiment of the disclosure. In operation S210, an optimal write current for the array of MRAM cells is determined. In operation S220, the optimal write current is applied to the MRAM cell. Next, in operation S230, a read current is applied to the MRAM cell. In operation S240, it is determined whether the magnetic orientation of the MRAM cell has changed. If the magnetic orientation is not changed, a different write current is applied to the MRAM cell and a read current is repeatedly applied, as shown in FIG. 7, in operation S250. If the magnetic orientation has not changed, then the application of different values of the write current is repeated until the magnetic orientation changes or a set number of iterations of applying different write currents are obtained. When the magnetic orientation is changed or a set number of iterations of applying different write currents are obtained, the application of the write current is stopped in operation S260.

In some embodiments, the method 200 includes iteratively repeating the applying the write current in operation S250 and the read current in operation S230 if the magnetic orientation of the first magnetic random access memory cell has not changed, wherein if the magnetic orientation of the first magnetic random access memory cell has changed, iteratively applying the write current and the read current is stopped, and the write current at each application of the write current is different from any other write current. In some embodiments, the write current applied at each iteration alternates between being greater than the optimal write current and being less than the optimal write current.

In some embodiments, each successive write current that is less than the optimal write current is less than a previous write current that is less than the optimal write current, and each successive write current that is greater than the optimal write current is greater than a previous write current that is greater than the optimal write current. For example, as shown in FIG. 6, in an embodiment, Iopt for the array of MRAM cells is determined to be 45 μ A. If the magnetic orientation of the MRAM cell is not changed after applying the write current of 45 μ A, a write current of 35 μ A is applied. If the magnetic orientation of the MRAM cell has not changed after applying the write current of 35 μ A, a third write current of 55 μ A is applied. If the magnetic orientation of the MRAM cell has not changed after applying the third write current of 55 μ A, a fourth write current of 25 μ A is applied. If the magnetic orientation of the MRAM-cell is not changed after applying the fourth write current of 25 μ A, a fifth write current of 65 μ A is applied. In this embodiment, the MRAM cell is rejected if 5 iterations are not sufficient to change the magnetic orientation. In this embodiment, the step size Δ I from each iteration of Iopt is 10 μ A, and the total range Δ I of write currents applied to the MRAM cells from the lowest write current value to the highest write current value is 40 μ A. As shown in fig. 6, in some embodiments, the write current applied after the application of the optimal write current alternates between a write current that is less than the optimal write current and a write current that is greater than the optimal write current. In an embodiment, the optimal write current is the midpoint of the values of all the alternating write currents.

FIG. 8 illustrates a portion of a circuit 300 for performing a transition write scheme in accordance with an embodiment of the present disclosure. In some embodiments, Iopt for a chip, array, module, or block of MRAM cells is determined during functional testing of the chip, array, module, or block of MRAM cells. In some embodiments, a Gaussian distribution of Iopt is determined by functional testing. The current source 310 applies a write current to the array of MRAM cells, the block of MRAM cells, or the MRAM cells. Current source 320 applies a read current to verify whether the MRAM cell(s) change magnetic orientation. In some embodiments, the same current source applies both the write current and the read current. In some embodiments, a comparator or sense amplifier 330 is included in the circuit 300. If the magnetic orientation changes, the writing process is stopped. If the magnetic orientation of the MRAM cell has not changed (write failed), the level shifter 340 changes the current value. The controller 350 controls the current sources 310, 320 and the level shifter 340. In some embodiments, Iopt, the magnitude of the current step Δ I for each iteration of changing the write current, the total range of current change Δ I for all iterations, and the number of iterations are determined during functional testing of the array, and the controller sets these values in circuit 300.

Fig. 9 is a flow chart illustrating a method 400 of determining an optimal write current for an array of MRAM cells in accordance with an embodiment of the present disclosure. In operation S410, a write current is applied to one of the plurality of MRAM cells. Next, a read current is applied to the MRAM cell in operation S420. In operation S430, it is determined whether the magnetic orientation of the MRAM cell has changed. As shown in fig. 9, if the magnetic orientation is not changed, a different write current is applied to the MRAM cell and a read current is repeatedly applied in operation S440. If the magnetic orientation is not changed, the application of different values of the write current is repeated until the magnetic orientation is changed. When the magnetic orientation has changed, in operation S450, a value of a write current that causes the magnetic orientation of the MRAM cell to change is determined. Then, the following steps are repeated in operation S460: applying a write current S410, applying a read current S420, determining whether the magnetic orientation of the MRAM cell has changed S430, and applying a different write current to the MRAM cell if the magnetic orientation of the MRAM cell has not changed S440. Next, in operation S470, it is determined whether the magnetic orientation of each MRAM cell of the plurality of MRAM cells is changed. If not all of the plurality of MRAM cells have changed their magnetic orientation, the step of applying the different write currents is repeated. The initial write current applied is the write current at the low end of the predicted range of suitable write currents. If the initial write current does not result in a change in magnetic orientation, the magnitude of the subsequently applied write current is increased in a stepwise manner until the magnetic orientation of the MRAM cell changes. If the magnetic orientation of each of the MRAM cells has changed, an optimal write current is determined based on the write current to change the magnetic orientation of each of the plurality of MRAM cells in operation S480. In some embodiments, the optimal write current is an average of the write currents to change the magnetic orientation of each of the plurality of MRAM cells.

In some embodiments, a plurality of parameters determined during functional testing are programmed into the MRAM array circuit by blowing fuses or antifuses in the circuit, wherein the plurality of parameters includes Iopt, a magnitude of a current step Δ I for each iteration of changing the write current, a total range of current changes Δ I for all iterations, and a number of iterations. Burn-in sets the parameters permanently. In some embodiments, the parameters for each block in the array of MRAM cells are different. Thus, each block in the array of MRAM cells can be optimized. For example, fig. 10 shows an antifuse block incorporating programmable circuitry for setting a step size for iterative write current changes and a range of write currents, in accordance with an embodiment of the present disclosure. As shown in FIG. 10, the programmable multiplexer inputs blow the appropriate antifuses in the antifuse block to set the parameters of the MRAM array circuit. For example, after the functional test determines the Iopt for a chip, array, module, or block of MRAM cells, the Iopt for the chip, array, module, or block of MRAM cells is burned in. Functional testing and burn-in may be performed on any size grouping of MRAM cells.

Fig. 11 illustrates a circuit such as functional test circuit 500 according to some embodiments of the present disclosure. The functional test circuit 500 includes an array 510 that includes a plurality of blocks 520. Each block 520 includes a plurality of magnetic random access memory cells. The functional test circuit 500 includes a current source 530 configured to provide a plurality of different write currents and read currents to each of the magnetic random access memory cells in the block 520 of the array 510. The functional test circuit 500 according to some embodiments further comprises a controller 540, the controller 540 configured to control the application of a different write current from the current source 530 to each of the magnetic random access memory cells in each of the regions 520 and to determine whether the magnetic orientation of each of the magnetic random access memory cells has changed in response to each application of the write current. The controller 540 is further configured to control the current source 530 such that the write current per application alternates between being greater than and less than the first write current applied to each magnetic random access memory cell to stop applying the write current to each magnetic random access memory cell when it is determined that the magnetic orientation of each magnetic random access memory cell has changed and to determine an average of the write currents that result in the change in the magnetic orientation of the magnetic random access memory cells in each block 520 of the array 510.

In some embodiments, the controller 540 is configured to set Iopt, the magnitude of the current step Δ I for each iteration of changing the write current, the total range of current change Δ I for all iterations, and the number of iterations in the circuit 500. In some embodiments, the controller 540 is configured to isolate certain MRAM cells in the array from the plurality of blocks 520 by blowing fuses or antifuses.

Using the zig-zag jump writing pattern of the present disclosure, the time for successful writing will beShorter. In addition, fewer devices fail with this new "jump" write scheme. In some embodiments, the number of failed MRAM cells obtained by using the jump writing scheme of the present disclosure is reduced by two orders of magnitude. In some embodiments, the failure rate of MRAM cells is reduced to 1 × 10 using the jump writing scheme of the present disclosure-6Or smaller. Accordingly, the present disclosure improves the yield of the semiconductor device.

An embodiment of the present disclosure is a method of fabricating an array of magnetic random access memory cells, including writing to the magnetic random access memory cells. Writing to a magnetic random access memory cell includes: determining an optimal write current for the array of magnetic random access memory cells; the optimal write current is applied to a first magnetic random access memory cell in the array. Applying a first read current to the first magnetic random access memory cell to determine whether a magnetic orientation of the first magnetic random access memory cell has changed in response to applying the optimal write current. Applying a second write current to the first magnetic random access memory cell when the magnetic orientation of the first magnetic random access memory cell is not changed. The second write current is different from the optimal write current. Applying a second read current to the first magnetic random access memory cell to determine whether a magnetic orientation of the first magnetic random access memory cell has changed in response to applying the second read current. In an embodiment, the method further comprises: applying a third write current to the first magnetic random access memory cell when the magnetic orientation of the first magnetic random access memory cell is not changed after applying the second write current, wherein the third write current is different from the optimal write current and the second write current; and applying a third read current to the first magnetic random access memory cell to determine whether the magnetic orientation of the first magnetic random access memory cell has changed in response to applying the third write current. In an embodiment, the second write current is greater than the optimal write current and the third write current is less than the optimal write current. In an embodiment, the second write current is less than the optimal write current and the third write current is greater than the optimal write current. In an embodiment, a method comprises: iteratively repeating applying a write current and a read current when the magnetic orientation of the first magnetic random access memory cell has not changed, wherein iteratively applying the write current and the read current is stopped when the magnetic orientation of the first magnetic random access memory cell has changed, and wherein the write current at each application of the write current is different from any other write current. In an embodiment, the write current applied at each iteration alternates between being greater than the optimal write current and being less than the optimal write current. In an embodiment, each successive write current smaller than the optimal write current is smaller than a previous write current smaller than the optimal write current, and each successive write current larger than the optimal write current is larger than a previous write current larger than the optimal write current. In an embodiment, the write current applied after applying the optimal write current alternates between a write current smaller than the optimal write current and a write current larger than the optimal write current. In an embodiment, the optimal write current is at the midpoint of the values of all alternating write currents.

Another embodiment of the present disclosure is a method of manufacturing an array of magnetic random access memory cells, comprising determining an optimal write current for the array of magnetic random access memory cells. Determining an optimal write current for the array of magnetic random access memory cells comprises: (a) applying a first write current to one of a plurality of magnetic random access memory cells in the array of magnetic random access memory cells; and (b) applying a first read current to one of the plurality of magnetic random access memory cells to determine whether a magnetic orientation of the one of the plurality of magnetic random access memory cells has changed in response to the applying the write current. In operation (c), a second write current is applied to one of the plurality of magnetic random access memory cells when the magnetic orientation of the one of the plurality of magnetic random access memory cells is not changed, wherein the second write current is different from the optimal write current. Then in operation (d), a second read current is applied to one of the plurality of magnetic random access memory cells to determine whether a magnetic orientation of the one of the plurality of magnetic random access memory cells has changed in response to applying the second write current, wherein the second read current has the same value as the first read current. Next, in operation (e), when the magnetic orientation of one of the plurality of magnetic random access memory cells is not changed after the second write current is applied, applying a third write current to the one of the plurality of magnetic random access memory cells, wherein the third write current is different from the optimal write current and the second write current. In operation (f), a third read current is applied to one of the plurality of magnetic random access memory cells to determine whether a magnetic orientation of the one of the plurality of magnetic random access memory cells has changed in response to applying the third write current, wherein the third read current has a value that is the same as the first and second read currents. Then, in operation (g), iteratively repeating applying a write current and a read current when the magnetic orientation of one of the plurality of magnetic random access memory cells has not changed, wherein iteratively repeating applying a write current and a read current stops when the magnetic orientation of one of the plurality of magnetic random access memory cells has changed, wherein the write current at each application of the write current is different from any other write current, and wherein the first write current has a first magnitude and the magnitude of the subsequently applied write current increases in a stepwise manner. Subsequently, in operation (h), a value of a write current that causes a change in a magnetic orientation of the magnetic random access memory cell is determined. In operation (i), operations (a) through (h) are repeated for each of the plurality of magnetic random access memory cells in the array of magnetic random access memory cells. In operation (j), the optimal write current is determined based on the determined write current for each of the plurality of magnetic random access memory cells. In an embodiment, the optimal write current for each of the plurality of magnetic random access memory cells is an average of the write currents that cause the magnetic orientation of the magnetic random access memory cell to change. In an embodiment, a method comprises: writing to a magnetic random access memory cell in the array of magnetic random access memory cells, wherein writing to the magnetic random access memory cell comprises: applying the optimal write current to selected magnetic random access memory cells in the array; applying a read current of a write cell to the selected magnetic random access memory cell to determine whether a magnetic orientation of the selected magnetic random access memory cell has changed in response to applying the optimal write current; applying a write current of a write unit to the selected magnetic random access memory cell when the magnetic orientation of the selected magnetic random access memory cell has not changed in response to applying the optimal write current; and iteratively repeating applying the write current of the write unit and the read current of the write unit when the magnetic orientation of the selected magnetic random access memory cell is not changed. Stopping the iterative application of the write current of the write unit and the read current of the write unit when the magnetic orientation of the selected magnetic random access memory cell has changed, and the write current of the write unit at each application of the write current of the write unit is different from the write current of any other write unit. Then, after iteratively applying the write current of the write unit a set number of times, if the magnetic orientation of the selected magnetic random access memory cell is not changed, the selected magnetic random access memory cell is isolated. In an embodiment, the selected magnetic random access memory cell is isolated by blowing a fuse or an antifuse. In an embodiment, a magnitude of a write current of the write unit of a first application is greater than a magnitude of the optimal write current, and a magnitude of a write current of the write unit of a second application is less than the magnitude of the optimal write current. In an embodiment, a magnitude of a write current of the write unit of a first application is smaller than a magnitude of the optimal write current, and a magnitude of a write current of the write unit of a second application is larger than the magnitude of the optimal write current. In an embodiment, the magnitude of the write current of the write unit applied at each iteration alternates between being greater than the optimal write current and being less than the optimal write current. In an embodiment, the write current of the write cell applied after applying the optimal write current alternates between a write current of a write cell smaller than the optimal write current and a write current of a write cell larger than the optimal write current. In an embodiment, the write currents of the plurality of write cells applied after the application of the optimal write current alternate between a write current of a write cell smaller than the optimal write current and a write current of a write cell larger than the optimal write current, the write current of each successive write cell smaller than the optimal write current is smaller than the write current of a previous write cell smaller than the optimal write current, and the write current of each successive write cell larger than the optimal write current is larger than the write current of a previous write cell larger than the optimal write current.

Another embodiment of the present disclosure is a method of writing a magnetic random access memory cell, comprising: a first write current is applied to the first magnetic random access memory cell. Determining whether a magnetic orientation of the first magnetic random access memory cell has changed in response to the applying the first write current. Applying a second write current to the first magnetic random access memory cell when it is confirmed that the magnetic orientation of the first magnetic random access memory cell has not changed, wherein the second write current is different from the first write current. Determining whether a magnetic orientation of the first magnetic random access memory cell has changed in response to the applying the second write current. Applying a third write current to the first MRAM cell after confirming that the magnetic orientation of the first MRAM cell has not changed after applying the second write current, wherein the third write current is different from the first write current and the second write current. Determining whether a magnetic orientation of the first magnetic random access memory cell has changed in response to the applying the third write current. In an embodiment, the method comprises repeatedly applying said write current until the magnetic orientation of said first magnetic random access memory cell has changed or a certain number of applications of the write current is achieved, wherein the value of the write current applied during each application of the write current is different.

An embodiment of the present disclosure is a method of writing to a magnetic random access memory cell, comprising: the method includes iteratively applying a plurality of write currents to the first magnetic random access memory cell, and determining whether a magnetic orientation of the first magnetic random access memory cell has changed in response to each application of the write currents. The value of the write current applied during each application of the write current is different. The write current applied at each iteration alternates between being greater than and less than a first write current applied to a first magnetic random access memory cell. The iterative application of the write current is stopped when it is determined that the magnetic orientation of the first magnetic random access memory cell has changed.

Another embodiment of the disclosure is a method of writing to a plurality of magnetic random access memory cells in an array of magnetic random access memory cells, the method comprising: iteratively applying a plurality of write currents to a first magnetic random access memory cell in the array, and determining whether a magnetic orientation of the first magnetic random access memory cell has changed in response to each application of a write current. The value of the write current applied during each application of the write current is different. The write current applied at each iteration alternates between being greater than and less than the first write current applied to the first magnetic random access memory cell. Stopping the iterative application of the write current when it is determined that the magnetic orientation of the first magnetic random access memory cell has changed or the application of the write current to the first magnetic random access memory cell is performed a set number of times. A plurality of write currents are iteratively applied to a second magnetic random access memory cell in the array and a determination is made whether a magnetic orientation of the second magnetic random access memory cell has been changed in response to each application of a write current. The value of the write current applied during each application of the write current is different. The application of the write current at each iteration alternates between being greater than and less than the first write current applied to the second magnetic random access memory cell. The iterative application of the write current is stopped when it is determined that the magnetic orientation of the second magnetic random access memory cell has changed or the application of the write current to the second magnetic random access memory cell is performed a set number of times.

Another embodiment of the present disclosure is a method that includes applying a first write current to a first magnetic random access memory cell, wherein the first magnetic random access memory cell is located within a first block of magnetic random access memory cells in an array of magnetic random access memory cells. Determining whether a magnetic orientation of the first magnetic random access memory cell has changed in response to said applying the first write current. Applying a second write current to the first magnetic random access memory cell if the magnetic orientation of the first magnetic random access memory cell is not changed, wherein the second write current is different from the first write current. Determining whether a magnetic orientation of the first magnetic random access memory cell has changed in response to said applying the second write current. Applying a third write current to the first magnetic random access memory cell if the magnetic orientation of the first magnetic random access memory cell has not changed after said applying the second write current, wherein the third write current is different from the first write current and the second write current. Determining whether the magnetic orientation of the first magnetic random access memory cell has changed in response to said applying the third write current. The applying of the write current is repeated until the magnetic orientation of the first magnetic random access memory cell changes or a certain number of times of the applying of the write current is realized, wherein the value of the applied write current during each applying of the write current is different. A value of a write current that causes a change in a magnetic orientation of the first magnetic random access memory cell is determined. The first write current is repeatedly applied to each of a plurality of magnetic random access memory cells within a first block of magnetic random access memory cells in the array of magnetic random access memory cells. In response to repeatedly applying the first write current to each of the plurality of magnetic random access memory cells in the first block of magnetic random access memory cells, determining whether a magnetic orientation of each of the plurality of magnetic random access memory cells has changed. The second write current is repeatedly applied for each of the plurality of magnetic random access memory cells in the first block without a change in magnetic orientation, wherein the second write current is different from the first write current. For each magnetic random access memory cell to which the second write current is applied, determining whether the magnetic orientation of each magnetic random access memory cell has changed in response to repeatedly applying the second write current. After applying the second write current, repeatedly applying a third write current to each of the plurality of magnetic random access memory cells in the first block that do not have a change in magnetic orientation, wherein the third write current is different from the first write current and the second write current. For each of the plurality of magnetic random access memory cells to which the third write current is applied, determining whether a magnetic orientation of each of the plurality of magnetic random access memory cells has changed in response to repeatedly applying the third write current. The application of the write current is repeated until the magnetic orientation of each magnetic random access memory cell has changed or a certain number of write current applications are achieved. The value of the write current applied during each application of the write current to a particular magnetic random access memory cell is different. A value of a write current that causes a change in magnetic orientation of each magnetic random access memory cell in the first block is determined. An average of values of a plurality of write currents that cause a change in magnetic orientation of magnetic random access memory cells in the first block is determined. In an embodiment, the average write current for the first block is set for the first block during a burn-in operation of the array. In an embodiment, the array includes a plurality of blocks of magnetic random access memory cells. In an embodiment, the method is repeated for each block of magnetic random access memory cells in the array. In an embodiment, the magnetic random access memory cells of each of the plurality of blocks of magnetic random access memory cells have a different average write current. In an embodiment, the MRAM cells that do not change magnetic orientation after a set number of applications of write current are isolated from the corresponding block of MRAM cells by blowing a fuse or an antifuse. In some embodiments, a block of random access memory cells including greater than a set number of isolated random access memory cells is isolated from the array by blowing fuses or antifuses.

Another embodiment of the present disclosure is a circuit comprising a current source configured to apply a plurality of different write currents and read currents to a magnetic random access memory cell in an array of magnetic random access memory cells. The circuit includes a controller configured to determine an optimal write current for the array of magnetic random access memory cells, determine whether a magnetic orientation of the magnetic random access memory cells has changed in response to the applying a plurality of different write currents, and control the applying of the write current from the current source to the magnetic random access memory cells.

Another embodiment of the present disclosure is a circuit comprising a current source configured to apply a plurality of different write currents to a magnetic random access memory cell. The circuit includes a controller configured to control iterative application of a plurality of write currents from a current source to the magnetic random access memory cell and to determine whether a magnetic orientation of the magnetic random access memory cell has changed in response to each application of a write current. The controller is further configured to control the current source such that the write current applied each time alternates between being greater than and less than a first write current applied to the magnetic random access memory cell, and to cease applying the write current when it is determined that the magnetic orientation of the first magnetic random access memory cell has changed.

Another embodiment of the present disclosure is a functional test circuit comprising an array comprising a plurality of blocks, each block comprising a plurality of magnetic random access memory cells. The circuit includes a current source configured to provide a plurality of different write currents and read currents to each magnetic random access memory cell. The circuit includes a controller configured to control application of a plurality of different write currents from the current source to each magnetic random access memory cell and to determine whether a magnetic orientation of each magnetic random access memory cell has changed in response to each application of the write current. The controller is further configured to: controlling the current source such that the write current per application alternates between being greater than and less than the first write current applied to each magnetic random access memory cell; stopping applying the write current to each magnetic random access memory cell when it is determined that the magnetic orientation of each magnetic random access memory cell has changed; and determining an average of a plurality of write currents that result in a change in magnetic orientation of the magnetic random access memory cells in each block of the array.

It is to be understood that not all advantages need be discussed herein, that no particular advantage of all embodiments or examples is required, and that other embodiments or examples may provide a plurality of different advantages.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

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