阅读说明：本技术 存储器控制器中的刷新方案 (Refresh scheme in a memory controller ) 是由 赵亮 姚于斌 于 2018-07-16 设计创作，主要内容包括：本发明涉及存储器控制器中的刷新方案。在一种形式中,存储器控制器包括命令队列、仲裁器、刷新逻辑电路和最终仲裁器。所述命令队列接收并存储对存储器的存储器访问请求。所述仲裁器根据第一类型的访问和第二类型的访问来从所述命令队列选择性地选取访问。所述第一类型的访问和所述第二类型的访问对应于所述存储器中的对应存储器访问的不同页状态。所述刷新逻辑电路生成对所述存储器的存储体的刷新命令,并且为所述刷新命令提供优先级指示符,所述优先级指示符的值根据待处理刷新的数目来设置。所述最终仲裁器基于所述优先级指示符相对于所述第一类型的访问和所述第二类型的访问的存储器访问请求选择性地排序所述刷新命令。(The present invention relates to refresh schemes in memory controllers. In one form a memory controller includes a command queue, an arbiter, refresh logic, and a final arbiter. The command queue receives and stores memory access requests to memory. The arbiter selectively chooses an access from the command queue based on a first type of access and a second type of access. The first type of access and the second type of access correspond to different page states of corresponding memory accesses in the memory. The refresh logic generates a refresh command to a bank of the memory and provides the refresh command with a priority indicator whose value is set according to a number of pending refreshes. The final arbiter selectively orders the refresh commands relative to memory access requests of the first type of access and the second type of access based on the priority indicators.)

1. A memory controller, comprising:

a command queue for receiving and storing memory access requests to the memory;

an arbiter to selectively choose accesses from the command queue according to a first type of access and a second type of access, wherein the first type of access and the second type of access correspond to different page states of corresponding memory accesses in the memory;

refresh logic for generating a refresh command to a bank of the memory and providing a priority indicator to the refresh command, a value of the priority indicator being set according to a number of pending refreshes; and

a final arbiter to selectively order the refresh command relative to memory access requests of the first type of access and the second type of access based on the priority indicator.

2. The memory controller of claim 1, wherein the refresh logic circuit:

assigning the priority indicator to one of a first priority state and a second priority state; and

the final arbiter promotes the refresh command to be between the first type of access and the second type of access in response to the first priority state.

3. The memory controller of claim 2, wherein the final arbiter further promotes the refresh command above the first type of access and the second type of access in response to the second priority state.

4. The memory controller of claim 2, wherein the refresh logic circuit comprises:

a refresh counter for counting the number of per bank refreshes to be processed; and a comparator coupled to the refresh counter that provides the first priority state for the refresh command if the refresh counter exceeds a predetermined threshold.

5. The memory controller of claim 4, wherein the refresh logic circuit is further to raise the priority indicator of pending refresh commands when the refresh counter is between a lower threshold and an upper threshold based on a periodic time period.

6. The memory controller of claim 5, wherein the periodic time period is a derivative of a predetermined refresh interval and a total number of banks assigned to the memory controller.

7. The memory controller of claim 1, wherein the refresh logic circuit assigns the priority indicator further based on a programmable counter, and the programmable counter tracks a number of pending refresh commands.

8. The memory controller of claim 7, wherein the refresh logic circuit further raises the priority indicator of pending refresh commands when the programmable counter is above an emergency refresh count threshold.

9. The memory controller of claim 1, wherein the first type of access is not a page hit and the second type of access is a page hit.

10. The memory controller of claim 1, wherein the arbiter comprises a plurality of sub-arbiters for selectively choosing accesses based on sub-arbitration, wherein one sub-arbitration is a page hit and each other sub-arbitration is not a page hit.

11. The memory controller of claim 1, wherein in response to receiving priority indicators for more than one bank at a time, the final arbiter downgrades the priority indicator for the bank of the memory that is the closest recipient of the refresh command to be lower than the bank of the memory that is the earliest recipient of the refresh command.

12. The memory controller of claim 1, wherein the memory controller is adapted to interface to a synchronous graphics random access memory capable of supporting every two bank refreshes.

13. The memory controller of claim 12, wherein the refresh logic circuit further raises the priority indicator of pending refresh commands for a pair of banks when the priority indicator is a first priority state and a refresh timer is above a refresh timing interval.

14. The memory controller of claim 13, wherein the refresh logic circuit is further to raise the priority indicator of pending refresh commands to a second priority state for the pair of memory banks when the programmable counter is above an emergency refresh count threshold and both of the pair of memory banks have a first type of access.

15. A data processing system, comprising:

a memory access agent to provide memory access requests to a memory;

a memory system coupled to the memory access agent; and

a memory controller coupled to the memory system and the memory access agent, the memory controller comprising:

a command queue to store memory access commands received from the memory access agent;

an arbiter to selectively choose a memory access from the command queue according to a first type of access and a second type of access, wherein each type of access corresponds to a different page state of a bank in the memory; and

a final arbiter that arbitrates based on input received from refresh logic that generates refresh commands to the banks of the memory and provides priority indicators to the refresh commands, the priority indicators having values set according to a number of pending refreshes to selectively order the refresh commands relative to a first type of access and a second type of access.

16. The data processing system of claim 15, wherein the memory controller:

assigning the priority indicator to one of a first priority state and a second priority state; and

raising the refresh command to be between the first type of access and the second type of access in response to the first priority state.

17. The data processing system of claim 16, wherein:

the memory controller further assigns the priority indicator for the first priority state based in part on a clock;

the clock is used to track refresh intervals; and

the memory controller determines an intermediate refresh time interval based on a refresh time interval and a total number of memory banks assigned to the memory controller.

18. The data processing system of claim 17, wherein the intermediate refresh time interval is a time period less than the refresh time interval.

19. The data processing system of claim 17, wherein in response to the intermediate refresh time interval, the memory controller generates the refresh commands to the memory banks at a frequency higher than the refresh interval.

20. The data processing system of claim 15, wherein the memory controller is further to:

assigning the priority indicator based on a predetermined threshold of a refresh counter, wherein the refresh counter counts a number of per bank refreshes pending in the memory; and

raising the priority indicator of pending refresh commands based on a periodic time period when the refresh counter is between a lower threshold and an upper threshold.

21. The data processing system of claim 15, wherein the memory controller assigns the priority indicator for a second priority state further based on a programmable counter.

22. The data processing system of claim 21, wherein the memory controller promotes the priority indicator of the refresh command above the first type of access and the second type of access in response to the second priority state.

23. The data processing system of claim 21, wherein the memory controller prevents opening of a corresponding bank of memory in response to assertion of the second priority state.

24. The data processing system of claim 15, wherein the arbiter comprises a plurality of sub-arbiters, and the plurality of sub-arbiters are to selectively choose accesses based on sub-arbiters, wherein one sub-arbitration is a page hit and each other sub-arbitration is not a page hit.

25. The data processing system of claim 15, wherein the memory access agent comprises:

a central processing unit core;

a graphics processing unit core; and

a data fabric to interconnect the central processing unit core and the graphics processing unit core to the memory controller.

26. The data processing system of claim 15, wherein the memory is a high bandwidth memory.

27. A method for managing refreshes of a memory in a memory system via a memory controller, the method comprising:

receiving a plurality of memory access requests;

storing the plurality of memory access requests in a command queue; and

selectively selecting a memory access request from the command queue according to a first type of access and a second type of access, the first type of access and the second type of access corresponding to different page states of a corresponding memory access in the memory;

generating a refresh command to a bank of the memory and providing a priority indicator for the refresh command; and

selectively ordering the refresh command relative to memory access requests of the first type of access and the second type of access based on the priority indicator.

28. The method of claim 27, wherein providing the priority indicator for the refresh command further comprises:

assigning the priority indicator to one of a first priority state and a second priority state;

raising the refresh command to be between the first type of access and the second type of access in response to the first priority state; and

raising the refresh command above the first type of access and the second type of access in response to the second priority state.

29. The method of claim 27, further comprising assigning the priority indicator based on a predetermined threshold of a refresh counter, wherein the refresh counter counts a number of per bank refreshes pending in the memory.

30. The method of claim 29, further comprising raising the priority indicator of pending refresh commands based on a periodic time period when the refresh counter is between a lower threshold and an upper threshold.

31. The method of claim 30, wherein the periodic time period is a derivative of a predetermined refresh interval and a total number of banks assigned to the memory controller.

32. The method of claim 27, further comprising assigning the priority indicator based on a programmable counter, and the programmable counter tracks a number of refresh commands that are scheduled and outstanding.

33. The method of claim 32, further comprising raising the priority indicator of pending refresh commands when the programmable counter is above an emergency refresh count threshold.

34. The method of claim 27, wherein the first type of access is not a page hit and the second type of access is a page hit.

35. The method of claim 27, further comprising selectively choosing an access based on sub-arbiters, wherein an arbiter comprises a plurality of sub-arbiters, and one sub-arbiter is a page hit while each other sub-arbiter is not a page hit.

36. The method of claim 27, wherein the refresh command is for a selected bank.

Technical Field

The present invention relates generally to the field of computers, and more particularly to refresh schemes in memory controllers.

Background

Computer systems typically use inexpensive and high density Dynamic Random Access Memory (DRAM) chips for main memory. Most DRAM chips sold today are compatible with various Double Data Rate (DDR) DRAM standards promulgated by the Joint Electron Device Engineering Council (JEDEC). DRAM chips are not persistent memory devices. Thus, during normal operation of a computer system, DRAM chips require periodic memory refreshes for data retention. Memory refresh is a background maintenance process required during operation of semiconductor DRAM. Each bit of memory data is stored due to the presence or absence of charge on a small capacitor forming a DRAM chip. Over time, the charge on the capacitor leaks away and the stored data will be lost without a memory refresh. To prevent data loss, an external circuit sends a command to cause the memory to periodically read a row and rewrite the row, thereby restoring the charge on the capacitors of the memory cells of the row to the original charge level. When a refresh occurs, the memory is not available for normal read and write operations.

Attempts have been made to adjust the impact of refresh operations on DRAM bandwidth. Known memory controllers employ one of two processes to refresh the DRAM. In a first example, the memory controller waits until no other access to the memory is pending, and then the memory controller provides a refresh to the memory. These are called temporary refreshes. In another example, when the memory controller has waited too long and the memory is in urgent need of refresh, then the memory controller provides an emergency refresh. Each of the above examples may cause memory transactions to stall, thus causing memory performance to degrade.

Disclosure of Invention

In one aspect, a memory controller is provided, which may include: a command queue for receiving and storing memory access requests to the memory; an arbiter to selectively choose accesses from the command queue according to a first type of access and a second type of access, wherein the first type of access and the second type of access correspond to different page states of corresponding memory accesses in the memory; refresh logic for generating a refresh command to a bank of the memory and providing a priority indicator to the refresh command, a value of the priority indicator being set according to a number of pending refreshes; and a final arbiter for selectively ordering the refresh commands based on the priority indicators relative to memory access requests for the first type of access and the second type of access.

In another aspect, a data processing system is provided, which may include: a memory access agent to provide memory access requests to a memory; a memory system coupled to the memory access agent; and a memory controller coupled to the memory system and the memory access agent, the memory controller comprising: a command queue to store memory access commands received from the memory access agent; an arbiter to selectively choose a memory access from the command queue according to a first type of access and a second type of access, wherein each type of access corresponds to a different page state of a bank in the memory; and a final arbiter that arbitrates based on inputs received from refresh logic that generates refresh commands to the banks of the memory and provides priority indicators to the refresh commands, the priority indicators having values set according to a number of pending refreshes to selectively order the refresh commands with respect to a first type of access and a second type of access.

In yet another aspect, a method for managing refreshes of a memory in a memory system via a memory controller is provided, which may include: receiving a plurality of memory access requests; storing the plurality of memory access requests in a command queue; and selectively selecting a memory access request from the command queue according to a first type of access and a second type of access, the first type of access and the second type of access corresponding to different page states of a corresponding memory access in the memory; generating a refresh command to a bank of the memory and providing a priority indicator for the refresh command; and selectively ordering the refresh command with respect to memory access requests for the first type of access and the second type of access based on the priority indicator.