阅读说明：本技术 处理中断优先级的电路系统 (Circuit system for processing interrupt priority ) 是由 费晓行 费善健 于 2018-07-20 设计创作，主要内容包括：一种处理中断优先级的电路系统,电路系统如一片上系统(SoC),在其中运行的中断优先级处理方法中,片上系统中的处理器在执行工作时,当接收到访问一临界区的高优先级中断时,系统设计高优先级中断为恒开,但禁止访问临界区,如此,即设置一低优先级中断,以访问并处理高优先级中断所要访问的数据,当返回低优先级中断后,处理器将判断是否唤醒之前高优先级中断未处理完的工作,若尚有工作,即由处理器以一任务继续处理高优先级中断未处理完的工作。所披露的电路系统可以在保持有关中断的特性外,还保持系统处理重要任务的实时性。(A circuit system for handling interrupt priority, such as system on chip (SoC), in which the interrupt priority handling method is run, when a processor in the system on chip receives a high priority interrupt to access critical area, the system designs the high priority interrupt as constant, but prohibits access to the critical area, such that low priority interrupt is set to access and handle data to be accessed by the high priority interrupt, and when the low priority interrupt is returned, the processor will determine whether to wake up the previous high priority interrupt pending work, and if there is still work, the processor will continue to handle the high priority interrupt pending work with task.)

Circuitry of , comprising:

processor and or multiple subsystems, the processor being configured to perform a interrupt priority handling method including setting high priority interrupts constant to handle any real-time tasks.

2. The circuitry of claim 1, wherein the interrupt priority processing method performed by the processor of the circuitry further comprises:

receiving the high priority interrupt while the processor is performing work, the high priority interrupt being operative to access critical sections;

setting a low priority interrupt to access and process data of the critical section to be accessed by the high priority interrupt;

after returning to the low priority interrupt, the processor judges whether to awaken the unprocessed work of the high priority interrupt; and

the unprocessed work of the high priority interrupt is continuously processed by the processor.

3. The circuitry of claim 2, wherein the circuitry is system on a chip.

4. The circuitry of claim 2, wherein the or more subsystems issue the high priority interrupt or the low priority interrupt to the processor.

5. The circuitry of claim 2, wherein the circuitry runs on an computer system, and the interrupt priority handling method runs on a real-time operating system.

6. The circuitry of claim 2, wherein the work originally performed by the processor is tasks that do not require interrupt processing.

7. The circuitry of claim 2, wherein the work originally performed by the processor is a task of the low priority interrupt.

8. The circuitry of claim 2, wherein pre-operation is included to set the high priority interrupt to an interrupt with straight-on, but the processing function of the high priority interrupt prohibits access to the critical section.

9. The circuitry defined in claim 8 wherein the handling function of the low priority interrupt is set to allow access to the critical section.

10. The circuitry of claim 9, wherein the step of setting the low priority interrupt sets an flag state or a bit state to signal the low priority interrupt.

Technical Field

interrupt handling circuits, especially systems on chip with interrupt priority mechanism are proposed to achieve some high priority interrupts that are always on during processing and maintain the interrupt characteristics.

Background

A System on Chip (SoC) is a single Chip of kinds of systems integrating multiple functions, and is widely used by Chip designers, and when designing a System on Chip, a plurality of subsystems (subsystems) or subsystems of subsystems are provided, and the subsystems communicate with each other through a System bus (bus).

Because subsystems in a system-on-chip share common data with each other, conventionally, the subsystems communicate with each other by means of a trigger (trigger) interrupt (interrupt) as a mechanism for controlling data access, the interrupt is handled by an interrupt controller (interrupt controller) of a Central Processing Unit (CPU) in the system, the interrupt controller is used to connect various subsystems and the CPU, and when subsystems generate an interrupt, a signal is forwarded by the interrupt controller to reach the CPU.

During operation, the subsystem generates an Interrupt signal to the cpu, and after receiving the Interrupt signal, an Interrupt controller of the cpu determines which subsystem triggered the Interrupt, and then processes an Interrupt Service Routine (ISR), so that the subsystems can share data without collision.

Fig. 1 shows a circuit block diagram of a conventional system on chip.

on-chip systems in the electronic system include a central processor 110, in which there is an interrupt controller 115 for managing interrupt signals, other shared resources are listed schematically as a memory 111 and a sensor 112, which transmit information via a bus 10. the system on-chip is provided with a plurality of subsystems 101-105, and possibly subsystems of the subsystems, the subsystems 101-105 are modules in the system on-chip, and generate interrupt signals when the shared resources are needed, and the interrupt controller 115 receives the interrupt signals of a certain subsystem and transmits the interrupt signals to other subsystems, thereby achieving the purpose of interrupt management.

In most processes of processing real-time information, in the prior art, a method of disabling interrupt (disabled interrupt) is mostly used to implement setting of a critical section, and when programs are executing their critical section codes on a processor, another program is prevented from reentering the critical section to access, and the simplest and most direct method is to prohibit interrupt occurrence, which is called as "disable interrupt" (disabled interrupt).

However, this method also turns off the high-priority interrupt while prohibiting the low-priority interrupt, which greatly affects the real-time performance of the system processing.

Disclosure of Invention

The invention provides circuit systems for processing interrupt priority, such as circuit systems in a system on chip (SoC), aiming to utilize the characteristic of the interrupt priority of the SoC to set a high-priority interrupt to be constant on, but a processing function of the high-priority interrupt prohibits access to a critical area, while a low-priority interrupt processing function permits access to the critical area, through the setting, the aspect can continue to use the traditional interrupt-closing method to realize the setting of the critical area, and in addition, the aspect can maintain the real-time performance of system processing.

According to an embodiment, the circuitry implements interrupt priority handling methods and can be implemented in a real-time operating system, when a processor is executing tasks, a high priority interrupt is received accessing a critical section, and when data in the critical section to be accessed by the high priority interrupt is processed by setting a flag state or bit state for a low priority interrupt because the high priority interrupt prohibits access to the critical section.

In the embodiment, the processor originally performed tasks that are either ordinary tasks that need not be interrupted by interrupt processing or tasks that are interrupted by low priority.

According to the embodiment of the circuit system, the circuit system may be soc, which includes processor and or more subsystems, the processor is used to execute the above-mentioned interrupt priority processing method.

To further understand the techniques, methods and effects of the present invention adopted to achieve the intended purpose, reference is made to the following detailed description of the invention, drawings, and accompanying drawings, which are provided for reference and illustration, and not for the purpose of limiting the invention.

Drawings

FIG. 1 shows a circuit block diagram of a prior art system on chip;

FIG. 2 is a flow diagram of an embodiment of a method for interrupt priority handling;

FIG. 3 illustrates an example of interrupt priority processing flow performed when a high priority interrupt occurs while the system is processing normal tasks;

FIG. 4 illustrates an example of interrupt priority processing flow showing a high priority interrupt occurring while a low priority interrupt is being processed by a system-on-chip.

Detailed Description

The invention provides circuit systems for processing Interrupt Priority (Interrupt Priority), the disclosed technology aims to utilize the characteristic that a system on chip (SoC) has Interrupt Priority, a aspect continues to use a method of disabled Interrupt to realize the setting of a Critical Section (Critical Section), and in addition, a aspect enables a Central Processing Unit (CPU) high-Priority Interrupt to be always turned on, for example, a safety-related processing program, an emergency treatment or an important thread, tasks of the Priority Interrupt processing are always not interfered by other interrupts, so that the constant turning on can be maintained to maintain the real-time performance of the system for processing the important tasks.

The Interrupt Priority Level refers to Interrupt states (Interrupt state), including high-Priority interrupts and low-Priority interrupts, and may be written in a register (register) of an Interrupt controller (Interrupt controller) or managed by software.

However, there is still a need for a mechanism for determining how the subsystem uses System resources by using interrupt information, which requires that the cpu can always be open in the handler for high-priority interrupts, for example, when the soc is applied to Real-Time Operating systems (RTOS), in order to maintain Real-Time performance of System processing, such as Real-Time processing security-related programs, or programs that require immediate response, some high-priority interrupts require status of being open.

For example, when a user accesses critical section data through the system-on-chip to form threads executing a critical section code on the central processing unit, since the data cannot be simultaneously requested to be accessed by threads (threads) of multiple subsystems, if the data can be obtained by each executing thread, the problem that the data is not -induced or wrong exists, generally prevents other threads from accessing the critical section by turning off the interrupt.

Therefore, according to the embodiment of the circuit system for processing interrupt priority provided by the invention, the processing (interrupt off) of the critical section is realized by a method of masking (mask) low-priority interrupt, so that the real-time operating system does not influence the original processing flow, and the real-time performance of the real-time operating system can be effectively improved.

The system on chip (SoC) includes processors and or a plurality of subsystems, the processors are used for executing the interrupt priority processing method, wherein, the interrupt controller inside the cpu or the interrupt controller outside the system is responsible for processing the interrupt signal triggered by each subsystem (such as the module on the SoC), each subsystem can send the request to the cpu through the interrupt controller, the cpu provides the service according to the priority, when the subsystem triggers the interrupt, the interrupt controller is responsible for communicating with other subsystems and sending the corresponding interrupt signal and the interrupt demand signal to the cpu, when the interrupt controller receives the interrupt signal, the interrupt controller will forward to the cpu, and the interrupt controller will execute the relevant interrupt processing program.

For example, in SoC, the CPU supports 16 interrupt counts, where 0-7 are low priority interrupts, priority and can only be interrupted by high priority interrupts, and 8-15 are high priority interrupts, priority within 16 interrupts.

In this embodiment, the rules for handling the interrupt program are set , including modifying the off interrupt (disable interrupt) method to mask (mask) low priority interrupts, all on interrupt (enable interrupt) methods to unmask (unmask) low priority interrupts, and high priority interrupts set constant on, wherein the low priority interrupt handling function allows access to the critical area, and the high priority interrupts are in a constant on state to handle any real time tasks but disallow their handling function access to the critical area.

According to the above rules, the flow of the embodiment of the interrupt priority processing method proposed by the present invention is as follows

Before starting the method, the system performs a pre-operation to set straight-on interrupts (constant-on) for the purpose of processing real-time tasks, but the processing function for high priority interrupts prohibits access to critical sections, and the low priority interrupt processing function sets to allow access to critical sections, as shown in fig. 2.

Flow begins at step S201 where the CPU in the SOC is operating at processing and operating as a normal task without interrupt handling, such as task A (see FIG. 3) executed by a thread in the CPU, but may also be -like tasks handling low priority interrupts, where a high priority interrupt occurs at step S203, the CPU in the SOC or an interrupt controller therein receives the high priority interrupt request, and if the high priority interrupt is operating to access critical area, it typically handles events that are more urgent than , but since the high priority interrupt is set to disable access to the critical area, the CPU receives the interrupt request and, at step S205, communicates with the low priority interrupt (passes information to the low priority interrupt), e.g., sets flag states (flag) or bit states (0 or 1), thereby setting (de-masking) the low priority interrupt to access and process data in the critical area to which the high priority interrupt accessed.

Since the low priority interrupt is set to allow access to the critical section, the data in the critical section can also be accessed by task, when the processor is notified by the interrupt flag, the thread in the soc will mask the low priority interrupt, in step S207, and let the processing function of the low priority interrupt allow access to the critical section.

Then, when returning to the low priority interrupt, the low priority interrupt is masked, in step S209, the processor determines whether to wake up the unprocessed job of the high priority interrupt, if it is determined that the unprocessed job of the high priority interrupt is not needed to be continued, in step S211, the program is terminated, and the system can return to the original job (task a shown in fig. 3), otherwise, in step S213, the processor wakes up the job (task B shown in fig. 3) to continue processing the unprocessed job of the high priority interrupt.

An embodiment of the disclosed interrupt priority processing flow is shown in the following diagram.

[ example ]

The example of fig. 3 illustrates interrupt priority processing flow performed when a high priority interrupt occurs while the system is processing normal tasks.

When the system processor is executing -like tasks, such as task A (step S301), then high priority interrupts occur, which tend to handle more real-time or urgent tasks, and the system handles high priority interrupts in real-time (step S303).

For example, the high priority interrupt may work to access the critical section, but the rule design of the system is to keep the high priority interrupt constant but prohibit its processing function from accessing the critical section, so the processor then sets the low priority interrupt by means of a flag or the like (step S305) to allow the system to process the low priority interrupt, e.g., to allow the low priority interrupt to access and process the critical section data to be accessed by the high priority interrupt (step S307), when the access to the critical section data by the low priority interrupt is completed, and then checks whether to wake up the task (task B) that the high priority interrupt did not complete before (step S309), if there are unfinished tasks, wake up task B when the low priority interrupt returns, and the system delegates task B to continue to complete the work (step S311).

[ example two ]

FIG. 4 illustrates an example interrupt priority processing flow in which a processor in a system-on-chip has a high priority interrupt while processing a low priority interrupt.

When the processor is processing the task of the low-priority interrupt (step S401), it receives the signal of the high-priority interrupt, i.e. the high-priority interrupt is processed by the catcher (step S403), and then, when the high-priority interrupt is processed, it completes the transmission of the message by the method of communicating with the low-priority interrupt (step S405), and continues processing the task of the low-priority interrupt (step S407), and then checks whether the task of the previous high-priority interrupt is completed to judge whether to wake up the task B (step S409), if there is not yet the work of the high-priority interrupt, the system assigns the task B (step S411), and lets the task B continue to complete the rest of the work of the high-priority interrupt.

According to the above embodiments, the interrupt priority processing method disclosed in the present invention enables the high priority interrupt to be turned off constantly by resetting the method of turning off the interrupt and modifying the processing mechanism of the high priority interrupt, and the interrupt turning off mechanism can be continuously used by masking the tasks like the low priority interrupt processing , so that the processing requirement of the original critical area can be satisfied in aspect, and the real-time performance of the system processing can be effectively improved in aspect.

In summary, the interrupt priority processing method and related circuit system disclosed in the specification are suitable for a system on chip (SoC) with a priority interrupt mechanism, and are used for improving an interrupt handling program in an operating system.

It should be understood that the above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, so that the equivalent structural changes shown in the description and drawings of the present invention are included in the scope of the present invention.

Description of the symbols

CPU 110 interrupt controller 115

Memory 111 sensor 112

Bus 10 subsystem 101-105

Interrupt priority processing flow from step S201 to step S213

Example interrupt priority processing flow in Steps S301-S311

Step S401 to step S411 interrupt priority processing flow example two.