Semiconductor memory device with a memory cell having a plurality of memory cells
阅读说明:本技术 半导体存储器装置 (Semiconductor memory device with a memory cell having a plurality of memory cells ) 是由 冈田敏治 于 2019-07-19 设计创作,主要内容包括:本发明涉及半导体存储器装置。提供了能够在短时间内输出示出存储器单元的通常块和缺陷块的配置关系的数据序列的半导体存储器装置。具有:存储器部,包括具有每一个由多个存储器单元构成的多个存储器块的通常存储器区域、以及具有用于置换多个存储器块之中的作为包括缺陷单元的存储器块的缺陷块的冗余块的冗余存储器区域;存储部,将示出通常存储器区域中的缺陷块的位置的缺陷地址信息与作为该缺陷块的置换对象的冗余块的位置对应起来存储;以及输出电路,根据数据读出信号,基于存储部中存储的信息,输出示出通常存储器区域的至少一部分的区域中的缺陷块与缺陷块以外的块的配置关系的由2值的数据构成的数据序列。(A semiconductor memory device capable of outputting a data sequence showing an arrangement relationship between a normal block and a defective block of memory cells in a short time, the semiconductor memory device includes a memory section including a normal memory region including a plurality of memory blocks each formed of memory cells and a redundant memory region including a redundant block for replacing a defective block of the memory blocks including a defective cell, a storage section storing defect address information showing a position of the defective block in the normal memory region and a position of the redundant block to be replaced by the defective block in association with each other, and an output circuit outputting a data sequence showing an arrangement relationship between the defective block and a block other than the defective block in a region of at least parts of the normal memory region based on information stored in the storage section based on a data read signal.)
A semiconductor memory device of the kind 1, , comprising:
a memory unit including a normal memory area including a plurality of memory blocks each including memory cells, and a redundant memory area including a redundant block having another address, the redundant memory area being an area for replacing an access to a defective block among the plurality of memory blocks with an access to the other address;
a storage unit that stores address information indicating a position of the defective block in the normal memory area in association with address information indicating a position of a redundant block to be replaced with the defective block; and
and an output circuit that outputs a data sequence of 2-valued data indicating an arrangement relationship between the defective block and a memory block other than the defective block in the normal memory area for at least an area of parts of the normal memory area based on the information stored in the storage unit, based on a data read signal.
2. The semiconductor memory device according to claim 1, wherein the output circuit generates the data sequence based on a distribution pattern of the 2-value data occurring in the memory portion, assuming that -value data among the 2-value data are written to a redundant block corresponding to the defective block and another -value data are written to a memory block other than the defective block of the normal memory area.
3. The semiconductor memory device according to claim 2, wherein the output circuit receives the data read signal and an address designation designating an area of the at least part of the normal memory area, extracts a distribution pattern corresponding to the area designated by the address designation from a distribution pattern of the 2-valued data appearing in the memory portion, and outputs the extracted distribution pattern as the data sequence.
4. The semiconductor memory device according to any of claims 1 to 3, wherein the output circuit is configured to be switched to a1 st output mode or a2 nd output mode in response to a designation of an output mode,
when the 1 st output mode is designated, the data sequence is output based on the data read signal, and when the 2 nd output mode is designated, the information actually written in the memory unit is output based on the data read signal.
A semiconductor memory device of the kind described in 5, , comprising:
a memory unit including a normal memory area including a plurality of memory blocks each including memory cells, and a redundant memory area including a redundant block having another address, the redundant memory area being an area for replacing an access to a defective block among the plurality of memory blocks with an access to the other address;
a storage unit that stores address information indicating a position of the defective block in the normal memory area in association with address information indicating a position of a redundant block to be replaced with the defective block; and
and a fixed value write circuit for writing values of data among the 2-value data into a redundant block corresponding to the defective block and another values of data into a memory block other than the defective block in the normal memory area based on the information stored in the storage unit in accordance with a data write start signal.
Technical Field
The present invention relates to a semiconductor memory device.
Background
In a manufacturing process of a semiconductor Memory such as a DRAM (Dynamic Random Access Memory), a test for determining the quality of the semiconductor Memory is performed in a wafer test process of a wafer on which the semiconductor Memory is formed. In such a test, memory cells that do not satisfy the prescribed operating conditions are detected as failing cells. In a semiconductor memory, a redundant area is provided in addition to a normal memory area, and a memory cell determined as a defective cell in a test is replaced with a cell (redundant cell) in the redundant area. That is, when an access is tried for an address of a defective cell, an access is made to an address of a redundant cell instead of the defective cell. If a larger number of defective cells than the number of redundant cells are detected, the semiconductor memory is determined to be defective.
In addition, in order to improve the detection rate of fail bits in a semiconductor memory and improve testability, parallel tests of an expected value comparison method are performed, and in parallel tests of an expected value comparison method, data read from memory cells is compared with expected value data, and in this case, parallel tests of an expected value comparison method are performed on a normal memory cell that is not a redundant cell, and therefore, when a redundant region is accessed, there is a problem in that an expected value becomes unclear.
Disclosure of Invention
Problems to be solved by the invention
In the case of performing a test by the method of the above-described conventional technique, it is necessary to acquire information indicating which memory cell is replaced with a redundant cell. However, when acquiring this information, it is necessary to write data in advance into the normal area and the redundant area and to repeat a process of issuing a write command corresponding to writing of each memory cell from the outside of the DRAM by a DRAM controller or the like for each memory cell, as preparation for the writing, and therefore, there is a problem that it takes time to write.
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory device capable of outputting a data sequence showing an arrangement relationship between a normal block and a defective block of a memory cell in a short time.
Means for solving the problems
A semiconductor memory device includes a memory including a normal memory area including a plurality of memory blocks each including memory cells and a redundant memory area including a redundant block having a defective block among the plurality of memory blocks, the redundant memory area being an area for replacing an access to an address of the defective block with an access to another address, a storage unit storing address information indicating a position of the defective block in the normal memory area and address information indicating a position of the redundant block to be replaced by the defective block in association with each other, and an output circuit outputting a data sequence including 2-valued data indicating an arrangement relationship between the defective block and a memory block other than the defective block in the normal memory area in an area of at least parts of the normal memory area based on information stored in the storage unit in accordance with a data read signal.
The semiconductor memory device of the present invention includes a memory including a normal memory area including a plurality of memory blocks each including memory cells, and a redundant memory area including a redundant block having a defective block among the plurality of memory blocks, the redundant memory area being an area for replacing an access to an address of the defective block with an access to another address, a storage unit storing address information indicating a position of the defective block in the normal memory area in association with address information indicating a position of the redundant block to be replaced by the defective block, and a fixed value write circuit writing values of data among 2 values of data to the redundant block corresponding to the defective block and writing another values of data to a memory block other than the defective block in the normal memory area based on information stored in the storage unit in accordance with a data write start signal.
Effects of the invention
According to the semiconductor memory device of the present invention, it is possible to output a data sequence showing the arrangement relationship of normal blocks and defective blocks of memory cells in a short time.
Drawings
Fig. 1 is a block diagram showing the structure of a semiconductor memory device of embodiment 1.
Fig. 2A is a diagram showing the structure of a memory cell.
Fig. 2B is a diagram schematically showing an image in the case where a redundant area is used.
Fig. 3A is a diagram showing a memory area in the case where "0" is written to the cells of the normal area and "1" is written to the cells of the redundant area.
Fig. 3B is a diagram schematically showing access to a normal block and a redundant block.
Fig. 4 is a block diagram showing the structure of the fixed value output circuit and the flow of data.
Fig. 5 is a flowchart showing a processing routine of the data acquisition process.
Fig. 6 is a block diagram showing the structure of the semiconductor memory device of embodiment 2.
Fig. 7 is a block diagram showing the structure of the fixed value auto-write circuit and the flow of data.
Detailed Description
Hereinafter, preferred embodiments of the present invention will be described in detail. In the following description of the embodiments and the accompanying drawings, the same reference numerals are given to substantially the same or equivalent parts.
[ example 1]
Fig. 1 is a block diagram showing the structure of a semiconductor memory device 100 of the present embodiment. The semiconductor memory device 100 is composed of, for example, a dram (dynamic Random Access memory). The semiconductor memory device 100 includes a
The
The
Fig. 2A is a diagram schematically showing the structure of the
Fig. 2B is a diagram schematically showing an image in the case where a redundant area is used in the semiconductor memory of the present embodiment. Here, blocks of addresses PP, OO, NN, and MM of the normal area a1 are indicated by oblique lines as defective blocks.
In the
Referring again to fig. 1, the
The user IF 21 is an interface unit that receives a command (command signal) such as writing or reading from the outside of the semiconductor memory device 100 to the
The command/
The test
The read/write
The redundant area
The
The memory unit IF 27 is an interface unit that accesses the
The fixed
Fig. 3A is a diagram showing the appearance of the
The read position and size of the data sequence output by the fixed
Fig. 4 is a block diagram showing the structure of the fixed
The
The
The
Thus, when the fixed value output function of the fixed
Next, the processing operation of the data acquisition process performed by the semiconductor memory device 100 of the present embodiment will be described with reference to the flowchart of fig. 5.
First, a test mode control command including a command to validate the fixed value output function of the fixed
The command/
Next, the semiconductor memory device 100 receives a read command (read command) via the user IF 21 (step 102). the fixed
The semiconductor memory device 100 determines whether or not reading of the data sequence is completed (step 103). When it is determined that the reading is not completed (NO in step 103), the process returns to step 102 to wait for the reception of the read command again.
When the reading of the data sequence is completed (yes in step 103), a command to disable the function of the fixed
The command/
As described above, the semiconductor memory device 100 of the present embodiment includes the fixed
Further, since the data sequence can be output without writing for outputting the data sequence and while maintaining the stored data in the
[ example 2]
Next, example 2 of the present invention will be explained. Fig. 6 is a block diagram showing the structure of the
The fixed value
Fig. 7 is a block diagram showing the structure of the fixed value
The counter 41 starts counting in response to a command supplied from a DRAM controller or the like outside the
The address generation unit 42 generates an address by incrementing the count of the counter 41. The control signal generator 43 generates a control signal.
The address decoder 44 determines which of the normal area a1 and the redundant area a2 the address generated by the address generation section 42 shows, and supplies the result thereof to the data switching block 45.
The data switching block 45 determines "0" as data to be written into the
The fixed value
When a read command is received from a DRAM controller or the like outside the
As described above, in the
For example, in the case of 1Gbit DRAM with a data rate of 1600Mbps at maximum, 1024Mbit/1600Mbps =640ms is required at the lowest among all writes in the normal area a 1. Further, a processing time is required for the DRAM controller to issue a repeat of 800 ten thousand or more commands. In contrast, according to the
The present invention is not limited to the above embodiments. For example, in the above-described embodiment 2, a case has been described in which a command for writing all of the normal/redundant areas is issued from the DRAM controller, and the fixed value
Description of reference numerals
100 semiconductor memory device
10 memory area
General area of A1
A2 redundant area
11 fuse
12 control logic circuit
21 subscriber IF
22 command/address analysis unit
23 test mode control part
24 read/write control section
25 redundant area use judging part
26 fuse interface
27 memory cell IF
28 fixed value output circuit
31 function switching block
32 data switching block
33 address decoder
40 fixed value automatic write circuit
41 counter
42 address generating part
43 control signal generating part
44 address decoder
45 data switch block.
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