阅读说明：本技术 存储器设备以及制造存储器设备的方法 (Memory device and method of manufacturing memory device ) 是由 角野润 田崎雅幸 深田英幸 于 2018-05-01 设计创作，主要内容包括：根据本公开的实施例的存储器设备包含逻辑电路,其中层压包括具有不同布线间距的层的多个布线层,以及设置在多个布线层之间的存储器元件。(A memory device according to an embodiment of the present disclosure includes a logic circuit in which a plurality of wiring layers including layers having different wiring pitches and a memory element disposed between the plurality of wiring layers are laminated.)

1. A memory device, comprising:

a logic circuit in which a plurality of layers including wiring layers different in wiring pitch are stacked; and

a memory element disposed between the plurality of wiring layers.

2. The memory device of claim 1, wherein a selection element and the memory element are disposed together between the plurality of routing layers.

3. The memory device of claim 1, wherein

The logic circuit includes a logic portion and a memory portion in which the memory element is formed, and

the logic section and the memory section have the same wiring structure.

4. The memory device according to claim 1, wherein, among the plurality of wiring layers, a first wiring layer and a second wiring layer are stacked in order, the first wiring layer being formed by stacking a plurality of wiring layers with a dense wiring pitch, the second wiring layer being formed by stacking a plurality of wiring layers with a sparse wiring pitch than the wiring pitch of the first wiring layer.

5. The memory device of claim 4, wherein

The memory element and the selection element together constitute a memory cell, and

the memory cell is disposed between two wirings stacked in the first wiring layer.

6. The memory device of claim 4, wherein

The memory element and the selection element together constitute a memory cell, and

in the memory cell, the memory element is provided between one of the wirings stacked in the first wiring layer, and the selection element is provided between the other of the wirings.

7. The memory device of claim 4, wherein

The memory element and the selection element together constitute a memory cell, and

the memory cell and the conductive film are stacked between two wirings stacked in the first wiring layer.

8. The memory device of claim 4, wherein

The memory element and the selection element together constitute a memory cell, and

the memory cell is disposed between a plurality of wirings within the first wiring layer.

9. The memory device of claim 4, wherein

The memory element and the selection element together constitute a memory cell, and

the memory cells are disposed across the first wiring layer and the second wiring layer.

10. The memory device according to claim 9, wherein the memory element is disposed on the second wiring layer side, and the selection element is disposed on the first wiring layer side.

11. The memory device of claim 4, wherein

The memory element and the selection element together constitute a memory cell, and

the memory cells are respectively disposed between wirings in the first wiring layer and between wirings in the second wiring layer.

12. The memory device of claim 2, wherein

Each of the plurality of routing layers includes a plurality of routes, an

A protective film is formed on a side surface of the memory element and the selection element, the memory element and the selection element being provided on one wiring of wiring layers including the plurality of wirings, the protective film being formed in the same wiring layer as the one wiring and being continuous with an etching stopper film provided on the wiring constituting the logic circuit.

13. The memory device of claim 1, wherein the memory element is a resistance change memory element or a spin injection memory element.

14. A method of manufacturing a memory device, the method comprising:

forming a logic circuit by stacking a plurality of wiring layers including layers different in wiring pitch; and

memory elements are formed between the plurality of wiring layers.

15. The method of manufacturing a memory device of claim 14, wherein

Each of the plurality of routing layers includes a plurality of routes,

the method comprises the following steps

Forming a memory cell including the memory element and the selection element on one wiring of a wiring layer including the plurality of wirings, an

Thereafter, a via hole connecting between the plurality of wiring layers is formed on another wiring formed in the same wiring layer as the one wiring.

16. The method of manufacturing a memory device according to claim 15, further comprising, after forming the memory cell on the one wiring: an etching stopper film used when forming the through hole on the other wiring and a protective film covering a side surface of the memory element are collectively formed.

17. The method of manufacturing a memory device of claim 15, further comprising:

forming the selection element on the one wiring; and

thereafter, barrier metal films are collectively formed on the selection element and the other wiring, thereby forming barrier metal films having different film thicknesses on the selection element and the other wiring.

18. The method of manufacturing a memory device of claim 15, further comprising: forming an etching stopper film including materials different from each other on one wiring of the wiring layers including the plurality of wirings and on the memory cell.

Technical Field

The present disclosure relates to a memory device in which memory elements are mixed on a logic circuit, and to a method of manufacturing the memory device.

Background

For example, as in the semiconductor devices disclosed in PTLs 1 and 2, hybrid mounting of a nonvolatile memory on a logic circuit of a semiconductor device such as a microcomputer has been widely used as a means for improving the functional capability of the semiconductor device.

CITATION LIST

Patent document

PTL 1: japanese unexamined patent application publication No.2017-45947

PTL 2: japanese unexamined patent application publication No.2017-54900

Disclosure of Invention

Incidentally, in the case where a NOR-type flash memory is used as a memory to be mixed on a logic circuit, a memory section and a driver section are arranged in parallel with each other on a substrate. Therefore, the area per bit may increase, which raises a concern about an increase in cost.

It is desirable to provide a memory device that can achieve both higher functional capability and cost reduction, and a method of manufacturing such a memory device.

A memory device according to an embodiment of the present disclosure includes: a logic circuit in which a plurality of wiring layers including layers different in wiring pitch are stacked; and a memory element disposed between the plurality of wiring layers.

A method of manufacturing a memory device according to an embodiment of the present disclosure includes: forming a logic circuit by stacking a plurality of wiring layers including layers different in wiring pitch; and forming memory elements between the plurality of wiring layers.

In the memory device according to the embodiment of the present disclosure and the method of manufacturing the memory device according to the embodiment of the present disclosure, forming the memory element between the plurality of wiring layers including the layers which are different in wiring pitch and constitute the logic circuit allows the memory element to be mixed on the logic circuit without changing the wiring pattern or the stacked structure of the logic circuit.

According to the memory device of the embodiment of the present disclosure and the method of manufacturing the memory device of the embodiment of the present disclosure, the memory element is formed between the plurality of wiring layers including the wiring layers which are different in wiring pitch and constitute the logic circuit, which allows the memory element to be mixed on the logic circuit without changing the wiring pattern or the stacked structure of the logic circuit. This may enable both higher functional capabilities and cost reduction.

It is to be noted that the above-described effects are not necessarily restrictive, and any of the effects described in the present disclosure may be provided.

Drawings

Fig. 1 is a schematic cross-sectional view of the configuration of a memory device according to a first embodiment of the present disclosure.

Fig. 2 is an enlarged cross-sectional schematic view of a main portion of the memory section shown in fig. 1.

Fig. 3A is a schematic sectional view for describing an example of a method of manufacturing a main portion of the memory device shown in fig. 1.

Fig. 3B is a schematic cross-sectional view of a process subsequent to the process shown in fig. 3A.

Fig. 3C is a schematic cross-sectional view of a process subsequent to the process shown in fig. 3B.

Fig. 3D is a schematic cross-sectional view of a process subsequent to the process shown in fig. 3C.

Fig. 3E is a schematic cross-sectional view of a process subsequent to that shown in fig. 3D.

Fig. 3F is a schematic cross-sectional view of a process subsequent to that shown in fig. 3E.

Fig. 3G is a schematic cross-sectional view of a process subsequent to that shown in fig. 3F.

Fig. 3H is a schematic cross-sectional view of a process subsequent to that shown in fig. 3G.

Fig. 4 is a schematic cross-sectional view of the configuration of a memory device according to a second embodiment of the present disclosure.

Fig. 5 is a schematic cross-sectional view of the configuration of a memory device according to a third embodiment of the present disclosure.

Fig. 6 is a schematic cross-sectional view of the configuration of a memory device according to a fourth embodiment of the present disclosure.

Fig. 7 is a schematic cross-sectional view of the configuration of a memory device according to a fifth embodiment of the present disclosure.

Fig. 8 is a cross-sectional configuration view of the configuration of a memory device according to modification 1 of the present disclosure.

Fig. 9 is a schematic cross-sectional view of the configuration of a memory device according to modification 2 of the present disclosure.

Fig. 10A is a schematic sectional view for describing a method of manufacturing a main portion of the memory device shown in fig. 9.

Fig. 10B is a schematic cross-sectional view of a process subsequent to the process shown in fig. 10A.

Fig. 10C is a schematic cross-sectional view of a process subsequent to the process shown in fig. 10B.

Fig. 10D is a schematic cross-sectional view of a process subsequent to the process shown in fig. 10C.

Fig. 10E is a schematic cross-sectional view of a process subsequent to that shown in fig. 10D.

Fig. 10F is a schematic cross-sectional view of a process subsequent to that shown in fig. 10E.

Fig. 10G is a schematic cross-sectional view of a process subsequent to the process shown in fig. 10F.

Fig. 11A is a schematic sectional view for describing a method of manufacturing a main portion of a memory device according to modification 3 of the present disclosure.

Fig. 11B is a schematic cross-sectional view of a process subsequent to the process shown in fig. 11A.

Fig. 11C is a schematic cross-sectional view of a process subsequent to the process shown in fig. 11B.

Fig. 11D is a schematic cross-sectional view of a process subsequent to the process shown in fig. 11C.

Fig. 12 is a schematic cross-sectional view of the configuration of a memory device according to modification 4 of the present disclosure.

Fig. 13 is a schematic cross-sectional view of the configuration of a memory device according to modification 5 of the present disclosure.

Fig. 14 is a schematic sectional view of a configuration of a main portion of a memory device according to modification 6 of the present disclosure.

Fig. 15 is a schematic cross-sectional view of the configuration of the main part of a memory device according to modification 7 of the present disclosure.

Detailed Description

Hereinafter, some embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The following description is merely specific examples of the present disclosure, and the present disclosure is not limited to the following embodiments. Further, the present disclosure is not limited to the arrangement, the size ratio, and the like of each component shown in the drawings. Note that the description is given in the following order.

1. First embodiment (example in which memory cells are arranged between wiring layers constituting a logic circuit)

1-1, Structure of memory device

1-2 method of manufacturing a memory device

1-3, action and Effect

2. Second embodiment (example in which memory elements are formed between wiring layers on one side and selection elements are arranged between wiring layers on the other side among three stacked wiring layers)

3. Third embodiment (example in which memory cells are formed in three stacked wiring layers omitting second-layer wiring layer)

4. Fourth embodiment (example in which memory cells and intermediate resistance layer are formed in a stacked manner among three stacked wiring layers omitting second-layer wiring layer)

5. Fifth embodiment (example of forming memory cells to cross the boundary between wiring layers different in wiring pitch)

6. Modification example

6-1, modification 1 (example in which memory cells are formed in three stacked wiring layers including wiring layers with different wiring pitches, omitting second-layer wiring layer)

6-2, modification 2 (example in which an intermediate resistance layer is provided between a memory element and a selection element constituting a memory cell)

6-3, modification 3 (example in which coupling of a wiring and a via in a logic portion and coupling of a bit line BL and a memory cell in a memory portion are collectively performed by using an etching stopper film including different materials in the logic portion and the memory portion)

6-4, modification 4 (example in which a plurality of memory cells are provided between different wiring layers)

6-5, modification 5 (example in which a plurality of memory cells are provided between wiring layers having different wiring pitches)

6-6, modification 6 (example of positional deviation of barrier metal film formed on memory cell)

6-7, modification 7 (example of forming memory cells between wiring layers constituting a logic circuit by a damascene method)

<1, first embodiment >

Fig. 1 is a schematic diagram of a cross-sectional configuration of a memory device (memory device 1) according to a first embodiment of the present disclosure. Fig. 2 is an enlarged view of the configuration of the main portion of the memory device 1 shown in fig. 1. The memory device 1 constitutes a microcomputer to be mounted on, for example, a mobile device or an electronic device of an automobile or the like, and has a configuration in which a memory is mixed in a logic circuit. In the present embodiment, the memory device 1 has a configuration in which the memory elements 12 are formed between wiring layers (for example, between the metal film M3 and the metal film M4) among a plurality of wiring layers (the metal film M1 to the metal film M10) constituting the logic circuit 100.

(1-1, Structure of memory device)

As described above, the memory device 1 has the following configuration: a memory (memory element 12) is mixed on the logic circuit 100, and the logic circuit 100 has a multilayer wiring structure in which a plurality of wiring layers are stacked. The logic circuit 100 includes a logic portion 100A constituting a circuit that performs a logic operation and a memory portion 100B forming the memory element 12. The logic section 100A and the memory section 100B have the same wiring structure. In other words, the logic section 100A and the memory section 100B have the same wiring pattern in the same layer, and also have a wiring structure formed at the same wiring interval in the stacking direction.

The multilayer wiring structure constituting the logic circuit 100 has a configuration in which layers having different wiring pitches are stacked, and includes a layer (first wiring layer) in which a plurality of wiring layers having a dense wiring pitch are stacked, and a layer (second wiring layer) in which a plurality of wiring layers having a sparse wiring pitch are stacked. In the memory device 1 of the present embodiment, as shown in fig. 1, the logic circuit 100 has the following configuration: the first wiring layer 10 in which the wiring layer having the most dense wiring pitch is stacked, the second wiring layer 20 having a wiring pitch that is sparser than the wiring pitch of the first wiring layer 10, and the third wiring layer 30 having the most sparse wiring pitch are stacked in this order on the substrate 41.

The multilayer wiring structure constituting the logic circuit 100 has a structure in which ten wiring layers are stacked, for example. Specifically, the logic circuit 100 has the following configuration: for example, a metal film M1, a metal film M2, a metal film M3, a metal film M4, a metal film M5, a metal film M6, a metal film M7, a metal film M8, a metal film M9, and a metal film M10 are formed to be embedded in an insulating film, for example, an interlayer insulating film 48 (see fig. 3H), in this order from the substrate 41 side. The metal film M1 and the metal film M2 are coupled by a via V1. Hereinafter, in a similar manner, the metal film M2 and the metal film M3 are coupled through the via V2. The metal film M3 and the metal film M4 are coupled by a via V3. The metal film M4 and the metal film M5 are coupled by a via V4. The metal film M5 and the metal film M6 are coupled by a via V5. The metal film M6 and the metal film M7 are coupled by a via V6. The metal film M7 and the metal film M8 are coupled by a via V7. The metal film M8 and the metal film M9 are coupled by a via V8. The metal film M9 and the metal film M10 are coupled by a via V9. The metal film M1 is provided on the base plate 41 with the contact CT1 interposed therebetween. As described above, in the metal films M1 to M10, the metal films M1 to M6 are formed in accordance with the same wiring rule to constitute the first wiring layer 10. The metal film M7 and the metal film M8 are formed according to the same wiring rule to constitute the second wiring layer 20. The metal film M9 and the metal film M10 are formed according to the same wiring rule to constitute the third wiring layer 30. It is to be noted that the configuration of the logic circuit 100 as shown in fig. 1 is merely an example, and is not restrictive.

In the present embodiment, the memory element 12 constitutes the memory cell 13 together with the selection element 11, and is formed between wiring layers of the memory section 100B having a wiring structure similar to that of the logic section 100A. Specifically, for example, between the metal film M3 and the metal film M4 in the first wiring layer 10 having the densest wiring pitch, at a part of the via V3, the memory element 12 is formed as the memory cell 13 together with the selection element 11.

The memory cell 13 is an element constituting a memory cell array having a so-called cross-point array structure, and is provided at an intersection of a word line WL extending in one direction and a bit line BL extending in a direction different from the direction of the word line WL. The present embodiment has the following configuration: the metal film M3 provided in the memory section 100B functions as a word line WL and the metal film M4 functions as a bit line BL, and the selection element 11 is arranged on the word line WL side and the memory element 12 is arranged on the bit line BL side. Note that fig. 1 does not show the vias V2 and V5 respectively connecting between the metal film M2 and the word line WL and between the metal film M5 and the metal film M6; however, each electrical coupling is performed at a different location than the cross-sectional surface shown in fig. 1.

(selecting element)

The selection element 11 is used to selectively operate any one of a plurality of memory elements provided in a memory cell array having a so-called cross-point array structure. Further, the selection element 11 is coupled in series to the memory element 12, and causes a significant decrease in resistance as the applied voltage increases, while assuming a high resistance state at a low applied voltage. In other words, the selection element 11 has a nonlinear resistance characteristic that exhibits a high resistance in the case where the applied voltage is low, and the resistance significantly decreases in the case where the applied voltage is high to cause a large current to flow (for example, a current several orders of magnitude higher). Further, the selection element 11 is an element that does not perform a memory operation such as, for example, an operation of maintaining a conduction path formed by ion migration caused by an applied voltage even after the applied voltage is removed.

The selection element 11 has a configuration using, for example, a bidirectional threshold switch, and includes, for example, an element configuration of any one of bgaatte, bgaasete, bgaapten, bgaapteo, bgaaseteo, bgaactte, BGaCAsTe, bgaacnten, BGaCAsTe, BGaCAsTeO, and BGaCAsTeO. Further, the selection element 11 may be constituted using, for example, an MSM (metal-semiconductor-metal) diode, an MIM (metal-insulator-metal) diode, and a varistor, or may include a plurality of layers. In addition, as the selection element 11, a unidirectional diode or a bidirectional diode may be used depending on the operation method of the memory element 12.

(memory element)

The memory element 12 is a resistive random access memory element having non-volatility that allows, for example, a state in which a resistance value reversibly changes by an electric signal to be maintained. The memory element 12 has a structure in which, for example, an ion source layer 12A and a resistance change layer 12B are stacked as shown in fig. 2.

The ion source layer 12A is formed to include a movable element that forms a conduction path in the resistance change layer 12B by applying an electric field. These mobile elements are, for example, transition metal elements, aluminum (Al), copper (Cu) or chalcogens. Examples of chalcogens include tellurium (Te), selenium (Se), and sulfur (S). The transition metal element is an element belonging to any one of the fourth to sixth groups of the periodic table, and examples of such transition metal elements include titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), and the like. The ion source layer 12A includes one or two or more of the above-described movable elements. Alternatively, the ion source layer 12A may include oxygen (O), nitrogen (N), elements other than the above-described movable elements (e.g., manganese (Mn), cobalt (Co), iron (Fe), nickel (Ni), platinum (Pt)), silicon (Si), or the like.

The resistance change layer 12B includes, for example, an oxide of a metal element or a non-metal element or a nitride of a metal element or a non-metal element, and has a resistance value that changes in the case where a predetermined voltage is applied between a pair of electrodes.

In the memory element 12 of the present embodiment, when a voltage or current pulse in the "positive direction" is applied to an element in the initial state (high resistance state), for example, the transition metal element included in the ion source layer 12A is ionized to diffuse into the resistance change layer 12B, or oxygen ions migrate, thereby causing oxygen deficiency. As a result, a low-resistance portion (conduction path) in a low oxidation state is formed in the resistance change layer 12B to reduce the resistance (recording state) in the resistance change layer 12B. When a voltage pulse in the "negative direction" is applied to the memory element 12 in such a low resistance state, metal ions in the resistance change layer 12B migrate into the ion source layer 12A, or oxygen ions migrate from the ion source layer 12A to reduce oxygen deficiency in the conduction path portion. This results in the disappearance of the conduction path including the transition metal element, which places the resistance change layer 12B in a high-resistance state (initial state or erased state).

It is to be noted that the basic principle of the resistance change is not particularly limited to changes in phase, polarization, magnetization direction, formation of a conduction path (filament), and the like. In other words, as the memory element 12, any one of, for example, a PCM (phase change memory element), an FeRAM (ferroelectric random access memory element), an MRAM (magnetoresistive random access memory element), and a resistive random access memory element including a transition metal oxide or sulfide can be used.

Further, in the memory cell 13 shown in fig. 2, an example is shown in which the ion source layer 12A is arranged on the bit line BL side and the resistance change layer 12B is arranged on the selection element 11 side; however, this is not restrictive. As the configuration of the memory element 12, the ion source layer 12A may be arranged on the selection element 11 side, and the resistance change layer 12B may be arranged on the bit line BL side. In addition, the memory unit 13 may include another layer. For example, a barrier layer that prevents diffusion of the transition metal element and ion conduction, for example, may be formed between the selection element 11 and the memory element 12. Examples of materials for the barrier layer include tungsten (W), tungsten nitride (WN), titanium nitride (TiN), carbon (C), molybdenum (Mo), tantalum (Ta), tantalum nitride (TaN), titanium Tungsten (TiW), silicide, and the like. Providing the barrier layer reduces the degradation of the selection element 11 caused by the diffusion of the transition metal element included in the ion source layer 12A.

(1-2, method of manufacturing memory device)

The memory device 1 of the present embodiment can be manufactured in the following manner, for example. It is to be noted that the manufacturing method described below is merely an example, and any other method may be used to form the memory device 1.

Fig. 3A to 3H show a method of manufacturing a main portion (a wiring layer with the memory cell 13 formed therebetween) of the memory device 1 of the present embodiment in a process sequence. First, as shown in fig. 3A, for example, a wiring technique based on a typical damascene method is used to form a metal film M5 and a word line WL having the same wiring pattern as the metal film M5, each of the metal film M5 and the word line WL having a barrier metal film 43 at the periphery thereof and being embedded in an interlayer insulating layer 42. Note that, in the present embodiment, the metal films M1 to M10, the word line WL, the bit line BL, and the vias V1 to V9 include copper (Cu), and a barrier metal film (e.g., barrier metal film 43) that prevents diffusion of Cu is formed at their peripheries. Thereafter, a continuous barrier metal film (e.g., TiN film) 44, selection element layer 11X, memory element layer 12X, barrier metal film (e.g., TiN film) 45, and hard mask (mask 46) are sequentially formed on the metal film M5, word line WL, and interlayer insulating layer 42, for example, using a PVD (physical vapor deposition) method and a CVD (chemical vapor deposition) method.

Next, as shown in fig. 3B, the mask 46 is patterned using, for example, a photolithography method, and then the barrier metal film 44, the selection element layer 11X, the memory element layer 12X, and the barrier metal film 45 are etched using, for example, a dry etching method to form the memory cells 13 on the word lines WL.

Subsequently, as shown in fig. 3C, the SiN film 47 is formed using, for example, an ALD method or a CVD method. This ensures that the etching stopper film 47a and the protective film 47b protecting the memory cell 13 are formed in a single process.

Next, as shown in fig. 3D, a low-K film is formed on the SiN film 47 using, for example, a CVD method, and then the low-K film surface is planarized using a CMP (chemical mechanical polishing) method to form an interlayer insulating layer 48. Subsequently, a hard mask (mask 49) is formed on the interlayer insulating layer 48.

Next, by using the mosaic method, in the logic portionVia hole V3 and metal film M4 are formed on 100A, and bit line BL is formed on memory section 100B. First, as shown in fig. 3E, the mask 49 is patterned using a photolithography method, and the opening 48H reaching the etching stopper film 47a is formed by, for example, etching on the metal film M3 provided in the logic portion 100A₁。

Next, as shown in fig. 3F, the mask 49 is patterned using, for example, a photolithography method, and then an opening 48H having opening widths of the metal film M4 and the bit line BL is formed by etching on the metal film M3 and the memory cell 13, respectively₂。

Subsequently, as shown in fig. 3G, by performing etching again, the mask 46 on the memory cell 13 is removed, and the etching stopper film 47a on the metal film M3 is also etched to expose the metal film M3.

Next, for example, at opening 48H₂In, e.g. at opening 48H₂A TiN film is formed as the barrier metal film 50 on the side faces and the bottom surface. Finally, at opening 48H₂A copper (Cu) film is formed as the via hole V3, the metal film M4, and the bit line BL, and then the copper film formed on the interlayer insulating layer 48 is polished by a CMP method to remove the copper film, thereby planarizing the surface. This ensures that the wiring layers (here, the metal film M3 and the metal film M4) are formed with the memory cells 13 incorporated in the memory section 100B.

(1-3, action and Effect)

As described previously, hybrid mounting of a nonvolatile memory on a logic circuit constituting a semiconductor device such as a microcomputer has been widely used as a means for improving the functional capability of the semiconductor device. As a nonvolatile memory to be mixed in a logic circuit, a NOR type flash memory, a sliding gate type flash memory (slip-gate type flash memory), or the like is generally used.

These flash memories are memories to which semiconductor transistors are applied, and thus it is necessary to arrange a memory section and a driver section in parallel with each other on a substrate. Therefore, the area per bit may increase, which causes a problem of cost increase.

In contrast, in the memory device 1 and the manufacturing method thereof of the present embodiment, the memory element 12 is disposed between a plurality of wiring layers constituting the logic circuit 100. This allows hybrid mounting of the memory element 12 on the logic circuit 100 without the need to arrange the memory section and the driver section in parallel with each other on the substrate 41 as described above.

In view of all of this, in the memory device 1 and the manufacturing method thereof of the present embodiment, the memory element 12 is disposed between a plurality of wiring layers constituting the logic circuit 100. This allows hybrid mounting of the memory element 12 on the logic circuit 100 without arranging the memory section and the driver section in parallel with each other on the substrate 41 as described above, which can achieve both higher functional capability and cost reduction.

Further, in the present embodiment, a resistive random access nonvolatile memory element is used as the memory element 12. This makes it possible to form the memory elements 12 between the metal films constituting the first wiring layer 10 (for example, between the metal film M3 and the metal film M4) without changing the wiring pattern or the stacked structure of the wiring layers constituting the logic circuit, the first wiring layer 10 having the densest wiring pitch among the wiring layers constituting the logic circuit. Specifically, the memory element 12 can be formed by simply replacing the via V3 coupling the metal film M3 and the metal film M4 in the logic portion 100A with the memory cell 13. This makes it possible to provide the memory device 1 with higher functional capability at low cost.

Further, as described above, in the case where the dry etching method is used in the process of forming the memory cell 13, damage occurs at the side of the memory cell 13. Therefore, it is preferable to form a protective film on the side of the memory cell 13; however, this causes a concern about an increase in the number of processes. In contrast, in the method of manufacturing the memory device 1 of the present embodiment, the protective film 57b that protects the side walls of the memory cell 13 is collectively formed in the same process as the process of forming the etching stopper film 47a to be used in forming the via hole V3 that connects between the wirings provided in the logic portion (for example, between the metal film M3 and the metal film M4). This makes it possible to form the protective film 47b of the memory cell 13 without increasing the number of processes.

Next, descriptions are given of second to fifth embodiments and modified examples 1 to 7. Hereinafter, components similar to those of the above-described first embodiment are denoted by the same reference numerals, and descriptions thereof are appropriately omitted.

<2, second embodiment >

Fig. 4 is a schematic diagram of a cross-sectional configuration of a memory device (memory device 2A) according to a second embodiment of the present disclosure. The present embodiment is different from the above-described first embodiment in that the selection element 11 and the memory element 12 constituting the memory cell 13 are separately provided among three wiring layers formed in a stacked manner in the first wiring layer 10 constituting the logic circuit 100 (for example, between the metal film M3 and the metal film M4 and between the metal film M4 and the metal film M5, respectively).

As described above, in the memory device 2A of the present embodiment, with the metal film M4 constituting the first wiring layer 10 in the middle, the selection element 11 and the memory element 12 are disposed between the metal film M3 and the metal film M4 and between the metal film M4 and the metal film M5, respectively. In other words, the via V3 coupling the metal film M3 and the metal film M4 and the via V4 coupling the metal film M4 and the metal film M5 are replaced with the selection element 11 and the memory element 12, respectively, in the logic portion 100A. This allows the selection element 11 and the memory element 12 to sufficiently ensure respective thicknesses in the stacking direction, compared to the above-described first embodiment. Therefore, this embodiment achieves an effect that respective performances can be maintained as the microfabrication of the logic circuit 100 progresses, in addition to the above-described first embodiment.

<3, third embodiment >

Fig. 5 is a schematic diagram of a cross-sectional configuration of a memory device (memory device 3A) according to a third embodiment of the present disclosure. The present embodiment is different from the above-described first and second embodiments in that, for example, the metal film M4 in the first wiring layer 10 constituting the logic circuit 100 is omitted, and the memory cell 13 including the selection element 11 and the memory element 12 is disposed between the metal film M3 and the metal film M5.

The selection element 11 and the memory element 12 can be formed in the memory device 3A of the present embodiment by, for example, using the process of forming the via hole V3 and the metal film M4 as described in the above-described first embodiment. In other words, for example, in the process of forming via hole V3 and metal film M4 in logic section 100A as shown in fig. 3E to 3H, similar opening 48H is also formed in memory section 100B₂And the material of the selection element 11 is used instead of copper (Cu) for constituting the via hole V3 and the metal film M4. In this way, a selection element 11 as shown in fig. 5 can be formed. For the memory element 12, in the process of forming the via V4 and the metal film M5 in the logic portion 100A, an opening is formed using a similar method, and the opening is filled with the material of the memory element 12. In this manner, can form

The memory element 12 shown in fig. 5.

As a method other than the above-described methods, the methods given below are usable. For example, the selection element 11 is formed in a dry etching method, and then the via hole V3 and the metal film M4 are formed on the metal film M3 of the logic portion 100A. Note that, at this time, patterning of the metal film M4 is not performed on the selection element 11 provided in the memory section 100B. Such a process ensures that the top surface of the selection element 11 and the top surface of the metal film M4 are in the same plane. Subsequently, the memory element 12 is formed on the selection element 11 in a dry etching method, and then the via V4 and the metal film M5 are simultaneously formed in both the logic section 100A and the memory section 100B.

As described above, in the memory device 3A of the present embodiment, in the memory section 100B, the metal film M4 constituting the first wiring layer 10 is omitted, and the memory cell 13 is disposed between the metal film M3 and the metal film M5. This allows the selection element 11 and the memory element 12 to further ensure respective thicknesses corresponding to the thickness of the metal film M4 in the stacking direction. Therefore, compared with the second embodiment described above, the present embodiment achieves an effect that higher performance can be maintained even when microfabrication of the logic circuit 100 progresses.

<4, fourth embodiment >

Fig. 6 is a schematic diagram of a cross-sectional configuration of a memory device (memory device 4A) according to a fourth embodiment of the present disclosure. The present embodiment is different from the above-described first to third embodiments in that, for example, the metal film M4 in the first wiring layer 10 constituting the logic circuit 100 is omitted; and the memory cell 13 including the selection element 11 and the memory element 12 is disposed at a position where the via V3 and the metal film M4 are formed; and the intermediate resistance layer 14 is formed at the position where the through hole V4 is formed.

The intermediate resistance layer 14 serves to prevent an unexpected charging current from flowing through the memory cell 13. For example, the intermediate resistance layer 14 has a configuration similar to that of the via hole V4 to be provided in the logic portion 100A, and the intermediate resistance layer 14 may be formed, for example, when the via hole V4 of the logic portion 100A is formed. Alternatively, in a state where the film constituting the intermediate resistance layer 14 is formed on the memory element 12, the intermediate resistance layer 14 may be formed together with the memory element 12 in a dry etching method at the time of forming the memory element 12.

As described above, in the memory device 4A of the present embodiment, in the memory section 100B, the metal film M4 constituting the first wiring layer 10 is omitted; the memory cell 13 is disposed at a position where the via V3 and the metal film M4 are formed; and an intermediate resistance layer 14 is formed on the memory cell 13. This can prevent degradation in the memory cell 13 caused by an unexpected charging current that may flow through the memory cell 13 while ensuring the thicknesses of the selection element 11 and the memory element 12 in the stacking direction. Therefore, in addition to the effects of the first embodiment described above, the present embodiment achieves an effect that the respective performances can be maintained as the microfabrication of the logic circuit 100 progresses and an effect that allows the operational stability of the memory cell 13 to be enhanced.

Further, the formation of the intermediate resistance layer 14 generally involves an increase in the number of processes, resulting in an increase in cost. In contrast, in the present embodiment, the via hole V4 coupling the metal film M4 and the metal film M5 in the logic section 100A is used as the intermediate resistance layer 14 in the memory section 100B. This allows the intermediate resistance layer 14 to be formed without increasing the number of processes.

<5, fifth embodiment >

Fig. 7 is a schematic diagram of a cross-sectional configuration of a memory device (memory device 2B) according to a fifth embodiment of the present disclosure. The present embodiment is different from the above-described first to fourth embodiments in that the selection element 11 and the memory element 12 constituting the memory cell 13 are formed across the first wiring layer 10 and the second wiring layer 20 constituting the logic circuit 100.

As described above, in the memory device 2B of the present embodiment, the selection element 11 and the memory element 12 constituting the memory cell 13 are formed across the first wiring layer 10 and the second wiring layer 20 constituting the logic circuit 100. Specifically, for example, the selection element 11 is arranged between the metal film M6 constituting the first wiring layer 10 and provided at the boundary with respect to the second wiring layer 20 and the metal film M5 located immediately below the metal film M6, and the memory element 12 is formed between the metal film M6 and the metal film M7 constituting the second wiring layer 20. This allows the selection element 11 and the memory element 12 to sufficiently ensure respective thicknesses in the stacking direction. Further, the memory elements 12 are disposed in the second wiring layer 20 having a wiring pitch that is sparse than the first wiring layer 10. The vias V6 and V7 provided in the second wiring layer 20 are larger in wiring width than the vias V1 to V5 provided in the first wiring layer 10. Therefore, replacing the via (here, via V6) of the second wiring layer 20 with the memory element 12 can secure the element area of the memory element 12. Therefore, compared with the second embodiment described above, the present embodiment achieves an effect that the performance of the memory element 12 can be maintained even when the microfabrication of the logic circuit 100 is further advanced.

Further, in the present embodiment, the metal film M7 constituting the second wiring layer 20 having a large wiring pitch and film thickness in the stacking direction is used as the bit line BL, which allows the resistance of the bit line BL to be reduced. This suppresses signal degradation, and hence an effect can be achieved that the performance of the memory element 12 can be enhanced.

<6, modification >

(6-1, modification 1)

Fig. 8 is a schematic diagram of a cross-sectional configuration of a memory device (memory device 3B) according to modification 1 of the present disclosure. The memory device 3B of the present modification is a combination of the configurations of the above-described third embodiment and the above-described fifth embodiment. The memory cell 13 is formed across the first wiring layer 10 and the second wiring layer 20, and the selection element 11 and the memory element 12 are stacked between the metal film M5 and the metal film M7 in which the metal film M6 is omitted.

With the above configuration, the memory device 3B of the present modification achieves an effect that the performance of the memory element 12 can be maintained even when the microfabrication of the logic circuit 100 is further advanced.

(6-2, modification 2)

Fig. 9 is a schematic diagram of a cross-sectional configuration of a memory device (memory device 4B) according to modification 2 of the present disclosure. In the memory device 4B of the present modification, the intermediate resistance layer 14 provided between the memory cell 13 and the bit line BL in the fourth embodiment described above is provided between the selection element 11 and the memory element 12.

The memory device 4B of the present modification can be manufactured in the following manner, for example.

Fig. 10A to 10G show a method of manufacturing a wiring layer in which the memory cells 13 of the memory device 4B are formed in the process sequence. First, as shown in fig. 10A, for example, a barrier film 51 including, for example, titanium nitride (TiN) or tungsten (W) is formed on the metal film M3 and the word line WL having the same wiring pattern as the metal film M3 and on the interlayer insulating layer 42, each of the metal film M3 and the word line WL has a barrier metal film 43 at its periphery and is formed using a wiring technique based on a typical damascene method.

Subsequently, as shown in fig. 10B, a barrier metal film 44 is formed inside the barrier film 51 at a position corresponding to the word line WL, for example, using a PVD method, a CVD method, and a CMP method. Next, as shown in fig. 10C, the selective element layer 11X, the barrier metal film (for example, TiN film) 52, and the hard mask (masks 53 and 54) are sequentially formed on the barrier film 51 and the barrier metal film 44, for example, using a PVD method and a CVD method.

Next, as shown in fig. 10D, the mask 54 is patterned using, for example, a photolithography method, and then the selective element layer 11X, the barrier metal film 52, and the mask 53 are etched to form the memory cell 13 on the word line WL. Subsequently, the SiN film 47 is formed on the barrier film 51 and on the side faces and the top surface of the stacked selection elements 11, barrier metal film 52, and masks 53 and 54, for example, using an ALD method or a CVD method. Next, a low-K film is formed on the SiN film 47 using, for example, a CVD method, and then the surface is planarized by a CMP method to form the interlayer insulating layer 48. Then, a hard mask (mask 49) is formed on the interlayer insulating layer 48.

Subsequently, by using the damascene method, the via hole V3 and the metal film M4 are formed in the logic section 100A, and the bit line BL is formed in the memory section 100B. First, as shown in fig. 10E, the mask 49 is patterned using a photolithography method, and an opening 48H is formed on each metal film M3 provided in the logic portion 100A and the selection element 11, for example, by etching₃. Meanwhile, the barrier film 51 and the mask 53 function as etching stopper films on the metal film M3 and the selection elements 11, respectively.

Next, as shown in fig. 10F, the mask 49 is patterned using, for example, a photolithography method, and then the opening 48H of the metal film M4 is formed on the metal film M3 by etching₄. Then, by performing etching again, the barrier film 51 on the metal film M3 and the mask 53 on the selection member 11 are removed.

Next, as shown in FIG. 10G, openings 48H are opened, for example, using a PVD process₄The barrier metal film 50 is formed inside. At this time, the barrier metal film 50 to be formed has a film thickness following the opening 48H₄May vary in depth. In other words, as shown in fig. 10G, compared with the case where the barrier metal film 50 is formed on the metal film M3, there is an opening 48H₄Of the selection element 11 of smaller depth 48H₄The barrier metal film 50 is formed thicker at the bottom. The barrier metal film 50 provided on the selection element 11 corresponds to the intermediate resistance layer 14. The barrier metal film 50 is, for example, a TiN film, and has a higher resistance than copper (Cu) used to constitute the via hole V3. By using the opening 48H₄The barrier metal film 50 is formed as a thick film on the selection element 11, and such barrier metal film 50 is brought into contact with the via hole V3 to be formed on the selection element 11Together serving as the intermediate resistive layer 14. This makes it possible to adjust the resistance value of the intermediate resistance layer 14 to a desired value.

Then, at the opening 48H₄A copper (Cu) film serving as the via V3 and the metal film M4 is formed inside, and then the copper film formed on the interlayer insulating layer 48 is polished by a CMP method to remove the copper film, thereby planarizing the surface. Then, by using the above-described method of manufacturing the via hole V3, the metal film M4, and the memory cell 13, the via hole V4 and the memory element 12 are formed. In this manner, a wiring layer in which the selection element 11 and the memory element 12 are stacked with the via hole V3 in between is formed between the metal film M3 and the metal film M5 shown in fig. 9.

As described above, the intermediate resistive layer 14 may be provided between the selection element 11 and the memory element 12. In the present modification, the opening 48H is used in the manufacturing process₄The resistance value of the intermediate resistance layer 14 can be adjusted to a desired value by adjusting the thickness of the barrier metal film 50 to be formed on the selection element 11 by the difference in depth of (a).

(6-3, modification 3)

Fig. 11A to 11D show another example of a method of manufacturing a wiring layer in which the memory cell 13 of the memory device (memory device 1) according to modification 3 of the present disclosure is formed, in a process sequence.

In the present modification, as shown in fig. 11A, as in modification 2, a barrier film 51 is first formed on a metal film M3 and a word line WL having the same wiring pattern as that of the metal film M3, each of the metal film M3 and the word line WL having a barrier metal film 43 at the periphery thereof, and then a barrier metal film 44 is formed inside the barrier film 51 at a position corresponding to the word line WL. Subsequently, the selection element layer 11X, the memory element layer 12X, the barrier metal film 45, and the hard mask (mask 46) are sequentially formed on the barrier film 51 and the barrier metal film 44.

Next, the selection element layer 11X, the memory element layer 12X, and the barrier metal film 45 are etched using a photolithography method and a dry etching method to form the memory cell 13 on the word line WL. Subsequently, the SiN film 47 is formed on the barrier film 51 and on the side faces and the top surface of the stacked selection element layer 11X, memory element layer 12X, barrier metal film 45, and mask 46. Next, a low-K film is formed on the SiN film 47 using, for example, a CVD method, and then the surface is planarized by a CMP method to form the interlayer insulating layer 48.

Subsequently, by using the damascene method, the via hole V3 and the metal film M4 are formed in the logic section 100A, and the bit line BL is formed in the memory section 100B. First, as shown in fig. 11B, the mask 49 is patterned using a photolithography method, and the opening 48H reaching the barrier film 51 is formed on the metal film M3 provided in the logic portion 100A₅。

Next, as shown in fig. 11C, the mask 49 is first patterned using a photolithography method, and then an opening 48H is formed on each of the metal film M3 and the memory cell 13 by etching₆. Subsequently, by performing etching again, the barrier film 51 on the metal film M3 is etched together with the mask 46 on the memory cell 13. This results in exposure of the metal film M3 and the barrier metal film 45 provided on the memory cell 13.

Finally, as shown in FIG. 11D, at opening 48H₆After forming the barrier metal film 50 on the side and bottom surfaces thereof, a copper (Cu) film serving as the via V3 and the metal film M4 is embedded in the opening 48H₆And the copper film formed on the interlayer insulating layer 48 is polished by a CMP method to remove the copper film, thereby planarizing the surface.

In the manufacturing method described in the first embodiment described above, the process of providing the openings for coupling of the metal film M3 and the via hole V3 in the logic section 100A and coupling of the memory cell 13 (specifically, the barrier metal film 45 provided on the memory cell 13) and the bit line BL in the memory section 100B makes it difficult to simultaneously form such openings due to differences in etching materials or respective film thicknesses.

In contrast, in the present modification, a film (barrier film 51) ensuring the same etching resistance as that of the mask 46 formed on the memory cell 13 is provided in advance on the metal film M3 of the logic portion 100A. This makes it possible to form the opening 48H₆Process for preparing (A) aThis allows enhancement of manufacturing yield.

(6-4, modification 4)

Fig. 12 is a schematic diagram of a cross-sectional configuration of a memory device (memory device 5A) according to modification 4 of the present disclosure. In the memory device 5A of the present modification example, for example, the memory cells 13A and 13B are respectively provided between the metal film M3 and the metal film M4 constituting the first wiring layer 10 and between the metal film M4 and the metal film M5 constituting the first wiring layer 10.

In this way, the present technology allows a plurality of memory cells 13 to be formed between different wiring layers without changing the wiring patterns of the wiring layers constituting the logic circuit 100.

(6-5, modification 5)

Fig. 13 is a schematic diagram of a cross-sectional configuration of a memory device (memory device 5B) according to modification 5 of the present disclosure. In the memory device 5B of the present modification, the memory cells 13A and 13B are provided in the first wiring layer 10 and the second wiring layer 20, respectively.

The memory cells 13A and 13B provided in the memory device 5B of the present modification are different in size according to the design rule of the wiring layer formed. Specifically, the width of each of the selection elements 11 and the memory elements 12 constituting the memory cell 13A formed in the first wiring layer 10 is smaller than the width of each of the selection elements 11 and the memory elements 12 constituting the memory cell 13B formed in the second wiring layer 20. In general, in the case where the thicknesses in the stacking direction are equal, the memory element 12 having a smaller width, i.e., element area exhibits more excellent high-speed operation, and the memory element 12 having a larger element area has higher reliability.

As described above, the memory device 5B having the configuration of the present disclosure allows memory cells 13A and 13B different in characteristics to be mixedly mounted on one substrate 41 without changing the wiring pattern of the wiring layers constituting the logic circuit 100. This allows mixed mounting of the memory units depending on the intended use, which makes it possible to further enhance the functional capability of the memory device 5B.

(6-6, modification 6)

Fig. 14 is a schematic diagram of a cross-sectional configuration of a memory device (memory device 6) according to modification 6 of the present disclosure. The memory device 6 of the present modification has a configuration in which, for example, the barrier metal film 45 provided between the memory cell 13 and the bit line BL in the memory device 1 is formed so as to be intentionally offset from a position on the memory cell 13. The barrier metal film 45 functions as an electrode of the memory cell 13, for example, and forming the barrier metal film 45 in an offset manner results in a reduction in the contact area between the memory cell 13 and the barrier metal film 45 and an increase in the resistance value of the barrier metal film 45. Adjusting the resistance value of the barrier metal film 45 in this manner can reduce degradation of the memory cell 13 caused by an unexpected charging current.

(6-7, modification 7)

Fig. 15 is a schematic diagram of a cross-sectional configuration of a memory device (memory device 7) according to modification 6 of the present disclosure. In the memory device 7 of the present modification, the barrier metal film 44, the memory cell 13, and the barrier metal film 45 provided between the word line EL and the bit line BL in the memory device 1 are formed using, for example, a damascene method.

As shown in fig. 15, in the case where the barrier metal film 44, the selection element 11, the memory element 12, and the barrier metal film 45 are formed in this order inside, for example, the opening 81H formed in the interlayer insulating film 81, for example, using a damascene method, these barrier metal film 44, the selection element 11, the memory element 12, and the barrier metal film 45 are formed in layers on the side surfaces and the bottom surface of the opening 81H. In the case of providing the memory cell having such a configuration, it is necessary to form the bit line BL so as to be in contact with only the innermost barrier metal film 45 formed inside the opening 81H.

In the case where the opening (trench) is filled using the damascene method as described above, since the void is formed in the middle, the relatively thin etching stopper film 83 is formed at the relevant position (middle of the opening). By utilizing this in the present modification, as shown in fig. 15, an etching stopper film 83 is formed on the interlayer insulating film 81, and then the opening 45H is formed using anisotropic etching. This ensures that only the hole portion is etched, thereby making it possible to form the opening H constituting the bit line BL in a self-aligned manner.

Up to this point, the present disclosure has been described with reference to the first to fifth embodiments and modifications 1 to 7 thereof; however, the disclosure is not limited to the above-described embodiments and the like, and may be modified in various ways. For example, the above-described embodiments and the like exemplify a case where the selection element 11 to be configured is disposed on the word line WL side and the memory element 12 is disposed on the bit line BL side. However, this is not limiting; the memory element 12 may be arranged on the word line WL side, and the selection element 11 may be arranged on the bit line BL side.

Further, in any of the memory devices 1, 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6, and 7 of the present disclosure, the position between wiring layers where the memory cell 13 is to be formed is not limited. For example, the memory cell 13 may be formed between the metal film M2 and the metal film M3, or may be formed between the metal film M8 and the metal film M9. In addition, the above-described embodiments and the like exemplify the case where a resistive random access memory element is used as the memory element 12. However, this is not limiting; for example, spin injection memory elements may be used. It is to be noted that the spin injection memory element is difficult to be microfabricated as compared with the resistive random access memory element. Therefore, in the case of using a spin injection memory element, it is preferable to provide the spin injection memory element at any of the via V6 to V9 portions of the second wiring layer 20 or the third wiring layer 30.

It is noted that the effects described herein are merely exemplary. The effects of the present disclosure are not limited to the effects described herein. The present disclosure may have any effect other than those described herein.

Further, for example, the present disclosure may have the following configuration.

(1)

A memory device, comprising:

a logic circuit in which a plurality of layers including wiring layers different in wiring pitch are stacked; and

a memory element disposed between the plurality of wiring layers.

(2)

The memory device according to (1), wherein the selection element and the memory element are provided together between the plurality of wiring layers.

(3)

The memory device according to (1) or (2), wherein,

the logic circuit includes a logic portion and a memory portion in which the memory element is formed, and

the logic section and the memory section have the same wiring structure.

(4)

The memory device according to any one of (1) to (3), wherein, of the plurality of wiring layers, a first wiring layer in which a plurality of wiring layers with a dense wiring pitch are stacked and a second wiring layer in which a plurality of wiring layers with a sparse wiring pitch than that of the first wiring layer are stacked in order.

(5)

The memory device according to (4), wherein

The memory element and the selection element together constitute a memory cell, and

the memory cell is disposed between two wirings stacked in the first wiring layer.

(6)

The memory device according to (4), wherein

The memory element and the selection element together constitute a memory cell, and

in the memory cell, the memory element is provided between one of the wirings stacked in the first wiring layer, and the selection element is provided between the other of the wirings.

(7)

The memory device according to (4) or (5), wherein

The memory element and the selection element together constitute a memory cell, and

the memory cell and the conductive film are stacked between two wirings stacked in the first wiring layer.

(8)

The memory device according to any one of (4), (5) or (7), wherein

The memory element and the selection element together constitute a memory cell, and

the memory cell is disposed between a plurality of wirings within the first wiring layer.

(9)

The memory device according to (4), wherein

The memory element and the selection element together constitute a memory cell, and

the memory cell is disposed across the first wiring layer and the second wiring layer.

(10)

The memory device according to (9), wherein the memory element is disposed on the second wiring layer side, and the selection element is disposed on the first wiring layer side.

(11)

The memory device according to any one of (4) to (10), wherein

The memory element and the selection element together constitute a memory cell, and

the memory cells are respectively disposed between wirings in the first wiring layer and between wirings in the second wiring layer.

(12)

The memory device according to any one of (2) to (11), wherein

Each of the plurality of routing layers includes a plurality of routes, an

A protective film is formed on a side surface of the memory element and the selection element, the memory element and the selection element being provided on one wiring of wiring layers including the plurality of wirings, the protective film being formed in the same wiring layer as the one wiring and being continuous with an etching stopper film provided on a wiring constituting the logic circuit.

(13)

The memory device according to any one of (1) to (12), wherein the memory element is a resistance change memory element or a spin injection memory element.

(14)

A method of manufacturing a memory device, the method comprising:

forming a logic circuit by stacking a plurality of wiring layers including layers different in wiring pitch; and

memory elements are formed between the plurality of wiring layers.

(15)

The method of manufacturing a memory device according to (14), wherein

Each of the plurality of routing layers includes a plurality of routes,

the method comprises the following steps

Forming a memory cell including the memory element and the selection element on one wiring of a wiring layer including the plurality of wirings, an

Thereafter, a via hole connecting between the plurality of wiring layers is formed on another wiring formed in the same wiring layer as the one wiring.

(16)

The method of manufacturing a memory device according to (15), after forming the memory cell on the one wiring, further comprising: an etching stopper film used when forming the through hole on the other wiring and a protective film covering a side surface of the memory element are collectively formed.

(17)

The method of manufacturing a memory device according to (15) or (16), further comprising:

forming the selection element on the one wiring; and is

Thereafter, barrier metal films are collectively formed on the selection element and the other wiring, thereby forming barrier metal films having different film thicknesses on the selection element and the other wiring.

(18)

The method of manufacturing a memory device according to any one of (15) to (17), further comprising: forming an etching stopper film including materials different from each other on one wiring of the wiring layers including the plurality of wirings and on the memory cell.

This application claims priority to japanese prior patent application JP2017-107840, filed on 31.5.2017 with the present patent office, the entire contents of which are incorporated herein by reference.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors so long as they are within the scope of the appended claims or their equivalents.