阅读说明：本技术 半导体装置及半导体芯片 (Semiconductor device and semiconductor chip ) 是由 鹰巢博昭 于 2019-06-25 设计创作，主要内容包括：本发明涉及半导体装置及半导体芯片。半导体装置包括：平坦区域,其形成在半导体衬底的表面,该平坦区域的外周形状具有区域边和区域倒角部；外周区域,其以与平坦区域不同的同样的高度包围平坦区域；多个相似形状或相同形状的半导体元件,它们形成在平坦区域上；及配线金属,其经由形成在半导体元件上的第2绝缘膜的接触孔而将多个半导体元件连接。提供一种能够提高半导体元件的相对精度,并提高半导体集成电路装置的成品率的半导体装置。(The present invention relates to a semiconductor device and a semiconductor chip. The semiconductor device includes: a flat region formed on a surface of the semiconductor substrate, an outer peripheral shape of the flat region having a region side and a region chamfered portion; a peripheral region surrounding the flat region at the same height as the flat region; a plurality of semiconductor elements of similar or identical shape formed on the flat region; and a wiring metal for connecting the plurality of semiconductor elements through the contact hole of the 2 nd insulating film formed on the semiconductor elements. A semiconductor device is provided which can improve the relative accuracy of semiconductor elements and the yield of semiconductor integrated circuit devices.)

1. A semiconductor device, comprising:

a flat region provided on the 1 st insulating film formed on the surface of the semiconductor substrate, the outer peripheral shape of the flat region having a region edge and a region chamfered portion between the region edges in a plan view;

a peripheral region surrounding the flat region and having a height different from that of the flat region;

a plurality of semiconductor elements having a similar shape or a same shape and formed on the flat region at a predetermined distance or more from the outer peripheral region;

a 2 nd insulating film formed on the plurality of semiconductor elements;

a contact hole formed in the 2 nd insulating film on the plurality of semiconductor elements; and

and a wiring metal formed on the contact hole and connecting the plurality of semiconductor elements.

2. The semiconductor device according to claim 1,

the shape of the region chamfered portion is a straight line in a plan view, and an inner angle formed by the region side and the region chamfered portion is an angle exceeding 90 degrees.

3. The semiconductor device according to claim 1,

the shape of the region chamfered portion is a curve that is convex toward the outer peripheral region in a plan view.

4. The semiconductor device according to claim 3,

the shape of the zone edge is a curve which is convex towards the peripheral zone, and the periphery of the flat zone is circular or elliptical.

5. The semiconductor device according to any one of claims 2 to 4,

a conductive film is formed between the semiconductor substrate and the 1 st insulating film under the flat region.

6. The semiconductor device according to any one of claims 2 to 4,

the semiconductor element is a thin film resistor element, and the semiconductor device is a bleeder resistor circuit.

7. A semiconductor chip comprising the semiconductor device according to claim 2 and formed on the semiconductor substrate,

the semiconductor chip includes chip sides divided in a scribe region and chip chamfered portions provided between the chip sides in a plan view,

the chip side is disposed in a direction substantially parallel to the facing area side.

8. The semiconductor chip of claim 7,

when viewed from above, the chip chamfer part is in a straight line shape, and an inner angle formed by the chip side and the chip chamfer part is an angle exceeding 90 degrees.

9. The semiconductor chip of claim 7,

the chip chamfered portion has a shape of a curve which is convex toward the scribe line region in a plan view.

Technical Field

The present invention relates to a semiconductor device and a semiconductor chip.

Background

In many cases, a semiconductor integrated circuit device such as an analog IC mounted on a semiconductor substrate is used in which a plurality of semiconductor elements having the same or similar shape are combined, and the output characteristics are highly accurate by utilizing the high relative accuracy of the plurality of semiconductor elements. For example, the voltage detector compares a divided voltage of a power supply voltage output from a bleeder (bleeder) resistance circuit with a reference voltage by a voltage comparator, and outputs a signal voltage when the power supply voltage reaches a predetermined detection voltage. In general, a bleeder resistor circuit is a circuit in which a plurality of thin film resistor elements having the same shape are combined, and divides an applied voltage in accordance with a ratio of resistance values thereof to output the divided voltage. When the relative accuracy of the thin film resistance element is low, the divided voltage output by the bleeder resistance circuit deviates from a desired value, resulting in a shift in the detection voltage. Therefore, in the bleeder resistance circuit, relative accuracy of the resistance values of the thin film resistance elements for dividing the power supply voltage is extremely important, and for this reason, it is necessary to improve relative accuracy of the shapes of the plurality of thin film resistance elements having the same shape.

Patent document 1 discloses the following technique: the relative accuracy deviation of the resistance value of the thin film resistance element caused by the process deviation of the semiconductor process is predicted according to the characteristic variation trend of the semiconductor integrated circuit device in the semiconductor substrate surface, and the bleeder resistance circuit is adjusted by Trimming (Trimming) according to the relative accuracy deviation, thereby improving the yield of the semiconductor integrated circuit device.

Disclosure of Invention

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor chip in which the following semiconductor device and semiconductor integrated circuit device are formed: the relative accuracy of a plurality of semiconductor elements having the same or similar shape constituting a semiconductor device is improved, and the yield of a semiconductor integrated circuit device can be improved without performing height adjustment or complicated management in fine adjustment or the like.

In order to achieve the above object, the semiconductor device of the present invention employs the following means.

That is, a semiconductor device is characterized by comprising: a flat region provided on the 1 st insulating film formed on the surface of the semiconductor substrate, the outer peripheral shape of the flat region having a region edge and a region chamfered portion between the region edges in a plan view; a peripheral region surrounding the flat region and having a height different from that of the flat region; a plurality of semiconductor elements having a similar shape or a same shape and formed on the flat region at a predetermined distance or more from the outer peripheral region; a 2 nd insulating film formed on the plurality of semiconductor elements; a contact hole formed in the 2 nd insulating film on the plurality of semiconductor elements; and a wiring metal formed on the contact hole and connecting the plurality of semiconductor elements.

According to the present invention, by forming a semiconductor device in which a semiconductor element is formed on a flat region having an outer peripheral shape of a region side and a region chamfered portion, and an outer peripheral region having a height different from that of the flat region is provided on the outer periphery of the flat region, it is possible to improve the relative accuracy of a plurality of semiconductor elements having the same or similar shapes, and to improve the yield of a semiconductor integrated circuit device without height adjustment.

Drawings

Fig. 1 is a schematic plan view of a semiconductor device according to embodiment 1 of the present invention.

Fig. 2 is a schematic cross-sectional view of the semiconductor device of embodiment 1.

Fig. 3 is a circuit diagram of a bleeder resistance circuit constituting the semiconductor device of fig. 1 and 2.

Fig. 4 (a) and 4 (b) are schematic plan views showing the flow of the photoresist applied to the semiconductor substrate in embodiment 1.

Fig. 5 is a circuit block diagram of a voltage detector of an embodiment of the present invention.

Fig. 6 is a circuit block diagram of a voltage regulator of an embodiment of the present invention.

Fig. 7 is a schematic cross-sectional view of a semiconductor device according to embodiment 2 of the present invention.

Fig. 8 (a) and 8 (b) are schematic plan views showing the flow of the photoresist applied to the semiconductor substrate in embodiment 3 of the present invention.

Fig. 9 is a schematic cross-sectional view of the semiconductor device of embodiment 3.

Fig. 10 is a schematic plan view showing a stripe (stripe) of a photoresist applied to a conventional semiconductor substrate.

Fig. 11 (a) and 11 (b) are schematic plan views showing flows of a photoresist applied to a conventional semiconductor substrate.

(symbol description)

1: a power supply terminal; 2: a ground terminal; 3: an output terminal; 10. 20, 30, 40: a semiconductor substrate; 11. 21, 31: a flat region; 11a, 31 a: a zone edge; 11b, 31 b: a region chamfer; 12. 22, 32: a peripheral region; 13. 23, 33: a thin film resistance element; 14: a contact hole; 15a, 15b, 15c, 15 d: a wiring metal; 16. 26, 36: a bleeder resistance circuit; 17. 27, 37: 1 st insulating film; 18. 28, 38: a 2 nd insulating film; 19. 29, 39: a passivation film; 27 a: a conductive film; 27 b: a base insulating film; 91: a reference voltage circuit; 92: a voltage comparator; 93: a P-channel type transistor; 94: an N-channel transistor; 95: an error amplifier; 101. 301, 401: a semiconductor chip; 301 a: chip edge; 301 b: chip chamfering; 102. 302, 402: a Scribe line (Scribe) region; 400: a high step pattern.

Detailed Description

Before describing embodiments of the present invention, in order to facilitate understanding of the embodiments, the inventors of the present invention have found that a film thickness variation of a semiconductor material formed on a semiconductor substrate and composed of a viscous body and an influence on a relative accuracy of a semiconductor element due to the film thickness variation will be described.

Fig. 10 is a schematic plan view showing an appearance of a surface of a semiconductor substrate in a case where streaks are generated when a viscous body such as a photoresist is applied to a surface of a semiconductor substrate 40 by a spin coater in a photolithography process for processing and forming a conventional semiconductor element. In the case of the stripe, a difference in thickness of the photoresist, which occurs when the photoresist is dropped at the center and the stage (stage) is rotated, appears as a difference in texture and color. In fig. 10, regions 410, 420, and 430 are regions where the thickness of the photoresist film is thicker or the variation thereof is larger than in other regions.

When the photoresist film thickness varies, the line width and shape of the resist pattern after processing vary even if the same shape of the photomask pattern is used due to the standing wave effect of the irradiation light during exposure. Therefore, in the formation of a plurality of semiconductor elements having the same or similar shapes, the line widths and shapes vary depending on the variation in resist film thickness on the respective semiconductor elements, and the relative accuracy is lowered. In addition, a shift in output characteristics of a semiconductor device including a plurality of semiconductor elements occurs.

Such variations in photoresist film thickness depend on the level of the step formed on the surface of the semiconductor substrate and the shape of the pattern. Fig. 11 (a) and 11 (b) are schematic plan views showing respective plane patterns of an upper right region 440a and a lower region 440b with respect to the center of the semiconductor substrate 40 shown in fig. 10. For example, when a high step pattern 400 having a height higher than the periphery exists in a semiconductor chip 401 surrounded by a scribe line region 402 of a semiconductor substrate 40, when a photoresist is formed by a spin coater, it is supposed that a stripe as described below appears.

In fig. 11 (a), with respect to the flow of the photoresist of the dotted arrow from the center toward the outer periphery of the semiconductor substrate 40, the corners of the high step pattern 400 face. The flow of the photoresist is branched near the corner, and the flow is disturbed in the outer circumferential direction of the semiconductor substrate 40. The photoresist film thickness greatly varies according to the density of the dotted arrow.

In addition, in fig. 11 (b), since the corners of the high step pattern 400 do not face each other but face each other with respect to the flow of the photoresist indicated by the dotted arrow, the flow of the photoresist is not disturbed. Therefore, the variation in the resist film thickness on and around the high-step pattern 400 is small.

A pattern in a semiconductor integrated circuit is generally formed to be constituted by sides parallel or perpendicular with respect to an Orientation flat (Orientation flat). Therefore, in the regions provided obliquely on the semiconductor substrate 40 on the paper surface, such as the regions 410, 420, and 430 in fig. 10, the pattern corners always face the center of the semiconductor substrate 40, and therefore, variation in the photoresist film thickness is likely to occur. On the other hand, since the corners and the center of the pattern do not face each other at the positions above, below, on the paper surface, and on the left and right of the semiconductor substrate 40, the variation in the photoresist film thickness is less likely to occur.

The variation in the film thickness of the photoresist in the semiconductor device causes variation in line width and shape of a plurality of semiconductor elements having the same photoresist pattern, resulting in a decrease in relative accuracy. The present invention has been developed based on such findings, in order to suppress variation in film thickness of a photoresist on a semiconductor device.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings as appropriate. In order to facilitate understanding of the features of the present invention, some of the drawings used in the following description may be omitted or enlarged and may be different from the actual dimensional ratios.

(embodiment 1)

Next, a semiconductor device according to embodiment 1 will be described.

Fig. 1 is a schematic plan view showing a semiconductor device 100 according to embodiment 1 of the present invention, and shows a part of the characteristic portions in a perspective manner. Fig. 2 is a schematic cross-sectional view of the semiconductor device 100 taken along line a-a' in fig. 1.

The semiconductor device 100 according to embodiment 1 includes a flat region 11 formed on a semiconductor substrate 10, and an outer peripheral region 12 provided around the flat region 11. The flat region 11 has an octagonal outer peripheral shape in plan view, the octagonal outer peripheral shape having 4 region sides 11a and 4 region chamfered portions 11b, and the flat region 11 has a boundary line of 8 sides with respect to the outer peripheral region 12 in the horizontal direction, the vertical direction, and the oblique direction of the paper surface.

Thin film resistance elements 13 made of a plurality of polysilicon having the same shape are formed on the flat region 11 so as to be arranged at regular intervals. The thin-film resistive elements 13 are spaced apart by a distance x in the left-right direction from 8 boundary lines, respectively₁And a distance x₅And is formed to be spaced apart by a distance x in the up-down direction₇And a distance x₃And is formed to be spaced apart in an oblique direction by a distance x₂、x₄、x₆And a distance x₈Thereby forming the composite material. A 2 nd insulating film 18 is formed on the thin film resistance elements 13, and contact holes 14 are formed in the 2 nd insulating film 18 at one end portion and the other end portion of the thin film resistance elements 13. The thin film resistance elements 13 are connected to each other through the contact holes 14 by the wiring metals 15a, 15b, 15c, and 15d, and constitute a bleeder resistance circuit 16. As shown in fig. 2, a passivation film 19 is formed on the 2 nd insulating film 18. Next, the characteristic components of the semiconductor device 100 in embodiment 1 will be described.

As shown in fig. 2, the flat region 11 is formed in the 1 st insulating film 17 at a position higher than the outer peripheral region 12 by the upper surface of a LOCOS (Local Oxidation of Silicon) oxide film as an element separation film. The 1 st insulating film 17 is selected as an element isolation film for insulating and separating the thin film resistive element 13 from the semiconductor substrate 10 and suppressing parasitic capacitance, but is not limited thereto as long as it has the same function.

As shown in fig. 1, the flat region 11 is formed as a planar layout that suppresses the influence of the spin coater in the formation of the photoresist for processing the thin-film resistive element. That is, the corners of the spin coater opposed to the diagonal flow of the photoresist flowing from the center of the semiconductor substrate 10 are excluded, thereby suppressing the turbulence of the flow of the photoresist and the variation in film thickness caused by the turbulence. In the flat region 11, since the inner angle of any corner portion formed by the region side 11a and the region chamfered portion 11b is an obtuse angle of 90 degrees or more, the disturbance of the flow of the resist from other directions can be suppressed.

The outer peripheral region 12 has the same outer peripheral shape as the flat region 11, and seamlessly surrounds the outer periphery of the flat region 11, and is formed to be lower than the flat region 11 by the same height. In fig. 2, the upper surface of the LOCOS oxide film for element separation is defined as a flat region 11, and the outer peripheral region 12 is defined as a LOCOS oxide film non-formation region, so that the height y between the flat region 11 and the outer peripheral region 12 is set to be equal to or greater than the height y of the outer peripheral region 12₁The size of the LOCOS oxide film step is obtained. The outer peripheral region 12 is provided for the following purpose: in the formation of the photoresist for the thin-film resistive element 13, the thickness variation of the resist flowing from the center of the semiconductor substrate through the surface step on the surface of the semiconductor substrate is relaxed by passing through the region having the same height. Therefore, the outer peripheral region 12 may be set to be as high as the flat region.

As shown in fig. 1, the outer side of the outer peripheral region 12 is preferably shaped like the flat region 11, and the sides thereof are preferably arranged parallel to the sides of the outer periphery of the flat region 11, but the invention is not limited thereto. The width of the outer peripheral region 12 may be formed to a width of several μm to ten or several μm to reduce the variation in the film thickness of the photoresist flowing from the center of the semiconductor substrate 10.

The thin film resistor element 13 is formed of a polycrystalline silicon thin film to which conductivity is imparted by introducing an impurity, and has a resistance value determined by the conductivity, width and length thereofA resistive element. In fig. 1, the plurality of thin-film resistive elements are formed to have the same planar shape such as width and length. Accordingly, since each of the resistance elements is equally subjected to shape variations in the etching process of the thin-film resistance element 13, even if the absolute value of the resistance value varies, the resistance ratio between the thin-film resistance elements 13 can be maintained at a constant value based on the shape ratio. Thus, the thin-film resistive element 13 having relatively high accuracy (the resistance ratio is close to the ideal value) effectively improves the yield of the semiconductor integrated circuit device. In addition, in order to ensure a stable photoresist film thickness when forming the thin film resistance elements 13, the thin film resistance elements 13 are spaced from each region side of the flat region 11 by a distance (x)₁～x₈) Is formed to be a predetermined distance or more.

The bleeder resistance circuit 16 is a circuit in which a plurality of thin film resistance elements 13 having the same shape are connected by wiring metals 15a, 15b, 15c, and 15d, and divides an applied voltage into a predetermined ratio to output the divided voltage. Fig. 3 is a circuit diagram of the bleeder resistance circuit 16 in the case where the thin-film resistance elements 13 are connected by the wiring metals 15a, 15b, 15c, and 15 d. When a voltage is applied between the terminal a and the terminal C, a divided voltage value of 1/3, which is an applied voltage value, is output more accurately than the terminal B, based on a ratio of resistance values of the resistors R1 determined by the conductivity and shape of the plurality of thin-film resistive elements 13.

The bleeder resistance circuit 16 is disposed at the center of the flat region 11 and is spaced apart from each side of the octagonal flat region 11 by a distance x₁～x₈Thereby forming the composite material. These distances are provided to alleviate a variation in photoresist film thickness that occurs at a step portion between the flat region 11 and the outer peripheral region 12 in photoresist coating for forming the thin-film resistive element 13.

When the distance from the step portion is sufficiently long, the photoresist film thickness is constant over the thin film resistance element. On the other hand, if the distance is short, the thickness of the photoresist on the thin film resistor element varies, and the width and length of the thin film resistor vary due to the influence of standing waves during exposure. Therefore, it is difficult to form thin film resistors of the same shapeAnd (3) a component. Further, the relative accuracy of the divided voltage output from the bleeder resistance circuit 16 is lowered, and the yield of the semiconductor integrated circuit device is lowered. For stabilizing the shape of the thin-film resistance element 13, the distance x is set₁～x₈When a photoresist is applied to form a thin film resistor element with a sufficient length, it is important that structures such as transistors, wirings, and fuses using a polysilicon thin film are not disposed at all on the flat region 11 and a flat state is maintained.

Distance x required for stabilizing photoresist film thickness₁～x₈The thickness of the photoresist film and the height y shown in FIG. 2₁Is related to the size of (a). That is, as the step becomes smaller, the distance required for stabilizing the film thickness becomes shorter. The distance is related to the thickness of the photoresist film when the thin-film resistive element 13 is formed. Thus, the distance x₁～x₈Based on the selected manufacturing process conditions.

Although not shown, a well region or the like is formed as necessary on the lower surface of the 1 st insulating film 17 in the semiconductor substrate 10, and the resistance value of the thin film resistive element 13 made of polysilicon is stabilized by an electric field effect by fixing the region at a constant potential. The potential of the well region is preferably fixed to, for example, a ground voltage Vss or a power supply voltage Vdd applied to the semiconductor integrated circuit device.

Fig. 4 (a) and 4 (b) are partial schematic plan views of a semiconductor chip 101 on which a semiconductor device 100 having a flat region 11 and an outer peripheral region 12 according to embodiment 1 is mounted, the semiconductor chip being disposed on a semiconductor substrate 10 with a scribe line region 102 therebetween, and only characteristic portions are shown. The positions in the semiconductor substrate 10 in fig. 4 (a) and 4 (b) correspond to the regions 440a and 440b in fig. 10, respectively. As shown in fig. 4 (a), the flat region 11 does not have a 90-degree corner portion facing the photoresist flowing from the diagonally downward left direction indicated by the broken-line arrow, and thus is less likely to cause disturbance in the film thickness distribution as in fig. 4 (b). Therefore, it is possible to improve the uniformity of the photoresist film thickness in the region where the thin film resistance element is to be formed on the flat region 11, and to improve the yield of the semiconductor integrated circuit device while improving the relative accuracy of the plurality of thin film resistance elements.

In order to improve the uniformity of the photoresist film thickness in fig. 4 (a) and the uniformity of the photoresist film thickness in fig. 4 (b) in the same manner, the lengths of the 4 sides in the oblique direction in the flat region 11 and the lengths of the 4 sides in the vertical and horizontal directions are preferably made to be equal to each other. At this time, x in FIG. 1₂、x₄、x₆、x₈Length ratio of (x)₁、x₃、x₅、x₇Is short. Thus, x₂、x₄、x₆、x₈The length of (b) is set to a sufficient length not affected by the variation in the film thickness of the photoresist.

With the above-described configuration, as shown in fig. 4 (a) and 4 (b), in the photolithography step for forming the thin-film resistive element, the uniformity of the photoresist film thickness on the thin-film resistive element at an arbitrary position on the semiconductor substrate can be improved, and the relative accuracy of the thin-film resistive element can be improved.

Next, a semiconductor integrated circuit device in which the semiconductor device according to embodiment 1 is mounted will be described.

Fig. 5 is a schematic circuit block diagram of a voltage detector 101a mounted with the bleeder resistance circuit of embodiment 1.

The voltage detector 101a includes a bleeder resistance circuit 16, a reference voltage circuit 91, a voltage comparator 92, a P-channel transistor 93, and an N-channel transistor 94. And is an analog IC as follows: when the power supply voltage Vdd applied to the power supply terminal 1 fluctuates with respect to the ground voltage Vss applied to the ground terminal 2 and reaches a predetermined detection voltage, the output terminal 3 outputs the output voltage Vout as a detection signal.

The bleeder resistance circuit 16, which receives the power supply voltage Vdd from the terminal a and the ground voltage Vss from the terminal C, outputs the divided voltage of the two voltage differences from the terminal B. The voltage comparator 92 outputs a result of comparison between the divided voltage output from the bleeder resistance circuit 16 and the reference voltage output from the reference voltage circuit 91 as a voltage. The output circuit constituted by the P-channel transistor 93 and the N-channel transistor 94 outputs the output voltage Vout as a detection signal based on the voltage output by the voltage comparator 92. Therefore, by using the bleeder resistance circuit 16 of embodiment 1, the accuracy of voltage division of the power supply voltage can be improved, and the detection accuracy of the voltage detector 101a can be improved.

Fig. 6 is a schematic circuit block diagram of a voltage regulator 101b equipped with the bleeder resistance circuit of embodiment 1.

The voltage regulator 101b includes a bleeder resistance circuit 16, a reference voltage circuit 91, an error amplifier 95, and a P-channel transistor 93. And is an analog IC as follows: even if the power supply voltage Vdd applied to the power supply terminal 1 fluctuates with respect to the ground voltage Vss applied to the ground terminal 2, a predetermined constant voltage is output from the output terminal 3 as the output voltage Vout.

When the output voltage Vout input to the terminal a fluctuates with respect to the ground voltage Vss input to the terminal C, the divided voltage output from the terminal B by the bleeder resistance circuit 16 fluctuates. The error amplifier 95 amplifies the voltage of the difference between the divided voltage and the reference voltage outputted from the reference voltage circuit 91 and outputs the amplified voltage. The error amplifier 95 adjusts the gate voltage of the P-channel transistor 93 in accordance with the output voltage, thereby suppressing the variation of the output voltage Vout. Therefore, by using the bleeder resistance circuit 16 of embodiment 1, the voltage division accuracy of the output voltage Vout can be improved, and the detection accuracy of the voltage regulator 101b can be improved.

As described above, by employing the bleeder resistor circuit according to embodiment 1 in a semiconductor integrated circuit device such as a voltage detector or a voltage regulator, the accuracy of the output voltage can be improved, and the yield of the semiconductor integrated circuit device can be improved.

(embodiment 2)

Next, a semiconductor device according to embodiment 2 will be described.

Fig. 7 is a schematic cross-sectional view showing a semiconductor device 200 according to embodiment 2 of the present invention. The configuration of embodiment 2 is the same as that of fig. 1 in a plan view, and the schematic cross-sectional view of fig. 7 corresponds to a cross-sectional view taken along line a-a' of fig. 1.

The semiconductor device 200 according to embodiment 2 has a region in which the conductive film 27a is formed on the base insulating film 27b formed on the semiconductor substrate 20 as the flat region 21. In addition, the outer peripheral region 22 is provided around the flat region 21, and the conductive film 27a is not formed here. The 1 st insulating film 27 is formed on the conductive film 27a in the flat region 21 and on the outer peripheral region 22. On the flat region 21, thin-film resistance elements 23 made of a plurality of polysilicon having the same shape are formed so as to be arranged at regular intervals. The planar shapes of the flat region 21 and the thin-film resistance element 23 are the same as those of embodiment 1. A 2 nd insulating film 28 is formed on the thin film resistance element 23, and a passivation film 29 is formed on the 2 nd insulating film 28. The plurality of thin-film resistive elements 23 are connected to each other by a wiring metal (not shown) via a contact hole (not shown), and constitute a bleeder resistance circuit 26. Next, in embodiment 2, description will be given centering on the characteristic portions with respect to embodiment 1.

The bleeder resistance circuits 26 are disposed at the center of the flat area 21, and are formed at a distance x from the outer periphery of the flat area 21. These distances are provided to mitigate variations in photoresist film thickness that occur at the step between flat region 21 and outer peripheral region 22 in the spin coater-based photoresist formation for forming thin-film resistive element 23. Such a structure is the same as embodiment 1.

The flat region 21 is a region where a conductive film 27a is formed on a base insulating film 27b such as an element isolation film, and a 1 st insulating film 27 is formed on the conductive film 27 a. Flat area 21 has a height y₂Is provided at a position higher than the outer peripheral region 22 by a height y₂And the thickness of the conductive film 27a is substantially equal.

In embodiment 1, the difference in height between the outer peripheral region 12 and the flat region 11 is limited according to the thickness of the LOCOS oxide film that also serves as the element separation film. However, the difference in height between the outer peripheral region 22 and the flat region 21 in embodiment 2 can be set arbitrarily according to the thickness of the conductive film 27 a. Therefore, embodiment 2 has the following advantages: in forming the thin-film resistive element 23, the degree of freedom is high when the distance x is set so that the photoresist film thickness is constant.

The conductive film 27a is formed on the base insulating film 27b continuous with the outer peripheral region 22, and the base insulating film 27b is not limited to the LOCOS oxide film, and may be another insulating film, thereby providing a high degree of freedom in configuration setting.

The outer peripheral region 22 is a region where the conductive film 27a is not formed, surrounds the entire outer periphery of the flat region 21, and is formed to have the same height as that of the flat region 21. The outer peripheral region 22 has a structure in which the 1 st insulating film 27 is stacked on the base insulating film 27b, and other semiconductor elements may be formed without forming the outer side to have the same shape as the flat region 21, with a distance of several μm to ten and several μm.

When the conductive film 27a is formed using the same material as the gate electrode of a MOS transistor used in a semiconductor integrated circuit device, it is convenient without increasing the number of manufacturing steps. Further, by fixing the potential of the conductive film 27a, the resistance value of the thin-film resistive element 23 made of polysilicon can be stabilized by the electric field effect. For example, the potential of the conductive film 27a is preferably fixed to the ground voltage Vss or the power supply voltage Vdd.

With the above-described configuration, in the photolithography step for forming the thin-film resistive element, as in fig. 4 (a) and 4 (b) in embodiment 1, the uniformity of the photoresist film thickness on the thin-film resistive element can be improved, and the relative accuracy of the thin-film resistive element can be improved. In addition, since the difference in height between the flat area and the outer peripheral area can be set arbitrarily, the distance from the outer periphery of the flat area to the bleeder resistance circuit can be controlled arbitrarily.

(embodiment 3)

Next, the semiconductor device and the semiconductor integrated circuit device according to embodiment 3 will be described.

Fig. 8 (a) and 8 (b) are partial schematic plan views showing characteristic parts of a semiconductor chip 301 mounted with a semiconductor device 300 according to embodiment 3 of the present invention mounted on a semiconductor substrate 30 with a scribe line region 302 interposed therebetween. The positions in the semiconductor substrate 30 in fig. 8 (a) and 8 (b) correspond to the regions 440a and 440b in fig. 10, respectively. Fig. 9 is a schematic cross-sectional view of the semiconductor chip 301 and a part of the scribe line region 302 cut along the line B-B' in fig. 8 (B). Next, embodiment 3 will be described centering on the characteristic portions with respect to embodiment 1.

The semiconductor device 300 has the same structure as that of fig. 1 in a plan view, and includes: a flat region 31 having an octagonal outer peripheral shape with 4 region sides and 4 region chamfered portions; and an outer peripheral region 32 that seamlessly surrounds the flat region 31 and has an outer peripheral shape of an octagon. As shown in fig. 8 (a) and 8 (b), each side of the outer periphery of the outer peripheral region 32 is arranged in parallel with each side of the outer periphery of the flat region 31. As shown in fig. 9, the flat region 31 is formed in the 1 st insulating film 37 at a position higher than the outer peripheral region 32 with the upper surface of the LOCOS oxide film for element separation. The flat region 31 is provided with a thin film resistive element 33, a 2 nd insulating film 38, and a passivation film 39. The thin film resistance elements 33 are connected to each other through a contact hole (not shown) by a wiring metal (not shown) to constitute a bleeder resistance circuit 36. The outer periphery region 32, which is a LOCOS oxide film non-formation region, is surrounded by the LOCOS oxide film.

The semiconductor chip 301 has a semiconductor integrated circuit device formed therein, and as shown in fig. 8 (a), includes a semiconductor device 300, the semiconductor device 300 having a flat region 31, and the flat region 31 has an octagonal shape formed by 4 region sides 31a and 4 region chamfered portions 31 b. The outer peripheral shape of the semiconductor chip 301 is formed in an octagonal shape having 4 chip sides 301a and 4 chip chamfered portions 301b, and has a boundary line of 8 sides with respect to the scribe line region 302 in the horizontal direction, the vertical direction, and the oblique direction of the drawing sheet. The chip side 301a of the semiconductor chip 301 is arranged parallel to the region side 31a of the flat region 31. In addition, the chip chamfered portion 301b of the semiconductor chip 301 is arranged in parallel with the region chamfered portion 31b of the flat region 31.

The scribe line region 302 is a region cut by a dicing blade or the like when the semiconductor chip 301 is singulated. In order to improve the cuttability by dicing, the insulating film on the semiconductor substrate 30 is generally composed of only a minimum necessary film. Therefore, in the scribe line region 302, not the region formed with the LOCOS oxide film but the region not formed with the LOCOS oxide film is used, and the passivation film 39 is additionally removed.

As shown in fig. 8 (a), in the photolithography step for forming the thin-film resistive element, there is no 90-degree corner portion facing the flat region 31 with respect to the flow of the photoresist indicated by the dotted arrow. Therefore, similarly to fig. 8 (b), it is the same as embodiment 1 that the photoresist film thickness distribution on the region where the thin film resistance element is to be formed is less likely to be disturbed.

Further, in embodiment 3, there is no corner portion of the LOCOS oxide film facing the flow of the photoresist indicated by the dotted arrow on the outer periphery of the semiconductor chip 301. Therefore, in fig. 8 (a), the disturbance of the photoresist film thickness distribution occurring before the photoresist reaches the flat region 31 can be suppressed. Therefore, the uniformity of the photoresist film thickness in the area where the thin-film resistive element is to be formed can be further improved. This improves the relative accuracy of the plurality of thin film resistance elements, and improves the yield of the semiconductor integrated circuit device.

In this way, when there is a step having a corner of 90 degrees or less with respect to the photoresist flowing into the semiconductor chip, variation in the film thickness of the photoresist is likely to occur. Therefore, the outer peripheral shape of the semiconductor chip is not limited to the octagonal shape, and if the inner angle formed by the chip side and the chip chamfered portion is an angle exceeding 90 degrees, even in any shape, the variation in the film thickness of the photoresist can be effectively suppressed.

It is to be understood that the present invention is not limited to the above-described embodiments, and various modifications and combinations can be made without departing from the scope of the present invention.

For example, although the flat region 11 of the semiconductor device 100 shown in fig. 1 is formed in an octagonal shape having 4 region chamfered portions and 4 region sides, the same effect can be obtained even if the flat region is formed in a polygonal shape having more corner portions. Alternatively, the shape of the region chamfered portion may be a curve convex toward the outer peripheral region. Further, similarly to the area chamfered portion, the area side may be formed into a curve having a convex shape toward the outer periphery, or may be a flat area having a circular or elliptical outer peripheral shape.

As a matter of course, the shape of the chip chamfered portion in the semiconductor chip may be a curve having a convex shape toward the scribe line region, as in the flat region.

In addition, although the plurality of thin film resistance elements 13 in fig. 1 are all of the same shape, thin film resistance elements of similar shapes having different sizes may be combined. The present invention can exhibit a high effect in a bleeder resistance circuit that outputs a divided voltage by utilizing such a shape ratio of a similar shape.

In the above embodiments, the semiconductor element, the semiconductor device, and the semiconductor integrated circuit device have been described as the thin film resistance element, the bleeder resistance circuit, the voltage detector, and the voltage regulator, respectively, but the invention is not limited thereto. For example, the semiconductor element may be a memory element or an image sensor, and the semiconductor device may be a memory array or an imaging device. That is, the present invention is applicable to a semiconductor device in which it is required to improve the relative accuracy of a plurality of semiconductor elements having the same or similar shapes, and can improve the yield of a semiconductor integrated circuit device including the semiconductor device.