阅读说明：本技术 具有静电放电保护的电子电路 (Electronic circuit with electrostatic discharge protection ) 是由 T·贝德卡尔拉茨 L·德孔蒂 P·加利 于 2019-06-28 设计创作，主要内容包括：一种半导体衬底包括具有上表面的掺杂区。掺杂区可以包括二极管的传导端子(诸如阴极)或晶体管的传导端子(诸如漏极)。在掺杂区处提供硅化物层。该硅化物层具有仅部分覆盖掺杂区的上表面的区域的区域。部分区域覆盖有助于调制集成电路器件的阈值电压和/或漏电流。(A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conductive terminal (such as a cathode) of a diode or a conductive terminal (such as a drain) of a transistor. A silicide layer is provided at the doped region. The silicide layer has a region that only partially covers a region of the upper surface of the doped region. The partial area coverage helps to modulate the threshold voltage and/or leakage current of the integrated circuit device.)

1. An integrated circuit device, comprising:

a semiconductor substrate including a doped region having an upper surface; and

a silicide layer having a region only partially covering a region of the upper surface of the doped region.

2. The integrated circuit device of claim 1, wherein the doped region is one of a source region or a drain region of a MOS-type transistor.

3. The integrated circuit device of claim 1, wherein the doped region is one of an anode or a cathode of a diode.

4. The integrated circuit device of claim 3, wherein a portion of the anode of the diode is covered by a control electrode.

5. The integrated circuit device of claim 1, wherein the doped region forms a cathode of a diode and a drain of a transistor, the diode and the transistor being electrically connected to each other in series.

6. The integrated circuit device of claim 5, wherein the doped region has a dopant atom concentration of 10¹⁷To 10¹⁸Atom/cm³Within the range of (1).

7. The integrated circuit device of claim 5 further comprising another silicide layer having an area that only partially covers an area of an upper surface of another doped region in the semiconductor substrate, the other doped region forming an anode of the diode.

8. The integrated circuit device of claim 5 further comprising another silicide layer having an area that only partially covers an area of an upper surface of another doped region in the semiconductor substrate, the other doped region forming a source of the transistor.

9. The integrated circuit device of claim 5, wherein the diode and the transistor electrically connected in series with each other form a protection circuit against electrostatic discharge effects.

10. The integrated circuit device of claim 1, wherein the thickness of the silicide layer is in the range of 10nm to 30 nm.

11. The integrated circuit device of claim 1, wherein the semiconductor substrate is a semiconductor layer of a silicon-on-insulator structure.

12. The integrated circuit device of claim 11, wherein the silicon-on-insulator structure is an ultra-thin silicon-on-insulator type.

13. The integrated circuit device of claim 1, wherein the region of the upper surface of the doped region is covered by only a single portion of the silicide layer.

14. The integrated circuit device of claim 1, wherein the regions of the upper surface of the doped regions are covered by a plurality of separate portions of the silicide layer.

15. The integrated circuit device of claim 14, wherein the plurality of separate portions are regularly spaced from each other.

16. The integrated circuit device of claim 1, wherein the doped region is part of a protection circuit that protects against electrostatic discharge.

Technical Field

The present disclosure relates generally to electronic circuits, and more particularly to protection circuits against electrostatic discharge effects.

Background

The problems caused by electrostatic discharge become increasingly apparent as the size of components in electronic circuits decreases. Protection of electronic circuits against the effects of electrostatic discharge is an important issue in ensuring reliability and durability of electronic circuits.

Therefore, there is a need for better performing esd protection circuits.

Disclosure of Invention

Drawings

The foregoing and other features and advantages are discussed in detail in the following non-limiting description of specific embodiments, taken in conjunction with the accompanying drawings, wherein:

fig. 1 shows an electrical diagram of a protection circuit against the effects of electrostatic discharges;

FIG. 2 shows a cross-sectional view of an embodiment of the circuit of FIG. 1;

FIG. 3 shows a top view of the embodiment of FIG. 2;

FIG. 4 is a graph showing current versus voltage characteristics for the circuit of FIG. 1;

FIG. 5 is a graph illustrating another current characteristic versus voltage characteristic of the circuit of FIG. 1;

FIG. 6 shows a top view of another embodiment of the circuit of FIG. 1; and

fig. 7 shows a top view of yet another embodiment of the circuit of fig. 1.

Embodiments overcome all or some of the disadvantages of known protection circuits against electrostatic discharge effects.