阅读说明：本技术 可变电阻存储器装置 (Variable resistance memory device ) 是由 金熙中 李基硕 金根楠 黄有商 于 2019-06-27 设计创作，主要内容包括：公开了一种可变电阻存储器装置,所述可变电阻存储器装置包括：第一导线,在与基底的顶表面平行的第一方向上延伸；存储器单元,在第一导线的侧面上沿第一方向彼此隔开并连接到第一导线；以及第二导线,分别连接到存储器单元。每条第二导线在第二方向上与第一导线隔开。第二方向与基底的顶表面平行并且与第一方向交叉。第二导线在与基底的顶表面垂直的第三方向上延伸,并且在第一方向上彼此隔开。每个存储器单元包括可变电阻元件和选择元件,可变电阻元件和选择元件布置在同一水平处并且在第二方向上水平地布置。(Disclosed is a variable resistance memory device including: a first conductive line extending in a first direction parallel to a top surface of the substrate; memory cells spaced apart from each other in a first direction on a side of the first conductive line and connected to the first conductive line; and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart from the first conductive line in the second direction. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a selection element, which are arranged at the same level and horizontally in the second direction.)

1. A variable resistance memory device, the variable resistance memory device comprising:

a first conductive line on the substrate and extending in a first direction parallel to a top surface of the substrate;

a plurality of memory cells arranged at sides of the first conductive line, spaced apart from each other in the first direction, and connected to the first conductive line; and

a plurality of second conductive lines respectively connected to the plurality of memory cells,

wherein the plurality of second conductive lines are spaced apart from the first conductive lines in a second direction that is parallel to the top surface of the substrate and different from the first direction,

wherein each of the plurality of second conductive lines extends in a third direction perpendicular to the top surface of the substrate and is spaced apart from each other in the first direction, and

wherein each of the plurality of memory cells includes a variable resistance element and a selection element, the variable resistance element and the selection element being located at a same level with respect to a top surface of the substrate and being horizontally arranged in the second direction.

2. The variable resistance memory device according to claim 1,

wherein the selection element comprises a semiconductor pattern,

wherein the semiconductor pattern includes a plurality of impurity regions and a channel region between the plurality of impurity regions.

3. The variable resistance memory device according to claim 2,

wherein the plurality of impurity regions have a conductivity type different from a conductivity type of the channel region.

4. The variable resistance memory device according to claim 2, further comprising:

a selection line connected to the selection element,

wherein the semiconductor patterns have first side surfaces facing each other in a first direction, and

wherein the selection lines are disposed on a corresponding one of the first side surfaces and extend in the third direction.

5. The variable resistance memory device according to claim 4,

wherein the select line includes:

a gate electrode adjacent to the channel region of the semiconductor pattern; and

and a gate dielectric layer between the channel region of the semiconductor pattern and the gate electrode.

6. The variable resistance memory device according to claim 4,

the selection lines include a pair of selection lines extending parallel to each other in a third direction, an

The semiconductor pattern is disposed between the pair of selection lines, and the pair of selection lines are respectively disposed on the first side surfaces of the semiconductor pattern.

7. The variable resistance memory device according to claim 1, further comprising:

a plurality of selection lines on the side of the first conductive line,

wherein each of the plurality of select lines is connected to a select element of a corresponding one of the plurality of memory cells, and

wherein the plurality of selection lines extend parallel to each other in the third direction and are spaced apart from each other in the first direction.

8. The variable resistance memory device according to claim 7,

the selection element comprises a semiconductor pattern which is,

the semiconductor pattern includes a plurality of impurity regions and a channel region between the plurality of impurity regions, and

each of the plurality of select lines includes:

a gate electrode adjacent to the channel region of the semiconductor pattern; and

and a gate dielectric layer between the channel region of the semiconductor pattern and the gate electrode.

9. The variable resistance memory device according to claim 7, further comprising:

a shield line between two adjacent memory cells of the plurality of memory cells,

wherein the shield line extends in parallel with the select line in the third direction, the shield line being interposed between two adjacent select lines of the plurality of select lines.

10. The variable resistance memory device according to claim 1,

wherein the variable resistance element includes a magnetic tunnel junction pattern or a phase change material.

11. The variable resistance memory device according to claim 1, further comprising:

a plurality of vertical dielectric patterns formed on the substrate,

wherein each of the plurality of vertical dielectric patterns extends between two adjacent memory cells of the plurality of memory cells, and

wherein the plurality of memory cells and the plurality of vertical dielectric patterns are alternately arranged in a first direction on the side of the first conductive line.

12. The variable resistance memory device according to claim 11,

each of the plurality of vertical dielectric patterns extends between two adjacent second conductive lines of the plurality of second conductive lines, and

the plurality of second conductive lines and the plurality of vertical dielectric patterns are alternately arranged in the first direction.

13. The variable resistance memory device according to claim 1,

wherein each of the plurality of memory cells further comprises an electrode between the variable resistance element and the selection element,

wherein the variable resistance element, the selection element and the electrode are arranged at the same level from the top surface of the substrate and are arranged horizontally in the second direction.

14. A variable resistance memory device, the variable resistance memory device comprising:

a plurality of first conductive lines extending in a first direction parallel to a top surface of the substrate;

a plurality of second conductive lines spaced apart from the plurality of first conductive lines in a second direction, the second direction being parallel to the top surface of the substrate and different from the first direction, the plurality of second conductive lines extending in a third direction perpendicular to the top surface of the substrate and spaced apart from each other in the first direction, and the plurality of first conductive lines being spaced apart from each other in the third direction; and

a plurality of memory cells disposed between the plurality of first conductive lines and the plurality of second conductive lines and spaced apart from each other in the first direction and the third direction,

wherein each of the plurality of memory cells is connected to a corresponding one of the plurality of first conductive lines and a corresponding one of the plurality of second conductive lines, each of the plurality of memory cells includes a variable resistance element and a selection element, the variable resistance element and the selection element being arranged at a same level from a top surface of the substrate and horizontally arranged in a second direction.

15. The variable resistance memory device according to claim 14,

wherein each of the plurality of first conductive lines is commonly connected to a respective horizontal group of the plurality of memory cells, the respective horizontal group including at least two memory cells of the plurality of memory cells, the at least two memory cells being spaced apart from each other in the first direction and arranged at the same level from the top surface of the substrate in the third direction,

wherein each of the at least two memory cells of the respective horizontal group is connected to a respective one of the plurality of second conductive lines.

16. The variable resistance memory device according to claim 14,

wherein the variable resistance element includes a magnetic tunnel junction pattern or a phase change material.

17. The variable resistance memory device according to claim 14, further comprising:

a plurality of selection lines between the plurality of first conductive lines and the plurality of second conductive lines,

wherein the plurality of selection lines extend in the third direction and are spaced apart from each other in the first direction, and

wherein each of the plurality of select lines is commonly connected to a select element of each of at least two memory cells in a respective vertical group of the plurality of memory cells, the at least two memory cells in the respective vertical group being spaced apart from each other in a third direction.

18. The variable resistance memory device according to claim 17,

wherein the selection element comprises a semiconductor pattern,

wherein the semiconductor pattern includes a channel region and a plurality of impurity regions spaced apart from each other in the second direction with the channel region therebetween.

19. The variable resistance memory device according to claim 18,

wherein each of the plurality of select lines comprises:

a gate electrode adjacent to the channel region of the semiconductor pattern; and

and a gate dielectric layer between the channel region of the semiconductor pattern and the gate electrode.

20. The variable resistance memory device according to claim 14,

wherein the selection element comprises an amorphous chalcogenide material.

21. The variable resistance memory device according to claim 14,

wherein each of the plurality of memory cells further comprises an electrode between the variable resistance element and the selection element,

wherein the variable resistance element, the selection element and the electrode are arranged at the same level from the top surface of the substrate and are arranged horizontally in the second direction.

22. The variable resistance memory device according to claim 14,

wherein each of the plurality of second conductive lines is commonly connected to a respective vertical group of the plurality of memory cells, the respective vertical group including at least two memory cells spaced apart from each other in a third direction,

wherein each of the at least two memory cells in the respective vertical group is connected to a respective one of the plurality of first conductive lines.

23. A variable resistance memory device, the variable resistance memory device comprising:

a first conductive line on the substrate and extending in a first direction parallel to a top surface of the substrate;

a plurality of memory cells and a plurality of vertical dielectric patterns alternately arranged in a first direction on a side surface of the first conductive line, each of the plurality of memory cells including a variable resistance element and a selection element, the variable resistance element and the selection element being horizontally arranged in a second direction parallel to the top surface of the substrate and crossing the first direction; and

a plurality of second conductive lines respectively connected to the plurality of memory cells,

wherein the plurality of second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction.

24. The variable resistance memory device according to claim 23,

the plurality of second conductive lines are spaced apart from the first conductive lines in the second direction, and

the variable resistance element and the selection element included in each of the plurality of memory cells are interposed between the first conductive line and a corresponding one of the plurality of second conductive lines.

25. The variable resistance memory device according to claim 23,

each of the plurality of vertical dielectric patterns extends between two adjacent second conductive lines of the plurality of second conductive lines, and

the plurality of vertical dielectric patterns and the plurality of second conductive lines are alternately arranged in a first direction.

Technical Field

The present inventive concept relates to a variable resistance memory device, and more particularly, to a variable resistance memory device having memory cells arranged three-dimensionally.

Background

Semiconductor devices have been highly integrated to meet customer demands for high performance and low manufacturing cost. Since the degree of integration of semiconductor devices is an important factor in determining the price of products, the demand for high integration is increasing. The degree of integration of a typical two-dimensional or planar semiconductor device is largely determined by the area occupied by a unit memory cell, so that it is greatly influenced by the state of the art for forming fine patterns. However, the extremely expensive processing equipment required to increase the fineness of the pattern may place practical limits on increasing the integration of two-dimensional or planar semiconductor devices. In order to overcome the above limitations, three-dimensional semiconductor devices having memory cells arranged three-dimensionally have been proposed. In order to meet the trend of high performance and low power consumption of semiconductor memory devices, next generation semiconductor memory devices, such as MRAM (magnetic random access memory) and PRAM (phase change random access memory), are currently being developed.

Disclosure of Invention

Some example embodiments of the inventive concepts provide a variable resistance memory device having an increased degree of integration and a method of manufacturing the same.

According to some example embodiments of the inventive concepts, a variable resistance memory device includes: a first conductive line on the substrate and extending in a first direction parallel to a top surface of the substrate; a plurality of memory cells arranged spaced apart from each other in a first direction on a side of the first conductive line and connected to the first conductive line; and a plurality of second conductive lines respectively connected to the plurality of memory cells. Each second conductive line is spaced apart from the first conductive line in the second direction. The second direction is parallel to the top surface of the substrate and intersects the first direction. The plurality of second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a selection element, which are arranged at the same level from the top surface of the substrate and horizontally in the second direction.

According to some example embodiments of the inventive concepts, a variable resistance memory device includes: a plurality of first conductive lines extending in a first direction parallel to a top surface of the substrate; a plurality of second conductive lines spaced apart from the plurality of first conductive lines in a second direction, the second direction being parallel to the top surface of the substrate and different from the first direction, the plurality of second conductive lines extending in a third direction perpendicular to the top surface of the substrate and spaced apart from each other in the first direction, the plurality of first conductive lines being spaced apart from each other in the third direction; and a plurality of memory cells between the plurality of first conductive lines and the plurality of second conductive lines, and the plurality of memory cells are spaced apart from each other in the first direction and the third direction. Each memory cell is connected to a respective one of the plurality of first conductive lines and a respective one of the plurality of second conductive lines. Each memory cell includes a variable resistance element and a selection element, which are arranged at the same level from the top surface of the substrate and horizontally in the second direction.

According to some example embodiments of the inventive concepts, a variable resistance memory device includes: a first conductive line on the substrate and extending in a first direction parallel to a top surface of the substrate; a plurality of memory cells and a plurality of vertical dielectric patterns alternately arranged in a first direction on a side surface of the first conductive line, each memory cell including a variable resistance element and a selection element horizontally arranged in a second direction parallel to the top surface of the substrate and different from the first direction; and a plurality of second conductive lines respectively connected to the plurality of memory cells. The plurality of second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction.

Drawings

Fig. 1 illustrates a simplified perspective view showing a variable resistance memory device according to some example embodiments of the inventive concepts.

Fig. 2A illustrates a plan view showing the variable resistance memory device of fig. 1.

Fig. 2B shows a cross-sectional view taken along line I-I' of fig. 2A.

Fig. 3 illustrates a plan view showing a variable resistance memory device according to some example embodiments of the inventive concepts.

Fig. 4A, 4B and 4C show cross-sectional views taken along the line a-a ', the line B-B ' and the line C-C ' of fig. 3, respectively.

Fig. 5, 7, 9, 11, 13, and 15 illustrate plan views illustrating methods of manufacturing a variable resistance memory device according to some example embodiments of the inventive concepts.

Fig. 6A, 8A, 10A, 12A, 14A and 16A show cross-sectional views taken along the line a-a' of fig. 5, 7, 9, 11, 13 and 15, respectively.

Fig. 6B, 8B, 10B, 12B, 14B and 16B show cross-sectional views taken along the line B-B' of fig. 5, 7, 9, 11, 13 and 15, respectively.

Fig. 10C, 12C, 14C and 16C show cross-sectional views taken along line C-C' of fig. 9, 11, 13 and 15, respectively.

Fig. 17 illustrates a simplified perspective view showing a variable resistance memory device according to some example embodiments of the inventive concepts.

Fig. 18A illustrates a plan view showing the variable resistance memory device of fig. 17.

Fig. 18B shows a cross-sectional view taken along line I-I' of fig. 18A.

Fig. 19 illustrates a simplified perspective view showing a variable resistance memory device according to some example embodiments of the inventive concepts.

Fig. 20A illustrates a plan view showing the variable resistance memory device of fig. 19.

Fig. 20B shows a cross-sectional view taken along line I-I' of fig. 20A.

Fig. 21 illustrates a simplified perspective view showing a variable resistance memory device according to some example embodiments of the inventive concepts.

Fig. 22A illustrates a plan view showing the variable resistance memory device of fig. 21.

Fig. 22B shows a cross-sectional view taken along line I-I' of fig. 22A.

Fig. 23 illustrates a simplified perspective view showing a variable resistance memory device according to some example embodiments of the inventive concepts.

Fig. 24A illustrates a plan view showing the variable resistance memory device of fig. 23.

Fig. 24B shows a cross-sectional view taken along line I-I' of fig. 24A.

Fig. 25 illustrates a plan view showing a variable resistance memory device according to some example embodiments of the inventive concepts.

Fig. 26A shows a cross-sectional view taken along line a-a' of fig. 25.

Fig. 26B shows a cross-sectional view taken along line B-B' of fig. 25.

Detailed Description

Some exemplary embodiments of the inventive concept will now be described in detail below with reference to the accompanying drawings.

Fig. 1 illustrates a simplified perspective view showing a variable resistance memory device according to some example embodiments of the inventive concepts. Fig. 2A illustrates a plan view showing the variable resistance memory device of fig. 1. Fig. 2B shows a cross-sectional view taken along line I-I' of fig. 2A.

Referring to fig. 1, 2A and 2B, the substrate 100 may be provided thereon with a first conductive line CL1 and a second conductive line CL2 crossing the first conductive line CL 1. The first conductive line CL1 may extend in a first direction D1 parallel to the top surface 100U of the substrate 100. The second conductive line CL2 may be spaced apart from the first conductive line CL1 in a second direction D2 parallel to the top surface 100U of the substrate 100 and different from the first direction D1 while extending in a third direction D3 perpendicular to the top surface 100U of the substrate 100. The first conductive lines CL1 may be spaced apart from each other in the third direction D3, and the second conductive lines CL2 may be spaced apart from each other in the first direction D1.

The memory cells MC may be disposed between the first and second conductive lines CL1 and CL2, and may be spaced apart from each other in the first and third directions D1 and D3. The memory cells MC may be disposed at respective intersections between the first conductive lines CL1 and the second conductive lines CL 2. Each of the first conductive lines CL1 may be commonly connected to a plurality of memory cells MC spaced apart from each other in the first direction D1, and the plurality of memory cells MC may be connected to a corresponding second conductive line CL 2. Each of the second conductive lines CL2 may be commonly connected to a plurality of memory cells MC spaced apart from each other in the third direction D3, and the plurality of memory cells MC may be connected to a corresponding first conductive line CL 1. Each memory cell MC may be disposed between a corresponding one of the first conductive lines CL1 and a corresponding one of the second conductive lines CL2, and may be connected to a corresponding first conductive line CL1 and a corresponding second conductive line CL 2.

Each memory cell MC may include a variable resistance element VR and a selection element SW. The variable resistive elements VR and the selection elements SW may be horizontally arranged in the second direction D2, and may be connected in series between the respective first conductive lines CL1 and the respective second conductive lines CL 2. The variable resistive element VR may include a material that stores data based on a change in resistance. In some embodiments, the variable resistive element VR may include a magnetic tunnel junction pattern, which may include a fixed layer whose magnetization direction is fixed in one direction, a free layer whose magnetization direction may be switched parallel or anti-parallel to the magnetization direction of the fixed layer, and a tunnel barrier layer between the fixed layer and the free layer. In this case, the memory cell MC may include a Magnetic Random Access Memory (MRAM) cell. In other embodiments, the variable resistive element VR may include a material that may reversibly change its phase between a crystalline state and an amorphous state based on temperature. For example, the variable resistance element VR may include a compound In which one or more of Te and Se (chalcogen) is combined with one or more of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, and C. The variable resistance element VR may include one or more of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and InSbTe, or a superlattice structure in which a Ge-containing layer (e.g., GeTe layer) and a Ge-free layer (e.g., SbTe layer) are repeatedly stacked. In this case, the memory cell MC may include a phase change random access memory (PRAM) cell. In an embodiment of the inventive concept, the memory cells MC may be arranged in three dimensions. For example, the memory cells MC may be arranged in a plurality of horizontal groups and a plurality of vertical groups. In this case, each memory cell may be associated with a respective one of the horizontal groups and a respective one of the vertical groups. A plurality of horizontal groups may be vertically (i.e., in a third direction) stacked on the top surface of the substrate 100. Each of the plurality of horizontal groups may include at least two memory cells commonly connected to a corresponding one of the first conductive lines CL 1. In this case, each of the at least two memory cells in each horizontal group may be connected to a corresponding one of the second conductive lines CL 2. Each horizontal group and a corresponding one of the first conductive lines CL1 may be disposed at the same level from the top surface of the substrate 100. The plurality of vertical groups may be arranged spaced apart from each other in the first direction. Each of the plurality of vertical groups may include at least two memory cells stacked on each other in the third direction. At least two memory cells in each of the plurality of vertical groups may be commonly connected to a corresponding one of the second conductive lines CL 2. Each of the at least two memory cells in each vertical group may be connected to a corresponding one of first conductive lines CL 1.

In some embodiments, the selection element SW may include a semiconductor pattern SP. The semiconductor pattern SP may include a first impurity region SD1, a second impurity region SD2, and a channel region CH between the first impurity region SD1 and the second impurity region SD 2. The first impurity region SD1, the second impurity region SD2, and the channel region CH may be horizontally arranged in the second direction D2, and the first impurity region SD1 and the second impurity region SD2 may be spaced apart from each other in the second direction D2 with the channel region CH interposed therebetween. The semiconductor pattern SP may further include a first sub-impurity region L1 between the first impurity region SD1 and the channel region CH, and may further include a second sub-impurity region L2 between the second impurity region SD2 and the channel region CH. The first impurity region SD1 and the first sub-impurity region L1 may have a different conductivity type from the channel region CH, and the first impurity region SD1 may have an impurity concentration greater than that of the first sub-impurity region L1. The second impurity region SD2 and the second sub-impurity region L2 may have a different conductivity type from the channel region CH, and the second impurity region SD2 may have an impurity concentration greater than that of the second sub-impurity region L2. The first and second impurity regions SD1 and SD2 and the first and second sub-impurity regions L1 and L2 may have the same conductivity type. The semiconductor pattern SP may include, for example, silicon, germanium, silicon germanium, or Indium Gallium Zinc Oxide (IGZO). The first and second impurity regions SD1 and SD2 and the first and second sub-impurity regions L1 and L2 may include, for example, N-type impurities or P-type impurities.

Each memory cell MC may further include an electrode EP between the variable resistance element VR and the selection element SW. The electrode EP may electrically connect the variable resistance element VR and the selection element SW to each other, and may prevent direct contact between the variable resistance element VR and the selection element SW. The electrode EP may comprise a conductive material, such as one or more of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN and TiO. In some embodiments, each memory cell MC may further include a first ohmic pattern S1 between the selection element SW and the corresponding first conductive line CL1 (or the corresponding second conductive line CL2), a second ohmic pattern S2 between the selection element SW and the electrode EP, a third ohmic pattern S3 between the electrode EP and the variable resistance element VR, and a fourth ohmic pattern S4 between the variable resistance element VR and the corresponding second conductive line CL2 (or the corresponding first conductive line CL 1). The first to fourth ohmic patterns S1 to S4 may include a metal silicide.

The select line SWL may be disposed between the first conductive line CL1 and the second conductive line CL2, and may be connected to the memory cell MC. The selection lines SWL may extend in the third direction D3 and may be spaced apart from each other in the first direction D1. Each of the select lines SWL may be commonly connected to the respective memory cells MC spaced apart from each other in the third direction d 3. Each of the selection lines SWL may be connected to a selection element SW (e.g., a semiconductor pattern SP) of each of the corresponding memory cells MC. The semiconductor patterns SP may have side surfaces LS facing each other in the first direction D1, and each of the selection lines SWL may be disposed on a corresponding one of the side surfaces LS of the semiconductor patterns SP. Each of the selection lines SWL may include a gate electrode GE adjacent to the channel region CH of the semiconductor pattern SP, and may further include a gate dielectric layer GI between the gate electrode GE and the channel region CH of the semiconductor pattern SP. In some embodiments, the semiconductor pattern SP of each memory cell MC may be disposed between a pair of selection lines SWL among the selection lines SWL. A pair of selection lines SWL may be disposed on the respective side surfaces LS of the semiconductor patterns SP. In this case, the pair of selection lines SWL may be configured to receive the same voltage. In an example embodiment, each of the first conductive lines CL1 may be electrically connected to the corresponding variable resistance element VR according to whether the switching element SW is turned on or not. Each of the second conductive lines CL2 may be electrically connected to a corresponding variable resistance element VR. In example embodiments, each second conductive line CL2 may be in contact with a corresponding variable resistance element VR, or a conductive material may be interposed between each second conductive line CL2 and a corresponding variable resistance element VR. In this case, the first conductive line CL1 may be referred to as a bit line through which data may be written to or read from the memory cell MC. The second conductive line CL2 may be referred to as a common electrode.

Fig. 3 illustrates a plan view showing a variable resistance memory device according to some example embodiments of the inventive concepts. Fig. 4A, 4B and 4C show cross-sectional views taken along lines a-a ', B-B ' and C-C ' of fig. 3, respectively.

Referring to fig. 3, 4A, 4B, and 4C, a stacked structure SS may be disposed on the substrate 100. The substrate 100 may include a semiconductor substrate. The substrate 100 may further include a thin layer formed on the semiconductor substrate, but the inventive concept is not limited thereto. The stacked structure SS may extend in a first direction D1 parallel to the top surface 100U of the substrate 100. The substrate 100 may be provided thereon with the isolation dielectric patterns 130 on opposite sides of the stacked structure SS. The isolation dielectric pattern 130 may accordingly cover the opposite side surface SS _ S of the stacked structure SS. The isolation dielectric patterns 130 may extend in a first direction D1, and may be spaced apart from each other in a second direction D2 parallel to the top surface 100U of the substrate 100 and different from the first direction D1. The isolation dielectric patterns 130 may be spaced apart from each other in the second direction D2 through the stacked structure SS. The isolation dielectric pattern 130 may include, for example, one or more of oxide, nitride, and oxynitride.

The stacked structure SS may include the dielectric layers 110 and the first conductive lines CL1 alternately stacked in a third direction D3 perpendicular to the top surface 100U of the substrate 100. The lowermost one of the dielectric layers 110 may be interposed between the substrate 100 and the lowermost one of the first conductive lines CL1, but the inventive concept is not limited thereto.

The first conductive line CL1 may extend in the first direction D1. The first conductive line CL1 may include a first sub-conductive line CL1a and a second sub-conductive line CL1 b. The first sub-wires CL1a may extend in the first direction D1 and be spaced apart from each other in the third direction D3. The first sub-conductive lines CL1a may be separated from each other by a dielectric layer 110 therebetween. The second sub-wires CL1b may extend in the first direction D1 and be spaced apart from each other in the third direction D3. The second sub-conductive lines CL1b may be separated from each other by a dielectric layer 110 therebetween. The second sub-conductive line CL1b may be spaced apart from the first sub-conductive line CL1a in the second direction D2. One of the isolation dielectric patterns 130 may cover a side surface of the first sub-conductive line CL1a and a side surface of the dielectric layer 110 between the first sub-conductive lines CL1 a. Another one of the isolation dielectric patterns 130 may cover a side surface of the second sub-conductive line CL1b and a side surface of the dielectric layer 110 between the second sub-conductive lines CL1 b. One of the first sub-conductive lines CL1a and one of the second sub-conductive lines CL1b may be horizontally spaced apart from each other in the second direction D2 on a corresponding one of the dielectric layers 110.

The stack structure SS may include a second conductive line CL2 between the first sub-conductive line CL1a and the second sub-conductive line CL1 b. The second conductive lines CL2 may extend in the third direction D3 and be spaced apart from each other in the first direction D1. The second conductive line CL2 may cross the first sub-conductive line CL1a and the second sub-conductive line CL1 b. Each of the second conductive lines CL2 may penetrate the dielectric layer 110. First and second conductive lines CL1 and CL2 may include one or more of a metal (e.g., copper, tungsten, or aluminum) and a metal nitride (e.g., tantalum nitride, titanium nitride, or tungsten nitride). Dielectric layer 110 may comprise, for example, silicon nitride.

The stacked structure SS may include the vertical dielectric pattern 120 between the first sub-conductive line CL1a and the second sub-conductive line CL1 b. The vertical dielectric patterns 120 may extend in the third direction D3 and be spaced apart from each other in the first direction D1. The second conductive line CL2 and the vertical dielectric pattern 120 may be alternately arranged in the first direction D1 between the first sub-conductive line CL1a and the second sub-conductive line CL1 b. Each of the second conductive lines CL2 may be interposed between the vertical dielectric patterns 120 adjacent to each other in the first direction D1. Each of the vertical dielectric patterns 120 may have a linear shape extending in the second direction D2 when viewed on a plane. Each of the vertical dielectric patterns 120 may penetrate the dielectric layer 110. The vertical dielectric pattern 120 may include, for example, one or more of oxide, nitride, and oxynitride.

The stack structure SS may include memory cells MC located at respective intersections between the first conductive lines CL1 and the second conductive lines CL 2. The memory cells MC may include first memory cells MC1 at respective intersections between the first sub-conductive lines CL1a and the second conductive lines CL2, and further include second memory cells MC2 at respective intersections between the second sub-conductive lines CL1b and the second conductive lines CL 2. The first memory cells MC1 may be spaced apart from each other in the first and third directions D1 and D3 between the first sub-conductive line CL1a and the second conductive line CL 2. Each of the first sub-conductive lines CL1a may be commonly connected to the corresponding first memory cells MC1 spaced apart from each other in the first direction D1, and the corresponding first memory cells MC1 may be connected to the corresponding second conductive line CL 2. The first memory cells MC1 spaced apart in the first direction D1 may be separated from each other by the vertical dielectric patterns 120 therebetween. Each of the second conductive lines CL2 may be commonly connected to the corresponding first memory cells MC1 spaced apart from each other in the third direction D3, and the corresponding first memory cells MC1 may be connected to the corresponding first sub-conductive line CL1 a. The first memory cells MC1 spaced apart in the third direction D3 may be separated from each other by the dielectric layer 110 therebetween.

The second memory cells MC2 may be spaced apart from each other in the first and third directions D1 and D3 between the second sub-conductive line CL1b and the second conductive line CL 2. Each of the second sub-conductive lines CL1b may be commonly connected to the corresponding second memory cells MC2 spaced apart from each other in the first direction D1, and the corresponding second memory cells MC2 may be connected to the corresponding second conductive line CL 2. The second memory cells MC2 spaced apart in the first direction D1 may be separated from each other by the vertical dielectric patterns 120 therebetween. Each of the second conductive lines CL2 may be commonly connected to the corresponding second memory cells MC2 spaced apart from each other in the third direction D3, and the corresponding second memory cells MC2 may be connected to the corresponding second sub-conductive lines CL1 b. The second memory cells MC2 spaced apart in the third direction d3 may be separated from each other by the dielectric layer 110 therebetween. The second memory cell MC2 may be spaced apart from the first memory cell MC1 in the second direction D2.

Each memory cell MC may include a variable resistance element VR, a selection element SW, and an electrode EP between the variable resistance element VR and the selection element SW. The variable resistance element VR, the selection element SW, and the electrode EP may be horizontally arranged in a direction (e.g., the second direction D2) parallel to the top surface 100U of the substrate 100. Each memory cell MC may be locally disposed between a pair of vertical dielectric patterns 120 adjacent to each other in the first direction D1 and between a pair of dielectric layers 110 adjacent to each other in the third direction D3. Accordingly, the variable resistance element VR, the selection element SW, and the electrode EP may be horizontally arranged between the pair of vertical dielectric patterns 120 and between the pair of dielectric layers 110. The variable resistance element VR and the selection element SW included in each of the first memory cells MC1 may be connected in series between the corresponding first sub-conductive line CL1a and the corresponding second conductive line CL 2. The variable resistance element VR and the selection element SW included in each of the second memory cells MC2 may be connected in series between the corresponding second sub-conductive line CL1b and the corresponding second conductive line CL 2.

The memory cells MC may include a pair of memory cells MC spaced apart from each other in the second direction D2 by the respective second conductive lines CL 2. The pair of memory cells MC may include one of the first memory cells MC1 and one of the second memory cells MC 2. The pair of memory cells MC may be commonly connected to the corresponding second conductive line CL2, one of the pair of memory cells MC may be connected to the corresponding first sub-conductive line CL1a, and the other of the pair of memory cells MC may be connected to the corresponding second sub-conductive line CL1 b. The respective second conductive lines CL2 and the pair of memory cells MC connected thereto may be arranged in the second direction D2 on one surface of the respective vertical dielectric patterns 120. For example, the respective second conductive lines CL2 and the pair of memory cells MC connected thereto may be arranged between the vertical dielectric patterns 120 adjacent to each other in the first direction D1 in the second direction D2.

The second memory cell MC2 may be configured symmetrically with the first memory cell MC1 with respect to the second conductive line CL 2. For example, a pair of memory cells MC may be symmetrical to each other about the corresponding second conductive line CL 2. In some embodiments, the variable resistive element VR of the first memory cell MC1 and the variable resistive element VR of the second memory cell MC2 may be commonly connected to the corresponding second conductive line CL2, and the selection element SW of the first memory cell MC1 and the selection element SW of the second memory cell MC2 may be connected to the corresponding first sub-conductive line CL1a and the corresponding second sub-conductive line CL1b, respectively. In other embodiments, unlike as shown, the selection element SW of the first memory cell MC1 and the selection element SW of the second memory cell MC2 may be commonly connected to the corresponding second conductive line CL2, and the variable resistance element VR of the first memory cell MC1 and the variable resistance element VR of the second memory cell MC2 may be connected to the corresponding first sub-conductive line CL1a and the corresponding second sub-conductive line CL1b, respectively.

As discussed with reference to fig. 1, 2A, and 2B, the variable resistive element VR may include a material that stores data based on a change in resistance. The selection element SW may include a semiconductor pattern SP. The semiconductor pattern SP may include a first impurity region SD1, a second impurity region SD2, and a channel region CH between the first impurity region SD1 and the second impurity region SD 2. The electrode EP may be disposed between the variable resistance element VR and the semiconductor pattern SP. Each memory cell MC may be configured substantially the same as the memory cells MC discussed with reference to fig. 1, 2A, and 2B.

The gate electrode GE may be disposed in the vertical dielectric pattern 120. Each of the gate electrodes GE may have a linear shape extending in the third direction D3 and penetrate a corresponding one of the vertical dielectric patterns 120. The gate electrode GE may extend in the third direction D3 and be parallel to the second conductive line CL 2. The gate electrode GE may include a first gate electrode GE1 adjacent to the first memory cell MC1 and a second gate electrode GE2 adjacent to the second memory cell MC 2. The first gate electrodes GE1 may extend in the third direction D3 and may be spaced apart from each other in the first direction D1. Each of the first gate electrodes GE1 may penetrate a corresponding one of the vertical dielectric patterns 120 and may be disposed adjacent to a corresponding first memory cell MC1 spaced apart from each other in the third direction D3. Each of the first gate electrodes GE1 may be adjacent to the semiconductor pattern SP (e.g., the channel region CH) of each of the first memory cells MC1 spaced apart from each other in the third direction D3. The semiconductor pattern SP may have side surfaces LS facing each other in the first direction D1, and each of the first gate electrodes GE1 may be disposed on a corresponding one of the side surfaces LS of the semiconductor pattern SP. In some embodiments, the semiconductor pattern SP of each of the first memory cells MC1 may be disposed between a pair of the first gate electrodes GE 1. A pair of first gate electrodes GE1 may be disposed on the respective side surfaces LS of the semiconductor pattern SP. In this case, the pair of first gate electrodes GE1 may be configured to receive the same voltage.

The second gate electrodes GE2 may extend in the third direction D3 and be spaced apart from each other in the first direction D1. Each of the second gate electrodes GE2 may penetrate a corresponding one of the vertical dielectric patterns 120 and may be adjacent to a corresponding second memory cell MC2 spaced apart from each other in the third direction D3. Each of the second gate electrodes GE2 may be adjacent to the semiconductor pattern SP (e.g., the channel region CH) of each of the second memory cells MC2 spaced apart from each other in the third direction D3. Each of the second gate electrodes GE2 may be disposed on a corresponding one of the side surfaces LS of the semiconductor pattern SP. In some embodiments, the semiconductor pattern SP of each of the second memory cells MC2 may be disposed between a pair of the second gate electrodes GE 2. A pair of second gate electrodes GE2 may be disposed on the respective side surfaces LS of the semiconductor pattern SP. In this case, the pair of second gate electrodes GE2 may be configured to receive the same voltage.

The gate dielectric layer GI may be interposed between each gate electrode GE and the semiconductor pattern SP of each memory cell MC corresponding to the gate electrode GE. Gate dielectric layer GI may extend in third direction D3 and may be interposed between each gate electrode GE and dielectric layer 110 corresponding to gate electrode GE. The gate dielectric layer GI may extend between each vertical dielectric pattern 120 and the memory cell MC corresponding to the vertical dielectric pattern 120 and between each vertical dielectric pattern 120 and the dielectric layer 110 corresponding to the vertical dielectric pattern 120. The gate dielectric layer GI may extend between each vertical dielectric pattern 120 and the second conductive line CL2 corresponding to the vertical dielectric pattern 120. The gate dielectric layer GI may have a ring shape surrounding each of the vertical dielectric patterns 120 when viewed in a plane. The selection line SWL may be composed of one of the gate electrodes GE and a portion of the gate dielectric layer GI adjacent to the one of the gate electrodes GE. For example, the first selection line SWL1 may be composed of one of the first gate electrodes GE1 and a portion of the gate dielectric layer GI adjacent to one of the first gate electrodes GE1, and the second selection line SWL2 may be composed of one of the second gate electrodes GE2 and a portion of the gate dielectric layer GI adjacent to one of the second gate electrodes GE 2.

The gate electrode GE may include one or more of a metal (tungsten, titanium, tantalum, etc.) and a conductive metal nitride (titanium nitride, tantalum nitride, etc.), and the gate dielectric layer GI may include one or more of a high-k dielectric layer, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. For example, the high-k dielectric layer may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, scandium lead tantalum oxide, and lead zinc niobate.

In some embodiments, the shield line SM may be disposed in each of the vertical dielectric patterns 120. One of the shield lines SM may be disposed between the first gate electrodes GE1 adjacent to each other in the first direction D1 in each of the vertical dielectric patterns 120, and the other of the shield lines SM may be disposed between the second gate electrodes GE2 adjacent to each other in the first direction D1 in each of the vertical dielectric patterns 120. The shield wires SM may each have a linear shape extending in the third direction D3. The shield line SM may prevent coupling between the adjacent gate electrodes GE and may be connected to one or more nodes to which a ground voltage is applied. The shield wire SM may include metal.

According to the concept of the present invention, each memory cell MC may include a variable resistance element VR and a selection element SW horizontally arranged in a direction (e.g., the second direction D2) parallel to the top surface 100U of the substrate 100. Therefore, it is possible to easily stack the memory cells MC three-dimensionally on the substrate 100 and form the memory cells MC. In summary, the variable resistance memory device can easily increase the integration degree.

Fig. 5, 7, 9, 11, 13, and 15 illustrate plan views illustrating methods of manufacturing a variable resistance memory device according to some example embodiments of the inventive concepts. Fig. 6A, 8A, 10A, 12A, 14A and 16A show cross-sectional views taken along the line a-a' of fig. 5, 7, 9, 11, 13 and 15, respectively. Fig. 6B, 8B, 10B, 12B, 14B and 16B show cross-sectional views taken along the line B-B' of fig. 5, 7, 9, 11, 13 and 15, respectively. Fig. 10C, 12C, 14C and 16C show cross-sectional views taken along line C-C' of fig. 9, 11, 13 and 15, respectively.

Referring to fig. 5, 6A and 6B, a thin layer structure TS may be formed on the substrate 100. The thin layer structure TS may include a dielectric layer 110 and a semiconductor layer SL stacked on the top surface 100U of the substrate 100. The dielectric layers 110 and the semiconductor layers SL may be alternately and repeatedly stacked in a third direction D3 perpendicular to the top surface 100U of the substrate 100. The lowermost one of the dielectric layers 110 may be interposed between the substrate 100 and the lowermost one of the semiconductor layers SL, but the inventive concept is not limited thereto. The semiconductor layer SL may include, for example, silicon, germanium, silicon germanium, or Indium Gallium Zinc Oxide (IGZO). The dielectric layer 110 may include a material having an etch selectivity with respect to the semiconductor layer SL. Dielectric layer 110 may comprise, for example, silicon nitride.

Vertical holes 120H may be formed in the thin layer structure TS. Each vertical hole 120H may penetrate the thin-layer structure TS. Each vertical hole 120H may expose a top surface of the lowermost dielectric layer 110, but the inventive concept is not limited thereto. The vertical holes 120H may be spaced apart from each other in the first direction D1 within the thin-layer structure TS, and may each have a linear shape extending in the second direction D2.

Referring to fig. 7, 8A and 8B, a gate dielectric layer GI having a substantially uniform thickness covering the inner surface of each vertical hole 120H may be formed. The gate dielectric layer GI may include one or more of a high-k dielectric layer, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. A pre-gate electrode PGE may be formed in each vertical hole 120H. The pre-gate electrode PGE may be formed to partially fill each of the vertical holes 120H and have a substantially uniform thickness covering the inner surface of each of the vertical holes 120H. The gate dielectric layer GI may be interposed between the pre-gate electrode PGE and the inner surface of each vertical hole 120H while covering the bottom surface of each vertical hole 120H. The step of forming the pre-gate electrode PGE may include forming a gate electrode layer on the gate dielectric layer GI partially filling each of the vertical holes 120H, and anisotropically etching the gate electrode layer. The gate electrode layer may include one or more of a metal (tungsten, titanium, tantalum, etc.) and a conductive metal nitride (titanium nitride, tantalum nitride, etc.).

After the pre-gate electrode PGE is formed, a first dielectric layer 120a filling the remaining portion of each vertical hole 120H may be formed. The first dielectric layer 120a may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

Referring to fig. 9, 10A, 10B and 10C, a mask pattern MP may be formed on the thin layer structure TS. The mask pattern MP may include first openings OP1 and second openings OP2, the first openings OP1 having a linear shape extending in the second direction D2, the second openings OP2 being spaced apart from each other in the second direction D2 through the first openings OP 1. The first opening OP1 and the second opening OP2 may be vertically overlapped with each vertical hole 120H. The first and second openings OP1 and OP2 may expose portions of the pre-gate electrode PGE and portions of the first dielectric layer 120a formed in each of the vertical holes 120H. An anisotropic etching process may be performed to remove the exposed portions of the pre-gate electrode PGE and the exposed portions of the first dielectric layer 120 a. The anisotropic etching process may etch the lowermost dielectric layer 110 exposed to each vertical hole 120H, and thus an extended hole ER exposing the substrate 100 may be disposed in the lowermost dielectric layer 110.

When the pre-gate electrode PGE is etched through the anisotropic etching process, the gate electrode GE may be formed in each of the vertical holes 120H. The gate electrode GE may include four gate electrodes spaced apart from each other in the first and second directions D1 and D2 in each vertical hole 120H. The gate electrodes GE may each have a linear shape extending in the third direction D3. A portion of the first dielectric layer 120a may remain in each vertical hole 120H after the first dielectric layer 120a is etched by an anisotropic etching process. Portions of the first dielectric layer 120a may be interposed between the gate electrodes GE adjacent to each other in the first direction D1.

Referring to fig. 11, 12A, 12B, and 12C, the mask pattern MP may be removed. Then, a second dielectric layer 120b filling the remaining portion of each vertical hole 120H may be formed. In an example embodiment, the second dielectric layer 120b may be connected to the first dielectric layer 120a in each vertical hole 120H. A portion of the first dielectric layer 120a and the second dielectric layer 120b may constitute the vertical dielectric pattern 120, and a plurality of vertical dielectric patterns 120 may be respectively formed in the vertical holes 120H. The shield line SM may be formed in the vertical dielectric pattern 120. Each of the shield lines SM may be interposed between the gate electrodes GE adjacent to each other in the first direction D1, and a portion of the vertical dielectric pattern 120 may be interposed between each of the shield lines SM and the gate electrodes GE adjacent to each other in the first direction D1. Each of the shield lines SM may penetrate the vertical dielectric pattern 120 and have a linear shape extending in the third direction D3. The forming of the shield line SM step may include, for example, partially removing the vertical dielectric pattern 120 to form line holes between the gate electrodes GE adjacent to each other in the first direction D1, and forming a shield layer filling the line holes. The shielding layer may comprise, for example, a metal.

Referring to fig. 13, 14A, 14B, and 14C, a pair of trenches TR penetrating the thin layer structure TS may be formed. The pair of trenches TR may extend in the first direction D1 and be spaced apart from each other in the second direction D2. Each of the pair of trenches TR may expose a side surface of the dielectric layer 110 and a side surface of the semiconductor layer SL while exposing the top surface 100U of the substrate 100. The step of forming the trench TR may include, for example, forming a mask pattern defining an area where the trench TR is to be formed on the thin-layer structure TS, and etching the thin-layer structure TS by using the mask pattern as an etching mask.

The side surface of the semiconductor layer SL exposed to each trench TR may be recessed to form a first recessed region R1 between the dielectric layers 110. The step of forming the first recessed region R1 may include etching the semiconductor layer SL, for example, by performing an etching process having an etching selectivity with respect to the dielectric layer 110, the gate dielectric layer GI, and the substrate 100. For example, the etching process may include an isotropic etching process, such as a wet etching process and a dry etching process. An etchant may be supplied through the trench TR to form the first recessed region R1. The first recessed region R1 may extend horizontally from each trench TR. The first recessed regions R1 may extend in the first direction D1 and be spaced apart from each other in the third direction D3. Each of the first recessed regions R1 may be formed between a pair of the dielectric layers 110 adjacent to each other in the third direction D3. Each of the first recess regions R1 may extend in the first direction D1 to expose the gate dielectric layer GI on the side surfaces of the vertical dielectric patterns 120 and also to expose the side surfaces of the semiconductor layer SL between the vertical dielectric patterns 120. Impurities may be doped into a portion of the semiconductor layer SL exposed to the first recessed region R1. Accordingly, the first impurity region SD1 may be formed on the side of each semiconductor layer SL.

Referring to fig. 15, 16A, 16B, and 16C, after the first impurity regions SD1 are formed, first conductive lines CL1 may be formed in the respective first recess regions R1. The step of forming the first conductive line CL1 may include, for example, forming a first conductive layer filling at least a part of the trench TR and the first recessed region R1 in the thin-layer structure TS, and removing the first conductive layer from the trench TR. The first conductive layer may include one or more of a metal (e.g., copper, tungsten, or aluminum) and a metal nitride (e.g., tantalum nitride, titanium nitride, or tungsten nitride). The step of removing the first conductive layer may include etching the first conductive layer until the top surface of the thin-layer structure TS and the inner surface of each trench TR are exposed. When the first conductive layer is etched, the first conductive line CL1 may be locally formed in the first recessed region R1. In example embodiments, the first conductive layer may be anisotropically etched to form the first conductive line CL1 locally in the first recessed region R1. Each of the first conductive lines CL1 may extend in the first direction D1 to contact a side surface of the first impurity region SD1 located between the vertical dielectric patterns 120.

The isolation dielectric pattern 130 may be formed in the corresponding trench TR. The step of forming the isolation dielectric pattern 130 may include, for example, forming an isolation dielectric layer filling the trench TR in the thin layer structure TS, and performing a planarization process on the isolation dielectric layer until a top surface of the thin layer structure TS is exposed. The isolation dielectric pattern 130 may be locally formed in the trench TR through a planarization process. The isolation dielectric patterns 130 may extend in the first direction D1 and be spaced apart from each other in the second direction D2 through the first conductive line CL 1. The isolation dielectric pattern 130 may include, for example, one or more of oxide, nitride, and oxynitride.

Holes 140H penetrating the thin-layer structure TS may be formed. The holes 140H may be spaced apart from each other in the first direction D1 between the isolation dielectric patterns 130. The holes 140H and the vertical dielectric patterns 120 may be alternately arranged in the first direction D1. Each hole 140H may expose a side surface of the dielectric layer 110 and a side surface of the semiconductor layer SL of the thin-layer structure TS while exposing the top surface 100U of the substrate 100. The step of forming the hole 140H may include, for example, forming a mask pattern defining an area where the hole 140H is to be formed on the thin-layer structure TS, and etching the thin-layer structure TS by using the mask pattern as an etching mask.

The side surface of the semiconductor layer SL exposed to each hole 140H may be recessed to form a second recessed region R2 between the dielectric layers 110. The step of forming the second recessed region R2 may include etching the semiconductor layer SL, for example, by performing an etching process having an etching selectivity with respect to the dielectric layer 110, the gate dielectric layer GI, and the substrate 100. For example, the etching process may include an isotropic etching process, such as a wet etching process and a dry etching process. An etchant may be supplied through the hole 140H to form the second recessed region R2. A second recessed region R2 may extend horizontally from each aperture 140H. Each of the second recessed regions R2 may be formed between a pair of dielectric layers 110 adjacent to each other in the third direction D3 and between a pair of vertical dielectric patterns 120 adjacent to each other in the first direction D1. Impurities may be doped into a portion of the semiconductor layer SL exposed to the second recessed region R2. Accordingly, the second impurity region SD2 may be formed on the side of each semiconductor layer SL. A portion of each semiconductor layer SL may remain between the first impurity region SD1 and the second impurity region SD 2. This portion of each semiconductor layer SL may be referred to as a channel region CH. The semiconductor pattern SP may be composed of a first impurity region SD1, a second impurity region SD2, and a channel region CH between the first impurity region SD1 and the second impurity region SD 2.

Referring back to fig. 3, 4A, 4B and 4C, an electrode EP may be formed on a side surface of the semiconductor pattern SP. Its side is exposed to the second recessed region R2. The step of forming the electrode EP may include forming an electrode layer filling at least a portion of each hole 140H and the second recessed region R2 in the thin-layer structure TS, removing the electrode layer from each hole 140H, and recessing the electrode layer until the electrode layer remains to have a predetermined thickness in each second recessed region R2. Thereafter, a variable resistance element VR may be formed in each of the second recessed regions R2. The step of forming the variable resistive element VR may include forming a variable resistive material layer filling at least a portion of each hole 140H and the second recessed region R2 in the thin-layer structure TS, and removing the variable resistive material layer from each hole 140H. The step of removing the variable resistance material layer may include etching the variable resistance material layer until the inner surface of each hole 140H is exposed. Therefore, the variable resistance element VR may be locally formed in each of the second recessed regions R2.

The semiconductor pattern SP, the electrode EP, and the variable resistive element VR may be horizontally arranged in a direction (e.g., the second direction D2) parallel to the top surface 100U of the substrate 100. The semiconductor pattern SP, the electrode EP, and the variable resistance element VR may constitute a memory cell MC.

Fig. 17 illustrates a simplified perspective view showing a variable resistance memory device according to some example embodiments of the inventive concepts. Fig. 18A illustrates a plan view showing the variable resistance memory device of fig. 17. Fig. 18B shows a cross-sectional view taken along line I-I' of fig. 18A. Differences from the variable resistance memory device discussed with reference to fig. 1, 2A, and 2B will be mainly described below.

Referring to fig. 17, 18A and 18B, a first conductive line CL1 and a second conductive line CL2 crossing the first conductive line CL1 may be disposed on the substrate 100. The first conductive lines CL1 may extend in a third direction D3 perpendicular to the top surface 100U of the substrate 100 and may be spaced apart from each other in a first direction D1 parallel to the top surface 100U of the substrate 100. The second conductive lines CL2 may extend in the first direction D1 and be spaced apart from each other in the third direction D3. The first conductive line CL1 may include a first sub-conductive line CL1a disposed on a side of the second conductive line CL2, and may further include a second sub-conductive line CL1b disposed on an opposite side of the second conductive line CL 2. The second sub-conductive line CL1b may be spaced apart from the first sub-conductive line CL1a in a second direction D2 parallel to the top surface 100U of the substrate 100 and different from the first direction D1. The second conductive line CL2 may be disposed between the first sub-conductive line CL1a and the second sub-conductive line CL1 b.

The memory cell MC may be disposed at an intersection between the first conductive line CL1 and the second conductive line CL 2. For example, each memory cell MC may be disposed at an intersection between a corresponding one of the first conductive lines CL1 and a corresponding one of the second conductive lines CL 2. The memory cells MC may include first memory cells MC1 at respective intersections between the first sub-conductive lines CL1a and the second conductive lines CL2, and may further include second memory cells MC2 at respective intersections between the second sub-conductive lines CL1b and the second conductive lines CL 2. The first memory cells MC1 may be spaced apart from each other in the first and third directions D1 and D3 between the first sub-conductive line CL1a and the second conductive line CL 2. Each first memory cell MC1 may be connected to a respective first sub-conductive line CL1a and a respective second conductive line CL 2. The second memory cells MC2 may be spaced apart from each other in the first and third directions D1 and D3 between the second sub-conductive line CL1b and the second conductive line CL 2. Each second memory cell MC2 may be connected to a corresponding second sub-conductive line CL1b and a corresponding second conductive line CL 2. The second memory cell MC2 may be spaced apart from the first memory cell MC1 in the second direction D2.

Each memory cell MC may include a variable resistance element VR and a selection element SW. The variable resistance element VR and the selection element SW may be horizontally arranged in the second direction D2. The variable resistance element VR and the selection element SW included in each of the first memory cells MC1 may be connected in series between the corresponding first sub-conductive line CL1a and the corresponding second conductive line CL 2. The variable resistance element VR and the selection element SW included in each of the second memory cells MC2 may be connected in series between the corresponding second sub-conductive line CL1b and the corresponding second conductive line CL 2.

Each first memory cell MC1 and its corresponding second memory cell MC2 may be symmetrical to each other with respect to the corresponding second conductive line CL 2. In example embodiments, each of the first memory cells MC1, the corresponding second memory cell MC2, and the corresponding second conductive line CL2 may be located at the same level in the third direction D3 from the top surface 100U of the substrate 100. For example, the variable resistive element VR of each first memory cell MC1 and the variable resistive element VR of each second memory cell MC2 may be commonly connected to the corresponding second conductive line CL2, and the selection element SW of each first memory cell MC1 and the selection element SW of each second memory cell MC2 may be connected to the corresponding first sub-conductive line CL1a and the corresponding second sub-conductive line CL1b, respectively.

Each memory cell MC may further include a first electrode EP1 between the selection element SW and the first conductive line CL1, a second electrode EP2 between the variable resistance element VR and the selection element SW, and a third electrode EP3 between the variable resistance element VR and the second conductive line CL 2. The first, second and third electrodes EP1, EP2, EP3 may comprise a conductive material, such as one or more of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN and TiO. The selection element SW may be a diode or a device operating based on a threshold switching phenomenon, and may have a non-linear I-V curve (e.g., an S-type I-V curve). For example, the selection element SW may be an OTS (Ovonic Threshold Switch) device having an Ovonic characteristic. In an example embodiment, the OTS device may be a bidirectional switch.

Fig. 19 illustrates a simplified perspective view showing a variable resistance memory device according to some example embodiments of the inventive concepts. Fig. 20A illustrates a plan view showing the variable resistance memory device of fig. 19. Fig. 20B shows a cross-sectional view taken along line I-I' of fig. 20A. Differences from the variable resistance memory device discussed with reference to fig. 17, 18A, and 18B will be mainly described below.

Referring to fig. 19, 20A and 20B, according to the present embodiment, the second conductive line CL2 may include a third sub-conductive line CL2a adjacent to the first sub-conductive line CL1a, and may further include a fourth sub-conductive line CL2B adjacent to the second sub-conductive line CL 1B. The third sub-wires CL2a may extend in the first direction D1 and be spaced apart from each other in the third direction D3. The fourth sub-wires CL2b may extend in the first direction D1 and may be spaced apart from each other in the third direction D3. The fourth sub-conductive line CL2b may be spaced apart from the third sub-conductive line CL2a in the second direction D2 via the line dielectric pattern 200. The line dielectric pattern 200 may include, for example, one or more of oxide, nitride, and oxynitride.

The first memory cell MC1 may be disposed at a corresponding intersection between the first sub-conductive line CL1a and the third sub-conductive line CL2a, and the second memory cell MC2 may be disposed at a corresponding intersection between the second sub-conductive line CL1b and the fourth sub-conductive line CL2 b. Each first memory cell MC1 may be connected to a respective first sub-conductive line CL1a and a respective third sub-conductive line CL2a, and each second memory cell MC2 may be connected to a respective second sub-conductive line CL1b and a respective fourth sub-conductive line CL2 b. The first sub-conductive line CL1a, the first memory cell MC1, and the third sub-conductive line CL2a may be disposed symmetrically with the second sub-conductive line CL1b, the second memory cell MC2, and the fourth sub-conductive line CL2b, respectively, with respect to the line dielectric pattern 200.

Fig. 21 illustrates a simplified perspective view showing a variable resistance memory device according to some example embodiments of the inventive concepts. Fig. 22A illustrates a plan view showing the variable resistance memory device of fig. 21. Fig. 22B shows a cross-sectional view taken along line I-I' of fig. 22A. Differences from the variable resistance memory device discussed with reference to fig. 17, 18A, and 18B will be mainly described below.

Referring to fig. 21, 22A, and 22B, according to the present embodiment, the first sub-wires CL1a may extend in the first direction D1 and may be spaced apart from each other in the third direction D3. The second sub-wires CL1b may extend in the first direction D1 and may be spaced apart from each other in the third direction D3. The second sub-conductive line CL1b may be spaced apart from the first sub-conductive line CL1a in the second direction D2. The second conductive lines CL2 may extend in the third direction D3 and may be spaced apart from each other in the first direction D1. According to the present embodiment, the variable resistance memory device may be configured substantially the same as the variable resistance memory device discussed with reference to fig. 17, 18A, and 18B, except for the arrangement of the first conductive line CL1 and the second conductive line CL 2.

Fig. 23 illustrates a simplified perspective view showing a variable resistance memory device according to some example embodiments of the inventive concepts. Fig. 24A illustrates a plan view showing the variable resistance memory device of fig. 23. Fig. 24B shows a cross-sectional view taken along line I-I' of fig. 24A. Differences from the variable resistance memory device discussed with reference to fig. 17, 18A, and 18B will be mainly described below.

Referring to fig. 23, 24A and 24B, according to the present embodiment, the first sub-wires CL1a may extend in the first direction D1 and may be spaced apart from each other in the third direction D3. The second sub-wires CL1b may extend in the first direction D1 and may be spaced apart from each other in the third direction D3. The second sub-conductive line CL1b may be spaced apart from the first sub-conductive line CL1a in the second direction D2. The second conductive line CL2 may include a third sub-conductive line CL2a adjacent to the first sub-conductive line CL1a, and may further include a fourth sub-conductive line CL2b adjacent to the second sub-conductive line CL1 b. The third sub-wires CL2a may extend in the third direction D3 and may be spaced apart from each other in the first direction D1. The fourth sub-conductors CL2b may extend in the third direction D3 and may be spaced apart from each other in the first direction D1. The fourth sub-conductive line CL2b may be spaced apart from the third sub-conductive line CL2a in the second direction D2 via the line dielectric pattern 200. According to the present embodiment, the variable resistance memory device may be configured substantially the same as the variable resistance memory device discussed with reference to fig. 19, 20A, and 20B, except for the arrangement of the first conductive line CL1 and the second conductive line CL 2.

Fig. 25 illustrates a plan view showing a variable resistance memory device according to some example embodiments of the inventive concepts. Fig. 26A shows a cross-sectional view taken along line a-a' of fig. 25. Fig. 26B shows a cross-sectional view taken along line B-B' of fig. 25. Differences from the variable resistance memory device discussed with reference to fig. 3, 4A, 4B, and 4C will be mainly described below.

Referring to fig. 25, 26A, and 26B, a stacked structure SS may be disposed on the substrate 100. The substrate 100 may be provided thereon with the isolation dielectric patterns 130 on opposite sides of the stacked structure SS. The isolation dielectric pattern 130 may accordingly cover the opposite side surface SS _ S of the stacked structure SS. The isolation dielectric patterns 130 may extend in the first direction D1 and may be spaced apart from each other in the second direction D2 through the stacked structure SS. The stacked structure SS may be spaced apart from an adjacent stacked structure SS through the isolation dielectric pattern 130.

The stacked structure SS may include dielectric layers 110 and first conductive lines CL1 alternately stacked in the third direction D3. The first conductive line CL1 may extend in the first direction D1. The first conductive line CL1 may include a first sub-conductive line CL1a and a second sub-conductive line CL1 b. The first sub-wires CL1a may extend in the first direction D1 and may be spaced apart from each other in the third direction D3. The first sub-conductive lines CL1a may be separated from each other by a dielectric layer 110 therebetween. The second sub-wires CL1b may extend in the first direction D1 and may be spaced apart from each other in the third direction D3. The second sub-conductive lines CL1b may be separated from each other by a dielectric layer 110 therebetween. The second sub-conductive line CL1b may be spaced apart from the first sub-conductive line CL1a in the second direction D2.

The stack structure SS may include a second conductive line CL2 between the first sub-conductive line CL1a and the second sub-conductive line CL1 b. The second conductive lines CL2 may extend in the third direction D3 and may be spaced apart from each other in the first direction D1. The second conductive line CL2 may cross the first sub-conductive line CL1a and the second sub-conductive line CL1 b. Each of the second conductive lines CL2 may penetrate the dielectric layer 110.

The stacked structure SS may include the vertical dielectric pattern 120 between the first sub-conductive line CL1a and the second sub-conductive line CL1 b. The vertical dielectric patterns 120 may extend in the third direction D3 and may be spaced apart from each other in the first direction D1. The second conductive line CL2 and the vertical dielectric pattern 120 may be alternately arranged in the first direction D1 between the first sub-conductive line CL1a and the second sub-conductive line CL1 b.

The stack structure SS may include memory cells MC located at respective intersections between the first conductive lines CL1 and the second conductive lines CL 2. The memory cells MC may include first memory cells MC1 at respective intersections between the first sub-conductive lines CL1a and the second conductive lines CL2, and may further include second memory cells MC2 at respective intersections between the second sub-conductive lines CL1b and the second conductive lines CL 2. Each memory cell MC may include a variable resistance element VR, a selection element SW, a first electrode EP1 between the selection element SW and a corresponding first conductive line CL1, a second electrode EP2 between the variable resistance element VR and the selection element SW, and a third electrode EP3 between the variable resistance element VR and a corresponding second conductive line CL 2. The variable resistive element VR, the selection element SW, and the first to third electrodes EP1 to EP3 may be horizontally arranged in a direction (e.g., the second direction D2) parallel to the top surface 100U of the substrate 100. In example embodiments, the variable resistance element VR, the selection element SW, and the first to third electrodes EP1 to EP3 may be disposed at the same level from the top surface 100U of the substrate 100 in the third direction D3. Each memory cell MC may be locally disposed between a pair of vertical dielectric patterns 120 adjacent to each other in the first direction D1 and between a pair of dielectric layers 110 adjacent to each other in the third direction D3. Accordingly, the variable resistive element VR, the selection element SW, and the first to third electrodes EP1 to EP3 may be horizontally arranged between the pair of vertical dielectric patterns 120 in the first direction D1 and between the pair of dielectric layers 110 in the third direction D3 in the second direction D2. The second memory cell MC2 may be configured symmetrically with the first memory cell MC1 with respect to the second conductive line CL 2.

As discussed with reference to fig. 1, 2A, and 2B, the variable resistive element VR may include a material that stores data based on a change in resistance. In some embodiments, the selection element SW may be a diode. For example, the selection element SW may comprise a silicon diode in which p-type Si and n-type Si are bonded together or in which p-type NiO_xAnd n-type TiO_xOr p-type CuO_xAnd n-type TiO_xOxide diodes bonded together. In other embodiments, the selection element SW may be a device based on a threshold switching phenomenon having a non-linear I-V curve (e.g., an S-shaped I-V curve). For example, the selection element SW may be an OTS (ovonic threshold switch) device having an ovonic characteristic. In an example embodiment, the OTS device may be a bidirectional switch. In this case, the selection element SW may include a chalcogenide material and may be in a substantially amorphous state. In the present description, the phrase "substantially amorphous" may not exclude the presence of locally crystalline grain boundaries or locally crystalline portions. The chalcogenide material may include a compound In which one or more of Te and Se (chalcogen) is combined with one or more of Ge, Sb, Bi, Al, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, and P. For example, the chalcogenide material may include one or more of AsTe, AsSe, GeTe, SnTe, GeSe, SnTe, SnSe, ZnTe, AsTeSe, AsTeGe, AsSeGe, AsTeGeSe, AsSeGeSi, AsTeGeSi, AsTeGeGeGeGeGeS, AsTeGeSiIn, AsTeGeSiP, AsTeGeSiSbS, AsTeGeSiSbP, AsTeGeSeSeSb, AsTeSeGeSeSeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, and GeAsBiSe. In certain embodiments, the selection element SW may also include impurities, for example, one or more of C, N, B and O. According to the present embodiment, the selection element SW of the variable resistance memory device is not limited to the contents discussed with reference to fig. 3, 4A, 4B and 4C.

According to the concept of the present invention, memory cells may be three-dimensionally stacked on a substrate, and each memory cell may include a variable resistance element and a selection element arranged horizontally. Accordingly, a variable resistance memory device having an increased degree of integration can be easily provided.

The above description provides some example embodiments for explaining the inventive concept. Accordingly, the inventive concept is not limited to the above-described embodiments, and it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and essential characteristics of the inventive concept.